mailbox changes for v5.5
- omap : misc - catch error returned from pm_runtime_put_sync - hisi : misc - drop .owner from platform_driver - stm : change how wakeup is handled - imx : fix - bailout on error and nuke correct irq - imx : add support for imx7ulp platform -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEE6EwehDt/SOnwFyTyf9lkf8eYP5UFAl3jUDYACgkQf9lkf8eY P5VVsQ//drP3rGcUKUzIh0zhO478YlpjNy/kTZ93rUAFmN9JSL/MzBexM8fTcTrD O+0JAU8P4a+qANxqKpRUxDsLROaD8Vq8q+oSGUgtr8y/XGDlVb4O74LLQy/277U8 FFDzUkQYtYsRBOv6fQU3u5cZt4Q9soVFU/+w10sF3Px4UiZOox+qsBKP5eik6xBe EaxMM8ear03ZA3nHq/EK3aHEXfNSu3xYfusS4BLEIFenmAaVRl9pCTcEdkQRoDea Y6cUWX7KgJWn8+cghtLmHHMz154Q5j+6CqFnEPRZbP/JvD9sHqFPRNxYlec/i+yL gQagKlj3OdCLUzbolxayhUO/SDmTHeUsvDClZMy+CpROUKOmm1yAcDlnsXmP6wtg LTGHB/WFtYFNBMko9nBDZS2HyzUtEo9s7uHjTktXn0MRJvadifrJPB+eYaXZADyA wsbbqbxn4DFeATw24mYBcNAkdLxsXYOO0a7Gl2v+NPnh6aNHcmxeiFUF2jAa8o4N ACXeQiUofMwKahIQu228zBPgT35JqhJJpPqesYoce1TmaHQiCqiocf0wv3aENFrZ WiEFLQ/N6k7NSeXo8b1KA5XiqA8Sry9SJlEeJfv0uakNPXihsv+cC5a6EANzrDzM ahZ6KXJ4vIYrpCl7o7wcZkXydjlOffgB+6qCXpKOWJBxayjmF08= =KJ0/ -----END PGP SIGNATURE----- Merge tag 'mailbox-v5.5' of git://git.linaro.org/landing-teams/working/fujitsu/integration Pull mailbox updates from Jassi Brar: - omap : misc - catch error returned from pm_runtime_put_sync - hisi : misc - drop .owner from platform_driver - stm : change how wakeup is handled - imx : fix - bailout on error and nuke correct irq - imx : add support for imx7ulp platform * tag 'mailbox-v5.5' of git://git.linaro.org/landing-teams/working/fujitsu/integration: mailbox: imx: add support for imx v1 mu dt-bindings: mailbox: imx-mu: add imx7ulp MU support mailbox: imx: Clear the right interrupts at shutdown mailbox: imx: Fix Tx doorbell shutdown path mailbox: stm32-ipcc: Update wakeup management mailbox: no need to set .owner platform_driver_register mailbox/omap: Handle if CONFIG_PM is disabled
This commit is contained in:
commit
43fd4bd72c
@ -21,6 +21,8 @@ Required properties:
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imx6sx, imx7s, imx8qxp, imx8qm.
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The "fsl,imx6sx-mu" compatible is seen as generic and should
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be included together with SoC specific compatible.
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There is a version 1.0 MU on imx7ulp, use "fsl,imx7ulp-mu"
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compatible to support it.
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- reg : Should contain the registers location and length
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- interrupts : Interrupt number. The interrupt specifier format depends
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on the interrupt controller parent.
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@ -354,7 +354,6 @@ static int hi6220_mbox_probe(struct platform_device *pdev)
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static struct platform_driver hi6220_mbox_driver = {
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.driver = {
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.name = "hi6220-mbox",
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.owner = THIS_MODULE,
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.of_match_table = hi6220_mbox_of_match,
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},
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.probe = hi6220_mbox_probe,
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@ -12,19 +12,11 @@
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#include <linux/of_device.h>
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#include <linux/slab.h>
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/* Transmit Register */
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#define IMX_MU_xTRn(x) (0x00 + 4 * (x))
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/* Receive Register */
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#define IMX_MU_xRRn(x) (0x10 + 4 * (x))
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/* Status Register */
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#define IMX_MU_xSR 0x20
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#define IMX_MU_xSR_GIPn(x) BIT(28 + (3 - (x)))
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#define IMX_MU_xSR_RFn(x) BIT(24 + (3 - (x)))
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#define IMX_MU_xSR_TEn(x) BIT(20 + (3 - (x)))
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#define IMX_MU_xSR_BRDIP BIT(9)
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/* Control Register */
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#define IMX_MU_xCR 0x24
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/* General Purpose Interrupt Enable */
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#define IMX_MU_xCR_GIEn(x) BIT(28 + (3 - (x)))
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/* Receive Interrupt Enable */
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@ -44,6 +36,13 @@ enum imx_mu_chan_type {
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IMX_MU_TYPE_RXDB, /* Rx doorbell */
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};
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struct imx_mu_dcfg {
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u32 xTR[4]; /* Transmit Registers */
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u32 xRR[4]; /* Receive Registers */
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u32 xSR; /* Status Register */
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u32 xCR; /* Control Register */
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};
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struct imx_mu_con_priv {
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unsigned int idx;
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char irq_desc[IMX_MU_CHAN_NAME_SIZE];
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@ -61,12 +60,27 @@ struct imx_mu_priv {
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struct mbox_chan mbox_chans[IMX_MU_CHANS];
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struct imx_mu_con_priv con_priv[IMX_MU_CHANS];
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const struct imx_mu_dcfg *dcfg;
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struct clk *clk;
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int irq;
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bool side_b;
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};
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static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = {
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.xTR = {0x0, 0x4, 0x8, 0xc},
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.xRR = {0x10, 0x14, 0x18, 0x1c},
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.xSR = 0x20,
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.xCR = 0x24,
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};
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static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
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.xTR = {0x20, 0x24, 0x28, 0x2c},
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.xRR = {0x40, 0x44, 0x48, 0x4c},
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.xSR = 0x60,
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.xCR = 0x64,
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};
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static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox)
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{
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return container_of(mbox, struct imx_mu_priv, mbox);
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@ -88,10 +102,10 @@ static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, u32 set, u32 clr)
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u32 val;
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spin_lock_irqsave(&priv->xcr_lock, flags);
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val = imx_mu_read(priv, IMX_MU_xCR);
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val = imx_mu_read(priv, priv->dcfg->xCR);
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val &= ~clr;
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val |= set;
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imx_mu_write(priv, val, IMX_MU_xCR);
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imx_mu_write(priv, val, priv->dcfg->xCR);
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spin_unlock_irqrestore(&priv->xcr_lock, flags);
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return val;
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@ -111,8 +125,8 @@ static irqreturn_t imx_mu_isr(int irq, void *p)
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struct imx_mu_con_priv *cp = chan->con_priv;
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u32 val, ctrl, dat;
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ctrl = imx_mu_read(priv, IMX_MU_xCR);
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val = imx_mu_read(priv, IMX_MU_xSR);
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ctrl = imx_mu_read(priv, priv->dcfg->xCR);
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val = imx_mu_read(priv, priv->dcfg->xSR);
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switch (cp->type) {
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case IMX_MU_TYPE_TX:
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@ -138,10 +152,10 @@ static irqreturn_t imx_mu_isr(int irq, void *p)
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imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx));
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mbox_chan_txdone(chan, 0);
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} else if (val == IMX_MU_xSR_RFn(cp->idx)) {
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dat = imx_mu_read(priv, IMX_MU_xRRn(cp->idx));
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dat = imx_mu_read(priv, priv->dcfg->xRR[cp->idx]);
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mbox_chan_received_data(chan, (void *)&dat);
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} else if (val == IMX_MU_xSR_GIPn(cp->idx)) {
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imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), IMX_MU_xSR);
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imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), priv->dcfg->xSR);
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mbox_chan_received_data(chan, NULL);
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} else {
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dev_warn_ratelimited(priv->dev, "Not handled interrupt\n");
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@ -159,7 +173,7 @@ static int imx_mu_send_data(struct mbox_chan *chan, void *data)
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switch (cp->type) {
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case IMX_MU_TYPE_TX:
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imx_mu_write(priv, *arg, IMX_MU_xTRn(cp->idx));
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imx_mu_write(priv, *arg, priv->dcfg->xTR[cp->idx]);
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imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0);
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break;
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case IMX_MU_TYPE_TXDB:
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@ -214,11 +228,24 @@ static void imx_mu_shutdown(struct mbox_chan *chan)
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struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
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struct imx_mu_con_priv *cp = chan->con_priv;
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if (cp->type == IMX_MU_TYPE_TXDB)
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if (cp->type == IMX_MU_TYPE_TXDB) {
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tasklet_kill(&cp->txdb_tasklet);
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return;
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}
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imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx) |
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IMX_MU_xCR_RIEn(cp->idx) | IMX_MU_xCR_GIEn(cp->idx));
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switch (cp->type) {
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case IMX_MU_TYPE_TX:
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imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx));
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break;
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case IMX_MU_TYPE_RX:
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imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_RIEn(cp->idx));
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break;
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case IMX_MU_TYPE_RXDB:
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imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_GIEn(cp->idx));
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break;
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default:
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break;
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}
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free_irq(priv->irq, chan);
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}
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@ -257,7 +284,7 @@ static void imx_mu_init_generic(struct imx_mu_priv *priv)
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return;
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/* Set default MU configuration */
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imx_mu_write(priv, 0, IMX_MU_xCR);
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imx_mu_write(priv, 0, priv->dcfg->xCR);
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}
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static int imx_mu_probe(struct platform_device *pdev)
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@ -265,6 +292,7 @@ static int imx_mu_probe(struct platform_device *pdev)
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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struct imx_mu_priv *priv;
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const struct imx_mu_dcfg *dcfg;
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unsigned int i;
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int ret;
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@ -282,6 +310,11 @@ static int imx_mu_probe(struct platform_device *pdev)
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if (priv->irq < 0)
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return priv->irq;
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dcfg = of_device_get_match_data(dev);
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if (!dcfg)
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return -EINVAL;
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priv->dcfg = dcfg;
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priv->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(priv->clk)) {
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if (PTR_ERR(priv->clk) != -ENOENT)
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@ -335,7 +368,8 @@ static int imx_mu_remove(struct platform_device *pdev)
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}
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static const struct of_device_id imx_mu_dt_ids[] = {
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{ .compatible = "fsl,imx6sx-mu" },
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{ .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp },
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{ .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx },
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{ },
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};
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MODULE_DEVICE_TABLE(of, imx_mu_dt_ids);
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@ -868,7 +868,7 @@ static int omap_mbox_probe(struct platform_device *pdev)
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dev_info(mdev->dev, "omap mailbox rev 0x%x\n", l);
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ret = pm_runtime_put_sync(mdev->dev);
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if (ret < 0)
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if (ret < 0 && ret != -ENOSYS)
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goto unregister;
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devm_kfree(&pdev->dev, finfoblk);
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@ -52,7 +52,6 @@ struct stm32_ipcc {
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struct clk *clk;
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spinlock_t lock; /* protect access to IPCC registers */
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int irqs[IPCC_IRQ_NUM];
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int wkp;
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u32 proc_id;
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u32 n_chans;
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u32 xcr;
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@ -282,16 +281,9 @@ static int stm32_ipcc_probe(struct platform_device *pdev)
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/* wakeup */
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if (of_property_read_bool(np, "wakeup-source")) {
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ipcc->wkp = platform_get_irq_byname(pdev, "wakeup");
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if (ipcc->wkp < 0) {
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if (ipcc->wkp != -EPROBE_DEFER)
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dev_err(dev, "could not get wakeup IRQ\n");
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ret = ipcc->wkp;
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goto err_clk;
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}
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device_set_wakeup_capable(dev, true);
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ret = dev_pm_set_dedicated_wake_irq(dev, ipcc->wkp);
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ret = dev_pm_set_wake_irq(dev, ipcc->irqs[IPCC_IRQ_RX]);
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if (ret) {
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dev_err(dev, "Failed to set wake up irq\n");
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goto err_init_wkp;
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@ -334,10 +326,10 @@ static int stm32_ipcc_probe(struct platform_device *pdev)
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return 0;
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err_irq_wkp:
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if (ipcc->wkp)
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if (of_property_read_bool(np, "wakeup-source"))
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dev_pm_clear_wake_irq(dev);
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err_init_wkp:
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device_init_wakeup(dev, false);
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device_set_wakeup_capable(dev, false);
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err_clk:
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clk_disable_unprepare(ipcc->clk);
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return ret;
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@ -345,27 +337,17 @@ err_clk:
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static int stm32_ipcc_remove(struct platform_device *pdev)
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{
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struct stm32_ipcc *ipcc = platform_get_drvdata(pdev);
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struct device *dev = &pdev->dev;
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if (ipcc->wkp)
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if (of_property_read_bool(dev->of_node, "wakeup-source"))
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dev_pm_clear_wake_irq(&pdev->dev);
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device_init_wakeup(&pdev->dev, false);
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device_set_wakeup_capable(dev, false);
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return 0;
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}
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#ifdef CONFIG_PM_SLEEP
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static void stm32_ipcc_set_irq_wake(struct device *dev, bool enable)
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{
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struct stm32_ipcc *ipcc = dev_get_drvdata(dev);
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unsigned int i;
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if (device_may_wakeup(dev))
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for (i = 0; i < IPCC_IRQ_NUM; i++)
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irq_set_irq_wake(ipcc->irqs[i], enable);
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}
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static int stm32_ipcc_suspend(struct device *dev)
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{
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struct stm32_ipcc *ipcc = dev_get_drvdata(dev);
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@ -373,8 +355,6 @@ static int stm32_ipcc_suspend(struct device *dev)
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ipcc->xmr = readl_relaxed(ipcc->reg_proc + IPCC_XMR);
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ipcc->xcr = readl_relaxed(ipcc->reg_proc + IPCC_XCR);
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stm32_ipcc_set_irq_wake(dev, true);
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return 0;
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}
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@ -382,8 +362,6 @@ static int stm32_ipcc_resume(struct device *dev)
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{
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struct stm32_ipcc *ipcc = dev_get_drvdata(dev);
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stm32_ipcc_set_irq_wake(dev, false);
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writel_relaxed(ipcc->xmr, ipcc->reg_proc + IPCC_XMR);
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writel_relaxed(ipcc->xcr, ipcc->reg_proc + IPCC_XCR);
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