usb: dwc2: Add hibernation updates for ULPI PHY
Added programmming of ULPI_LATCH_EN_DURING_HIB_ENTRY bit in GPWRDN register when using ULPI PHY during entry/exit to/from hibernation. This bit set to 1 during entering to hibernation if ULPI PHY used. On exiting from hibernation this bit reset to 0. Applicable for both host and device modes. Signed-off-by: Minas Harutyunyan <Minas.Harutyunyan@synopsys.com> Link: https://lore.kernel.org/r/e024cb39a7177ec201c873df25ca6365f2e55947.1708948356.git.Minas.Harutyunyan@synopsys.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -249,6 +249,11 @@ void dwc2_hib_restore_common(struct dwc2_hsotg *hsotg, int rem_wakeup,
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dwc2_writel(hsotg, gpwrdn, GPWRDN);
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udelay(10);
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/* Reset ULPI latch */
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gpwrdn = dwc2_readl(hsotg, GPWRDN);
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gpwrdn &= ~GPWRDN_ULPI_LATCH_EN_DURING_HIB_ENTRY;
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dwc2_writel(hsotg, gpwrdn, GPWRDN);
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/* Disable PMU interrupt */
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gpwrdn = dwc2_readl(hsotg, GPWRDN);
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gpwrdn &= ~GPWRDN_PMUINTSEL;
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@ -705,6 +705,11 @@ static inline void dwc_handle_gpwrdn_disc_det(struct dwc2_hsotg *hsotg,
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gpwrdn_tmp &= ~GPWRDN_PMUINTSEL;
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dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
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/* Reset ULPI latch */
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gpwrdn = dwc2_readl(hsotg, GPWRDN);
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gpwrdn &= ~GPWRDN_ULPI_LATCH_EN_DURING_HIB_ENTRY;
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dwc2_writel(hsotg, gpwrdn, GPWRDN);
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/* De-assert Wakeup Logic */
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gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
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gpwrdn_tmp &= ~GPWRDN_PMUACTV;
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@ -5309,6 +5309,8 @@ void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg)
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int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg)
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{
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u32 gpwrdn;
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u32 gusbcfg;
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u32 pcgcctl;
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int ret = 0;
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/* Change to L2(suspend) state */
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@ -5328,6 +5330,22 @@ int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg)
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}
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gpwrdn = GPWRDN_PWRDNRSTN;
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udelay(10);
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gusbcfg = dwc2_readl(hsotg, GUSBCFG);
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if (gusbcfg & GUSBCFG_ULPI_UTMI_SEL) {
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/* ULPI interface */
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gpwrdn |= GPWRDN_ULPI_LATCH_EN_DURING_HIB_ENTRY;
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}
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dwc2_writel(hsotg, gpwrdn, GPWRDN);
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udelay(10);
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/* Suspend the Phy Clock */
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pcgcctl = dwc2_readl(hsotg, PCGCTL);
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pcgcctl |= PCGCTL_STOPPCLK;
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dwc2_writel(hsotg, pcgcctl, PCGCTL);
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udelay(10);
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gpwrdn = dwc2_readl(hsotg, GPWRDN);
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gpwrdn |= GPWRDN_PMUACTV;
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dwc2_writel(hsotg, gpwrdn, GPWRDN);
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udelay(10);
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@ -5428,6 +5446,11 @@ int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
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if (reset)
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dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK);
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/* Reset ULPI latch */
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gpwrdn = dwc2_readl(hsotg, GPWRDN);
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gpwrdn &= ~GPWRDN_ULPI_LATCH_EN_DURING_HIB_ENTRY;
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dwc2_writel(hsotg, gpwrdn, GPWRDN);
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/* De-assert Wakeup Logic */
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gpwrdn = dwc2_readl(hsotg, GPWRDN);
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gpwrdn &= ~GPWRDN_PMUACTV;
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@ -5503,6 +5503,11 @@ int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg)
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gusbcfg = dwc2_readl(hsotg, GUSBCFG);
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if (gusbcfg & GUSBCFG_ULPI_UTMI_SEL) {
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/* ULPI interface */
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udelay(10);
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gpwrdn = dwc2_readl(hsotg, GPWRDN);
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gpwrdn |= GPWRDN_ULPI_LATCH_EN_DURING_HIB_ENTRY;
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dwc2_writel(hsotg, gpwrdn, GPWRDN);
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udelay(10);
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/* Suspend the Phy Clock */
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pcgcctl = dwc2_readl(hsotg, PCGCTL);
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pcgcctl |= PCGCTL_STOPPCLK;
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@ -5609,6 +5614,11 @@ int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup,
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dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
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dwc2_writel(hsotg, hr->hcfg, HCFG);
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/* Reset ULPI latch */
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gpwrdn = dwc2_readl(hsotg, GPWRDN);
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gpwrdn &= ~GPWRDN_ULPI_LATCH_EN_DURING_HIB_ENTRY;
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dwc2_writel(hsotg, gpwrdn, GPWRDN);
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/* De-assert Wakeup Logic */
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gpwrdn = dwc2_readl(hsotg, GPWRDN);
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gpwrdn &= ~GPWRDN_PMUACTV;
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