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PCI: j721e: Add PCIe 4x lane selection support

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Add support for setting of two-bit field that allows selection of 4x lane
PCIe which was previously limited to only 2x lanes.

Link: https://lore.kernel.org/linux-pci/20231128054402.2155183-5-s-vadapalli@ti.com
Signed-off-by: Matt Ranostay <mranostay@ti.com>
Signed-off-by: Achal Verma <a-verma1@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
This commit is contained in:
Matt Ranostay 2023-11-28 11:14:01 +05:30 committed by Krzysztof Wilczyński
parent 3ac7f14084
commit 4490f559f7
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GPG Key ID: 7C64768D3DE334E7
1 changed files with 8 additions and 2 deletions
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10
drivers/pci/controller/cadence/pci-j721e.c
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@ -42,7 +42,6 @@ enum link_status {
};
#define J721E_MODE_RC BIT(7)
#define LANE_COUNT_MASK BIT(8)
#define LANE_COUNT(n) ((n) << 8)
#define GENERATION_SEL_MASK GENMASK(1, 0)
@ -52,6 +51,7 @@ struct j721e_pcie {
struct clk *refclk;
u32 mode;
u32 num_lanes;
u32 max_lanes;
void __iomem *user_cfg_base;
void __iomem *intd_cfg_base;
u32 linkdown_irq_regfield;
@ -205,11 +205,15 @@ static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie,
{
struct device *dev = pcie->cdns_pcie->dev;
u32 lanes = pcie->num_lanes;
u32 mask = BIT(8);
u32 val = 0;
int ret;
if (pcie->max_lanes == 4)
mask = GENMASK(9, 8);
val = LANE_COUNT(lanes - 1);
ret = regmap_update_bits(syscon, offset, LANE_COUNT_MASK, val);
ret = regmap_update_bits(syscon, offset, mask, val);
if (ret)
dev_err(dev, "failed to set link count\n");
@ -441,7 +445,9 @@ static int j721e_pcie_probe(struct platform_device *pdev)
dev_warn(dev, "num-lanes property not provided or invalid, setting num-lanes to 1\n");
num_lanes = 1;
}
pcie->num_lanes = num_lanes;
pcie->max_lanes = data->max_lanes;
if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)))
return -EINVAL;