clk: st: Support for VCC-mux and MUX clocks
The patch supports the VCC-mux and MUX clocks used by ClockGenC/F VCC-mux clock : Divider-Multiplexer-Gate inside ClockGenC/F It includes support for each channel : 4-parent Multiplexer, Post Divide by 1, 2, 4 or 8, Gate to switch OFF the output channel. The clock is implemented using generic clocks implemented in the kernel clk_divider, clk_mux, clk_gate and clk_composite (to combine all) MUX clock : 2-parent clock used inside ClockGenC/F. The clock is implemented using generic clocks implemented in the kernel clk_mux. Signed-off-by: Pankaj Dev <pankaj.dev@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
This commit is contained in:
Gabriel FERNANDEZ
Mike Turquette
parent
b9b8e614b5
commit
44993d3840
@ -18,6 +18,7 @@
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#include <linux/clk-provider.h>
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static DEFINE_SPINLOCK(clkgena_divmux_lock);
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static DEFINE_SPINLOCK(clkgenf_lock);
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static const char ** __init clkgen_mux_get_parents(struct device_node *np,
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int *num_parents)
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@ -527,3 +528,274 @@ void __init st_of_clkgena_prediv_setup(struct device_node *np)
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return;
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}
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CLK_OF_DECLARE(clkgenaprediv, "st,clkgena-prediv", st_of_clkgena_prediv_setup);
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struct clkgen_mux_data {
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u32 offset;
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u8 shift;
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u8 width;
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spinlock_t *lock;
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unsigned long clk_flags;
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u8 mux_flags;
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};
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static struct clkgen_mux_data clkgen_mux_c_vcc_hd_416 = {
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.offset = 0,
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.shift = 0,
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.width = 1,
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};
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static struct clkgen_mux_data clkgen_mux_f_vcc_fvdp_416 = {
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.offset = 0,
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.shift = 0,
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.width = 1,
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};
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static struct clkgen_mux_data clkgen_mux_f_vcc_hva_416 = {
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.offset = 0,
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.shift = 0,
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.width = 1,
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};
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static struct clkgen_mux_data clkgen_mux_f_vcc_hd_416 = {
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.offset = 0,
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.shift = 16,
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.width = 1,
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.lock = &clkgenf_lock,
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};
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static struct clkgen_mux_data clkgen_mux_c_vcc_sd_416 = {
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.offset = 0,
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.shift = 17,
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.width = 1,
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.lock = &clkgenf_lock,
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};
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static struct of_device_id mux_of_match[] = {
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{
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.compatible = "st,stih416-clkgenc-vcc-hd",
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.data = &clkgen_mux_c_vcc_hd_416,
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},
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{
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.compatible = "st,stih416-clkgenf-vcc-fvdp",
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.data = &clkgen_mux_f_vcc_fvdp_416,
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},
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{
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.compatible = "st,stih416-clkgenf-vcc-hva",
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.data = &clkgen_mux_f_vcc_hva_416,
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},
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{
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.compatible = "st,stih416-clkgenf-vcc-hd",
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.data = &clkgen_mux_f_vcc_hd_416,
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},
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{
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.compatible = "st,stih416-clkgenf-vcc-sd",
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.data = &clkgen_mux_c_vcc_sd_416,
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},
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{}
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};
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void __init st_of_clkgen_mux_setup(struct device_node *np)
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{
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const struct of_device_id *match;
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struct clk *clk;
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void __iomem *reg;
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const char **parents;
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int num_parents;
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struct clkgen_mux_data *data;
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match = of_match_node(mux_of_match, np);
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if (!match) {
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pr_err("%s: No matching data\n", __func__);
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return;
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}
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data = (struct clkgen_mux_data *)match->data;
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reg = of_iomap(np, 0);
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if (!reg) {
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pr_err("%s: Failed to get base address\n", __func__);
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return;
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}
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parents = clkgen_mux_get_parents(np, &num_parents);
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if (IS_ERR(parents)) {
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pr_err("%s: Failed to get parents (%ld)\n",
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__func__, PTR_ERR(parents));
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return;
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}
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clk = clk_register_mux(NULL, np->name, parents, num_parents,
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data->clk_flags | CLK_SET_RATE_PARENT,
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reg + data->offset,
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data->shift, data->width, data->mux_flags,
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data->lock);
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if (IS_ERR(clk))
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goto err;
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pr_debug("%s: parent %s rate %u\n",
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__clk_get_name(clk),
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__clk_get_name(clk_get_parent(clk)),
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(unsigned int)clk_get_rate(clk));
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of_clk_add_provider(np, of_clk_src_simple_get, clk);
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err:
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kfree(parents);
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return;
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}
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CLK_OF_DECLARE(clkgen_mux, "st,clkgen-mux", st_of_clkgen_mux_setup);
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#define VCC_MAX_CHANNELS 16
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#define VCC_GATE_OFFSET 0x0
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#define VCC_MUX_OFFSET 0x4
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#define VCC_DIV_OFFSET 0x8
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struct clkgen_vcc_data {
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spinlock_t *lock;
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unsigned long clk_flags;
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};
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static struct clkgen_vcc_data st_clkgenc_vcc_416 = {
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.clk_flags = CLK_SET_RATE_PARENT,
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};
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static struct clkgen_vcc_data st_clkgenf_vcc_416 = {
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.lock = &clkgenf_lock,
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};
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static struct of_device_id vcc_of_match[] = {
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{ .compatible = "st,stih416-clkgenc", .data = &st_clkgenc_vcc_416 },
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{ .compatible = "st,stih416-clkgenf", .data = &st_clkgenf_vcc_416 },
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{}
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};
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void __init st_of_clkgen_vcc_setup(struct device_node *np)
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{
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const struct of_device_id *match;
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void __iomem *reg;
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const char **parents;
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int num_parents, i;
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struct clk_onecell_data *clk_data;
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struct clkgen_vcc_data *data;
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match = of_match_node(vcc_of_match, np);
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if (WARN_ON(!match))
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return;
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data = (struct clkgen_vcc_data *)match->data;
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reg = of_iomap(np, 0);
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if (!reg)
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return;
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parents = clkgen_mux_get_parents(np, &num_parents);
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if (IS_ERR(parents))
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return;
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clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
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if (!clk_data)
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goto err;
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clk_data->clk_num = VCC_MAX_CHANNELS;
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clk_data->clks = kzalloc(clk_data->clk_num * sizeof(struct clk *),
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GFP_KERNEL);
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if (!clk_data->clks)
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goto err;
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for (i = 0; i < clk_data->clk_num; i++) {
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struct clk *clk;
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const char *clk_name;
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struct clk_gate *gate;
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struct clk_divider *div;
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struct clk_mux *mux;
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if (of_property_read_string_index(np, "clock-output-names",
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i, &clk_name))
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break;
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/*
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* If we read an empty clock name then the output is unused
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*/
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if (*clk_name == '\0')
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continue;
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gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
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if (!gate)
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break;
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div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL);
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if (!div) {
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kfree(gate);
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break;
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}
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mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
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if (!mux) {
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kfree(gate);
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kfree(div);
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break;
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}
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gate->reg = reg + VCC_GATE_OFFSET;
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gate->bit_idx = i;
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gate->flags = CLK_GATE_SET_TO_DISABLE;
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gate->lock = data->lock;
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div->reg = reg + VCC_DIV_OFFSET;
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div->shift = 2 * i;
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div->width = 2;
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div->flags = CLK_DIVIDER_POWER_OF_TWO;
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mux->reg = reg + VCC_MUX_OFFSET;
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mux->shift = 2 * i;
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mux->mask = 0x3;
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clk = clk_register_composite(NULL, clk_name, parents,
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num_parents,
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&mux->hw, &clk_mux_ops,
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&div->hw, &clk_divider_ops,
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&gate->hw, &clk_gate_ops,
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data->clk_flags);
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if (IS_ERR(clk)) {
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kfree(gate);
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kfree(div);
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kfree(mux);
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goto err;
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}
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pr_debug("%s: parent %s rate %u\n",
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__clk_get_name(clk),
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__clk_get_name(clk_get_parent(clk)),
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(unsigned int)clk_get_rate(clk));
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clk_data->clks[i] = clk;
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}
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kfree(parents);
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of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
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return;
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err:
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for (i = 0; i < clk_data->clk_num; i++) {
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struct clk_composite *composite;
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if (!clk_data->clks[i])
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continue;
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composite = container_of(__clk_get_hw(clk_data->clks[i]),
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struct clk_composite, hw);
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kfree(container_of(composite->gate_hw, struct clk_gate, hw));
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kfree(container_of(composite->rate_hw, struct clk_divider, hw));
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kfree(container_of(composite->mux_hw, struct clk_mux, hw));
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}
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if (clk_data)
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kfree(clk_data->clks);
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kfree(clk_data);
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kfree(parents);
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}
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CLK_OF_DECLARE(clkgen_vcc, "st,clkgen-vcc", st_of_clkgen_vcc_setup);
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