iv/linux
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

cxl: Convert find_cxl_root() to return a 'struct cxl_root *'

Browse Source 
Commit 790815902ec6 ("cxl: Add support for _DSM Function for retrieving QTG ID")
introduced 'struct cxl_root', however all usages have been worked
indirectly through cxl_port. Refactor code such as find_cxl_root()
function to use 'struct cxl_root' directly.

Suggested-by: Dan Williams <dan.j.williams@intel.com>
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/170449246044.3779673.13035770941393418591.stgit@djiang5-mobl3
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
This commit is contained in:
Dave Jiang 2024-01-05 15:07:40 -07:00 committed by Dan Williams
parent 98856b2ea3
commit 44cd71ef7b
6 changed files with 28 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/cxl/acpi.c
View File

@ -295,14 +295,12 @@ out:
return rc;
}
static int cxl_acpi_qos_class(struct cxl_port *root_port,
static int cxl_acpi_qos_class(struct cxl_root *cxl_root,
struct access_coordinate *coord, int entries,
int *qos_class)
{
struct device *dev = cxl_root->port.uport_dev;
acpi_handle handle;
struct device *dev;
dev = root_port->uport_dev;
if (!dev_is_platform(dev))
return -ENODEV;

17
drivers/cxl/core/cdat.c
View File

@ -162,7 +162,6 @@ static int cxl_port_perf_data_calculate(struct cxl_port *port,
struct xarray *dsmas_xa)
{
struct access_coordinate c;
struct cxl_port *root_port;
struct cxl_root *cxl_root;
struct dsmas_entry *dent;
int valid_entries = 0;
@ -175,8 +174,7 @@ static int cxl_port_perf_data_calculate(struct cxl_port *port,
return rc;
}
root_port = find_cxl_root(port);
cxl_root = to_cxl_root(root_port);
cxl_root = find_cxl_root(port);
if (!cxl_root->ops || !cxl_root->ops->qos_class)
return -EOPNOTSUPP;
@ -193,7 +191,8 @@ static int cxl_port_perf_data_calculate(struct cxl_port *port,
dent->coord.write_bandwidth);
dent->entries = 1;
rc = cxl_root->ops->qos_class(root_port, &dent->coord, 1, &qos_class);
rc = cxl_root->ops->qos_class(cxl_root, &dent->coord, 1,
&qos_class);
if (rc != 1)
continue;
@ -349,15 +348,19 @@ static int cxl_qos_class_verify(struct cxl_memdev *cxlmd)
{
struct cxl_dev_state *cxlds = cxlmd->cxlds;
struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds);
struct cxl_port *root_port __free(put_device) = NULL;
LIST_HEAD(__discard);
struct list_head *discard __free(dpa_perf) = &__discard;
struct cxl_port *root_port;
int rc;
root_port = find_cxl_root(cxlmd->endpoint);
if (!root_port)
struct cxl_root *cxl_root __free(put_cxl_root) =
find_cxl_root(cxlmd->endpoint);
if (!cxl_root)
return -ENODEV;
root_port = &cxl_root->port;
/* Check that the QTG IDs are all sane between end device and root decoders */
cxl_qos_match(root_port, &mds->ram_perf_list, discard);
cxl_qos_match(root_port, &mds->pmem_perf_list, discard);

6
drivers/cxl/core/pmem.c
View File

@ -64,12 +64,14 @@ static int match_nvdimm_bridge(struct device *dev, void *data)
struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_memdev *cxlmd)
{
struct cxl_port *port = find_cxl_root(cxlmd->endpoint);
struct cxl_root *cxl_root = find_cxl_root(cxlmd->endpoint);
struct cxl_port *port;
struct device *dev;
if (!port)
if (!cxl_root)
return NULL;
port = &cxl_root->port;
dev = device_find_child(&port->dev, NULL, match_nvdimm_bridge);
put_device(&port->dev);

4
drivers/cxl/core/port.c
View File

@ -972,7 +972,7 @@ static bool dev_is_cxl_root_child(struct device *dev)
return false;
}
struct cxl_port *find_cxl_root(struct cxl_port *port)
struct cxl_root *find_cxl_root(struct cxl_port *port)
{
struct cxl_port *iter = port;
@ -982,7 +982,7 @@ struct cxl_port *find_cxl_root(struct cxl_port *port)
if (!iter)
return NULL;
get_device(&iter->dev);
return iter;
return to_cxl_root(iter);
}
EXPORT_SYMBOL_NS_GPL(find_cxl_root, CXL);

14
drivers/cxl/cxl.h
View File

@ -617,12 +617,6 @@ struct cxl_port {
long pci_latency;
};
struct cxl_root_ops {
int (*qos_class)(struct cxl_port *root_port,
struct access_coordinate *coord, int entries,
int *qos_class);
};
/**
* struct cxl_root - logical collection of root cxl_port items
*
@ -640,6 +634,12 @@ to_cxl_root(const struct cxl_port *port)
return container_of(port, struct cxl_root, port);
}
struct cxl_root_ops {
int (*qos_class)(struct cxl_root *cxl_root,
struct access_coordinate *coord, int entries,
int *qos_class);
};
static inline struct cxl_dport *
cxl_find_dport_by_dev(struct cxl_port *port, const struct device *dport_dev)
{
@ -734,7 +734,7 @@ struct cxl_port *devm_cxl_add_port(struct device *host,
struct cxl_dport *parent_dport);
struct cxl_root *devm_cxl_add_root(struct device *host,
const struct cxl_root_ops *ops);
struct cxl_port *find_cxl_root(struct cxl_port *port);
struct cxl_root *find_cxl_root(struct cxl_port *port);
void put_cxl_root(struct cxl_root *cxl_root);
DEFINE_FREE(put_cxl_root, struct cxl_root *, if (_T) put_cxl_root(_T))

4
drivers/cxl/port.c
View File

@ -94,6 +94,7 @@ static int cxl_endpoint_port_probe(struct cxl_port *port)
struct cxl_endpoint_dvsec_info info = { .port = port };
struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport_dev);
struct cxl_dev_state *cxlds = cxlmd->cxlds;
struct cxl_root *cxl_root;
struct cxl_hdm *cxlhdm;
struct cxl_port *root;
int rc;
@ -130,7 +131,8 @@ static int cxl_endpoint_port_probe(struct cxl_port *port)
* This can't fail in practice as CXL root exit unregisters all
* descendant ports and that in turn synchronizes with cxl_port_probe()
*/
root = find_cxl_root(port);
cxl_root = find_cxl_root(port);
root = &cxl_root->port;
/*
* Now that all endpoint decoders are successfully enumerated, try to