iio: adc: add driver for Rockchip saradc
The ADC is a 3-channel signal-ended 10-bit Successive Approximation Register (SAR) A/D Converter. It uses the supply and ground as its reference and converts the analog input signal into 10-bit binary digital codes. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Hartmut Knaack <knaack.h@gmx.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
This commit is contained in:
Heiko Stübner
Jonathan Cameron
parent
af097e8631
commit
44d6f2ef94
@ -206,6 +206,16 @@ config NAU7802
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To compile this driver as a module, choose M here: the
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module will be called nau7802.
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config ROCKCHIP_SARADC
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tristate "Rockchip SARADC driver"
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depends on ARCH_ROCKCHIP || (ARM && COMPILE_TEST)
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help
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Say yes here to build support for the SARADC found in SoCs from
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Rockchip.
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To compile this driver as a module, choose M here: the
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module will be called rockchip_saradc.
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config TI_ADC081C
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tristate "Texas Instruments ADC081C021/027"
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depends on I2C
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@ -22,6 +22,7 @@ obj-$(CONFIG_MCP320X) += mcp320x.o
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obj-$(CONFIG_MCP3422) += mcp3422.o
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obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o
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obj-$(CONFIG_NAU7802) += nau7802.o
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obj-$(CONFIG_ROCKCHIP_SARADC) += rockchip_saradc.o
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obj-$(CONFIG_TI_ADC081C) += ti-adc081c.o
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obj-$(CONFIG_TI_ADC128S052) += ti-adc128s052.o
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obj-$(CONFIG_TI_AM335X_ADC) += ti_am335x_adc.o
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317
drivers/iio/adc/rockchip_saradc.c
Normal file
317
drivers/iio/adc/rockchip_saradc.c
Normal file
@ -0,0 +1,317 @@
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/*
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* Rockchip Successive Approximation Register (SAR) A/D Converter
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* Copyright (C) 2014 ROCKCHIP, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/clk.h>
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#include <linux/completion.h>
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#include <linux/regulator/consumer.h>
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#include <linux/iio/iio.h>
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#define SARADC_DATA 0x00
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#define SARADC_DATA_MASK 0x3ff
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#define SARADC_STAS 0x04
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#define SARADC_STAS_BUSY BIT(0)
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#define SARADC_CTRL 0x08
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#define SARADC_CTRL_IRQ_STATUS BIT(6)
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#define SARADC_CTRL_IRQ_ENABLE BIT(5)
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#define SARADC_CTRL_POWER_CTRL BIT(3)
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#define SARADC_CTRL_CHN_MASK 0x7
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#define SARADC_DLY_PU_SOC 0x0c
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#define SARADC_DLY_PU_SOC_MASK 0x3f
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#define SARADC_BITS 10
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#define SARADC_TIMEOUT msecs_to_jiffies(100)
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struct rockchip_saradc {
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void __iomem *regs;
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struct clk *pclk;
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struct clk *clk;
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struct completion completion;
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struct regulator *vref;
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u16 last_val;
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};
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static int rockchip_saradc_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int *val, int *val2, long mask)
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{
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struct rockchip_saradc *info = iio_priv(indio_dev);
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int ret;
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switch (mask) {
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case IIO_CHAN_INFO_RAW:
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mutex_lock(&indio_dev->mlock);
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reinit_completion(&info->completion);
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/* 8 clock periods as delay between power up and start cmd */
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writel_relaxed(8, info->regs + SARADC_DLY_PU_SOC);
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/* Select the channel to be used and trigger conversion */
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writel(SARADC_CTRL_POWER_CTRL
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| (chan->channel & SARADC_CTRL_CHN_MASK)
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| SARADC_CTRL_IRQ_ENABLE,
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info->regs + SARADC_CTRL);
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if (!wait_for_completion_timeout(&info->completion,
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SARADC_TIMEOUT)) {
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writel_relaxed(0, info->regs + SARADC_CTRL);
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mutex_unlock(&indio_dev->mlock);
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return -ETIMEDOUT;
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}
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*val = info->last_val;
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mutex_unlock(&indio_dev->mlock);
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return IIO_VAL_INT;
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case IIO_CHAN_INFO_SCALE:
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ret = regulator_get_voltage(info->vref);
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if (ret < 0) {
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dev_err(&indio_dev->dev, "failed to get voltage\n");
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return ret;
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}
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*val = ret / 1000;
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*val2 = SARADC_BITS;
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return IIO_VAL_FRACTIONAL_LOG2;
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default:
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return -EINVAL;
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}
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}
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static irqreturn_t rockchip_saradc_isr(int irq, void *dev_id)
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{
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struct rockchip_saradc *info = (struct rockchip_saradc *)dev_id;
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/* Read value */
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info->last_val = readl_relaxed(info->regs + SARADC_DATA);
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info->last_val &= SARADC_DATA_MASK;
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/* Clear irq & power down adc */
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writel_relaxed(0, info->regs + SARADC_CTRL);
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complete(&info->completion);
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return IRQ_HANDLED;
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}
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static const struct iio_info rockchip_saradc_iio_info = {
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.read_raw = rockchip_saradc_read_raw,
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.driver_module = THIS_MODULE,
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};
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#define ADC_CHANNEL(_index, _id) { \
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.type = IIO_VOLTAGE, \
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.indexed = 1, \
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.channel = _index, \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
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.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
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.datasheet_name = _id, \
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}
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static const struct iio_chan_spec rockchip_saradc_iio_channels[] = {
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ADC_CHANNEL(0, "adc0"),
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ADC_CHANNEL(1, "adc1"),
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ADC_CHANNEL(2, "adc2"),
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};
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static int rockchip_saradc_probe(struct platform_device *pdev)
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{
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struct rockchip_saradc *info = NULL;
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struct device_node *np = pdev->dev.of_node;
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struct iio_dev *indio_dev = NULL;
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struct resource *mem;
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int ret;
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int irq;
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u32 rate;
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if (!np)
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return -ENODEV;
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indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*info));
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if (!indio_dev) {
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dev_err(&pdev->dev, "failed allocating iio device\n");
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return -ENOMEM;
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}
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info = iio_priv(indio_dev);
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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info->regs = devm_ioremap_resource(&pdev->dev, mem);
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if (IS_ERR(info->regs))
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return PTR_ERR(info->regs);
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init_completion(&info->completion);
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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dev_err(&pdev->dev, "no irq resource?\n");
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return irq;
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}
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ret = devm_request_irq(&pdev->dev, irq, rockchip_saradc_isr,
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0, dev_name(&pdev->dev), info);
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if (ret < 0) {
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dev_err(&pdev->dev, "failed requesting irq %d\n", irq);
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return ret;
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}
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info->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
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if (IS_ERR(info->pclk)) {
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dev_err(&pdev->dev, "failed to get pclk\n");
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return PTR_ERR(info->pclk);
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}
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info->clk = devm_clk_get(&pdev->dev, "saradc");
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if (IS_ERR(info->clk)) {
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dev_err(&pdev->dev, "failed to get adc clock\n");
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return PTR_ERR(info->clk);
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}
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info->vref = devm_regulator_get(&pdev->dev, "vref");
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if (IS_ERR(info->vref)) {
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dev_err(&pdev->dev, "failed to get regulator, %ld\n",
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PTR_ERR(info->vref));
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return PTR_ERR(info->vref);
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}
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/*
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* Use a default of 1MHz for the converter clock.
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* This may become user-configurable in the future.
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*/
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ret = clk_set_rate(info->clk, 1000000);
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if (ret < 0) {
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dev_err(&pdev->dev, "failed to set adc clk rate, %d\n", ret);
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return ret;
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}
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ret = regulator_enable(info->vref);
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if (ret < 0) {
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dev_err(&pdev->dev, "failed to enable vref regulator\n");
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return ret;
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}
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ret = clk_prepare_enable(info->pclk);
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if (ret < 0) {
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dev_err(&pdev->dev, "failed to enable pclk\n");
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goto err_reg_voltage;
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}
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ret = clk_prepare_enable(info->clk);
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if (ret < 0) {
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dev_err(&pdev->dev, "failed to enable converter clock\n");
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goto err_pclk;
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}
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platform_set_drvdata(pdev, indio_dev);
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indio_dev->name = dev_name(&pdev->dev);
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indio_dev->dev.parent = &pdev->dev;
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indio_dev->dev.of_node = pdev->dev.of_node;
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indio_dev->info = &rockchip_saradc_iio_info;
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indio_dev->modes = INDIO_DIRECT_MODE;
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indio_dev->channels = rockchip_saradc_iio_channels;
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indio_dev->num_channels = ARRAY_SIZE(rockchip_saradc_iio_channels);
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ret = iio_device_register(indio_dev);
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if (ret)
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goto err_clk;
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return 0;
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err_clk:
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clk_disable_unprepare(info->clk);
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err_pclk:
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clk_disable_unprepare(info->pclk);
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err_reg_voltage:
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regulator_disable(info->vref);
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return ret;
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}
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static int rockchip_saradc_remove(struct platform_device *pdev)
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{
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struct iio_dev *indio_dev = platform_get_drvdata(pdev);
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struct rockchip_saradc *info = iio_priv(indio_dev);
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iio_device_unregister(indio_dev);
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clk_disable_unprepare(info->clk);
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clk_disable_unprepare(info->pclk);
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regulator_disable(info->vref);
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return 0;
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}
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#ifdef CONFIG_PM_SLEEP
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static int rockchip_saradc_suspend(struct device *dev)
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{
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struct iio_dev *indio_dev = dev_get_drvdata(dev);
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struct rockchip_saradc *info = iio_priv(indio_dev);
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clk_disable_unprepare(info->clk);
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clk_disable_unprepare(info->pclk);
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regulator_disable(info->vref);
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return 0;
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}
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static int rockchip_saradc_resume(struct device *dev)
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{
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struct iio_dev *indio_dev = dev_get_drvdata(dev);
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struct rockchip_saradc *info = iio_priv(indio_dev);
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int ret;
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ret = regulator_enable(info->vref);
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if (ret)
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return ret;
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ret = clk_prepare_enable(info->pclk);
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if (ret)
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return ret;
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ret = clk_prepare_enable(info->clk);
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if (ret)
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return ret;
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return ret;
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}
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#endif
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static SIMPLE_DEV_PM_OPS(rockchip_saradc_pm_ops,
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rockchip_saradc_suspend, rockchip_saradc_resume);
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static const struct of_device_id rockchip_saradc_match[] = {
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{ .compatible = "rockchip,saradc" },
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{},
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};
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MODULE_DEVICE_TABLE(of, rockchip_saradc_match);
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static struct platform_driver rockchip_saradc_driver = {
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.probe = rockchip_saradc_probe,
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.remove = rockchip_saradc_remove,
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.driver = {
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.name = "rockchip-saradc",
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.owner = THIS_MODULE,
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.of_match_table = rockchip_saradc_match,
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.pm = &rockchip_saradc_pm_ops,
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},
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};
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module_platform_driver(rockchip_saradc_driver);
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