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Samsung DTS ARM64 changes for v6.8, part two

Browse Source 
1. Tesla FSD: Add Multi Format Codec (MFC) device nodes, for accelerated
    video de/encoding.
 
 2. Add initial Google Tensor GS101 SoC support. The GS101 SoC can be
    found on Google Pixel 6 phones.  Currently the DTS brings only basic
    support: core clock controllers, pin controllers, serial, watchdog
    and ARM core blocks.
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Merge tag 'samsung-dt64-6.8-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt

Samsung DTS ARM64 changes for v6.8, part two

1. Tesla FSD: Add Multi Format Codec (MFC) device nodes, for accelerated
   video de/encoding.

2. Add initial Google Tensor GS101 SoC support. The GS101 SoC can be
   found on Google Pixel 6 phones.  Currently the DTS brings only basic
   support: core clock controllers, pin controllers, serial, watchdog
   and ARM core blocks.

* tag 'samsung-dt64-6.8-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  MAINTAINERS: adjust file entry in GOOGLE TENSOR SoC SUPPORT
  MAINTAINERS: add entry for Google Tensor SoC
  arm64: dts: exynos: google: Add initial Oriole/pixel 6 board support
  arm64: dts: exynos: google: Add initial Google gs101 SoC support
  dt-bindings: arm: google: Add bindings for Google ARM platforms
  arm64: dts: fsd: Add MFC related DT enteries

Link: https://lore.kernel.org/r/20231220084722.22149-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2023-12-21 17:04:33 +00:00
commit 450388847b
9 changed files with 1950 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

53
Documentation/devicetree/bindings/arm/google.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/google.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Google Tensor platforms
maintainers:
- Peter Griffin <peter.griffin@linaro.org>
description: |
ARM platforms using SoCs designed by Google branded "Tensor" used in Pixel
devices.
Currently upstream this is devices using "gs101" SoC which is found in Pixel
6, Pixel 6 Pro and Pixel 6a.
Google have a few different names for the SoC:
- Marketing name ("Tensor")
- Codename ("Whitechapel")
- SoC ID ("gs101")
- Die ID ("S5P9845")
Likewise there are a couple of names for the actual device
- Marketing name ("Pixel 6")
- Codename ("Oriole")
Devicetrees should use the lowercased SoC ID and lowercased board codename,
e.g. gs101 and gs101-oriole.
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: Google Pixel 6 / Oriole
items:
- enum:
- google,gs101-oriole
- const: google,gs101
# Bootloader requires empty ect node to be present
ect:
type: object
additionalProperties: false
required:
- ect
additionalProperties: true
...

10
MAINTAINERS
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@ -9007,6 +9007,16 @@ S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/chrome-platform/linux.git
F: drivers/firmware/google/
GOOGLE TENSOR SoC SUPPORT
M: Peter Griffin <peter.griffin@linaro.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
L: linux-samsung-soc@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
F: arch/arm64/boot/dts/exynos/google/
F: drivers/clk/samsung/clk-gs101.c
F: include/dt-bindings/clock/google,gs101.h
GPD POCKET FAN DRIVER
M: Hans de Goede <hdegoede@redhat.com>
L: platform-driver-x86@vger.kernel.org

2
arch/arm64/boot/dts/exynos/Makefile
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@ -1,4 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
subdir-y += google
dtb-$(CONFIG_ARCH_EXYNOS) += \
exynos5433-tm2.dtb \
exynos5433-tm2e.dtb \

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arch/arm64/boot/dts/exynos/google/Makefile Normal file
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# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_EXYNOS) += \
gs101-oriole.dtb \

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arch/arm64/boot/dts/exynos/google/gs101-oriole.dts Normal file
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Oriole Device Tree
*
* Copyright 2021-2023 Google LLC
* Copyright 2023 Linaro Ltd - <peter.griffin@linaro.org>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "gs101-pinctrl.h"
#include "gs101.dtsi"
/ {
model = "Oriole";
compatible = "google,gs101-oriole", "google,gs101";
aliases {
serial0 = &serial_0;
};
chosen {
/* Bootloader expects bootargs specified otherwise it crashes */
bootargs = "";
stdout-path = &serial_0;
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&key_voldown>, <&key_volup>, <&key_power>;
button-vol-down {
label = "KEY_VOLUMEDOWN";
linux,code = <KEY_VOLUMEDOWN>;
gpios = <&gpa7 3 GPIO_ACTIVE_LOW>;
wakeup-source;
};
button-vol-up {
label = "KEY_VOLUMEUP";
linux,code = <KEY_VOLUMEUP>;
gpios = <&gpa8 1 GPIO_ACTIVE_LOW>;
wakeup-source;
};
button-power {
label = "KEY_POWER";
linux,code = <KEY_POWER>;
gpios = <&gpa10 1 GPIO_ACTIVE_LOW>;
wakeup-source;
};
};
};
&ext_24_5m {
clock-frequency = <24576000>;
};
&ext_200m {
clock-frequency = <200000000>;
};
&pinctrl_far_alive {
key_voldown: key-voldown-pins {
samsung,pins = "gpa7-3";
samsung,pin-function = <GS101_PIN_FUNC_EINT>;
samsung,pin-pud = <GS101_PIN_PULL_NONE>;
samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
};
key_volup: key-volup-pins {
samsung,pins = "gpa8-1";
samsung,pin-function = <GS101_PIN_FUNC_EINT>;
samsung,pin-pud = <GS101_PIN_PULL_NONE>;
samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
};
};
&pinctrl_gpio_alive {
key_power: key-power-pins {
samsung,pins = "gpa10-1";
samsung,pin-function = <GS101_PIN_FUNC_EINT>;
samsung,pin-pud = <GS101_PIN_PULL_NONE>;
samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
};
};
&serial_0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_bus>;
status = "okay";
};
&usi_uart {
samsung,clkreq-on; /* needed for UART mode */
status = "okay";
};
&watchdog_cl0 {
timeout-sec = <30>;
status = "okay";
};

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arch/arm64/boot/dts/exynos/google/gs101-pinctrl.dtsi Normal file
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arch/arm64/boot/dts/exynos/google/gs101-pinctrl.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Pinctrl binding constants for GS101
*
* Copyright 2020-2023 Google LLC
*/
#ifndef __DTS_ARM64_SAMSUNG_EXYNOS_GOOGLE_PINCTRL_GS101_H__
#define __DTS_ARM64_SAMSUNG_EXYNOS_GOOGLE_PINCTRL_GS101_H__
#define GS101_PIN_PULL_NONE 0
#define GS101_PIN_PULL_DOWN 1
#define GS101_PIN_PULL_UP 3
/* Pin function in power down mode */
#define GS101_PIN_PDN_OUT0 0
#define GS101_PIN_PDN_OUT1 1
#define GS101_PIN_PDN_INPUT 2
#define GS101_PIN_PDN_PREV 3
/* GS101 drive strengths */
#define GS101_PIN_DRV_2_5_MA 0
#define GS101_PIN_DRV_5_MA 1
#define GS101_PIN_DRV_7_5_MA 2
#define GS101_PIN_DRV_10_MA 3
#define GS101_PIN_FUNC_INPUT 0
#define GS101_PIN_FUNC_OUTPUT 1
#define GS101_PIN_FUNC_2 2
#define GS101_PIN_FUNC_3 3
#define GS101_PIN_FUNC_EINT 0xf
#endif /* __DTS_ARM64_SAMSUNG_EXYNOS_GOOGLE_PINCTRL_GS101_H__ */

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arch/arm64/boot/dts/exynos/google/gs101.dtsi Normal file
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// SPDX-License-Identifier: GPL-2.0-only
/*
* GS101 SoC
*
* Copyright 2019-2023 Google LLC
* Copyright 2023 Linaro Ltd - <peter.griffin@linaro.org>
*/
#include <dt-bindings/clock/google,gs101.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/samsung,exynos-usi.h>
/ {
compatible = "google,gs101";
#address-cells = <2>;
#size-cells = <1>;
interrupt-parent = <&gic>;
aliases {
pinctrl0 = &pinctrl_gpio_alive;
pinctrl1 = &pinctrl_far_alive;
pinctrl2 = &pinctrl_gsacore;
pinctrl3 = &pinctrl_gsactrl;
pinctrl4 = &pinctrl_peric0;
pinctrl5 = &pinctrl_peric1;
pinctrl6 = &pinctrl_hsi1;
pinctrl7 = &pinctrl_hsi2;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
};
cluster1 {
core0 {
cpu = <&cpu4>;
};
core1 {
cpu = <&cpu5>;
};
};
cluster2 {
core0 {
cpu = <&cpu6>;
};
core1 {
cpu = <&cpu7>;
};
};
};
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0000>;
enable-method = "psci";
cpu-idle-states = <&ANANKE_CPU_SLEEP>;
capacity-dmips-mhz = <250>;
dynamic-power-coefficient = <70>;
};
cpu1: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0100>;
enable-method = "psci";
cpu-idle-states = <&ANANKE_CPU_SLEEP>;
capacity-dmips-mhz = <250>;
dynamic-power-coefficient = <70>;
};
cpu2: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0200>;
enable-method = "psci";
cpu-idle-states = <&ANANKE_CPU_SLEEP>;
capacity-dmips-mhz = <250>;
dynamic-power-coefficient = <70>;
};
cpu3: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0300>;
enable-method = "psci";
cpu-idle-states = <&ANANKE_CPU_SLEEP>;
capacity-dmips-mhz = <250>;
dynamic-power-coefficient = <70>;
};
cpu4: cpu@400 {
device_type = "cpu";
compatible = "arm,cortex-a76";
reg = <0x0400>;
enable-method = "psci";
cpu-idle-states = <&ENYO_CPU_SLEEP>;
capacity-dmips-mhz = <620>;
dynamic-power-coefficient = <284>;
};
cpu5: cpu@500 {
device_type = "cpu";
compatible = "arm,cortex-a76";
reg = <0x0500>;
enable-method = "psci";
cpu-idle-states = <&ENYO_CPU_SLEEP>;
capacity-dmips-mhz = <620>;
dynamic-power-coefficient = <284>;
};
cpu6: cpu@600 {
device_type = "cpu";
compatible = "arm,cortex-x1";
reg = <0x0600>;
enable-method = "psci";
cpu-idle-states = <&HERA_CPU_SLEEP>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <650>;
};
cpu7: cpu@700 {
device_type = "cpu";
compatible = "arm,cortex-x1";
reg = <0x0700>;
enable-method = "psci";
cpu-idle-states = <&HERA_CPU_SLEEP>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <650>;
};
idle-states {
entry-method = "psci";
ANANKE_CPU_SLEEP: cpu-ananke-sleep {
idle-state-name = "c2";
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010000>;
entry-latency-us = <70>;
exit-latency-us = <160>;
min-residency-us = <2000>;
};
ENYO_CPU_SLEEP: cpu-enyo-sleep {
idle-state-name = "c2";
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010000>;
entry-latency-us = <150>;
exit-latency-us = <190>;
min-residency-us = <2500>;
};
HERA_CPU_SLEEP: cpu-hera-sleep {
idle-state-name = "c2";
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010000>;
entry-latency-us = <235>;
exit-latency-us = <220>;
min-residency-us = <3500>;
};
};
};
/* TODO replace with CCF clock */
dummy_clk: clock-3 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <12345>;
clock-output-names = "pclk";
};
/* ect node is required to be present by bootloader */
ect {
};
ext_24_5m: clock-1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-output-names = "oscclk";
};
ext_200m: clock-2 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-output-names = "ext-200m";
};
pmu-0 {
compatible = "arm,cortex-a55-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
};
pmu-1 {
compatible = "arm,cortex-a76-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
};
pmu-2 {
compatible = "arm,cortex-x1-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster2>;
};
pmu-3 {
compatible = "arm,dsu-pmu";
interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>;
cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
<&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <1>;
ranges;
gsa_reserved_protected: gsa@90200000 {
reg = <0x0 0x90200000 0x400000>;
no-map;
};
tpu_fw_reserved: tpu-fw@93000000 {
reg = <0x0 0x93000000 0x1000000>;
no-map;
};
aoc_reserve: aoc@94000000 {
reg = <0x0 0x94000000 0x03000000>;
no-map;
};
abl_reserved: abl@f8800000 {
reg = <0x0 0xf8800000 0x02000000>;
no-map;
};
dss_log_reserved: dss-log-reserved@fd3f0000 {
reg = <0x0 0xfd3f0000 0x0000e000>;
no-map;
};
debug_kinfo_reserved: debug-kinfo-reserved@fd3fe000 {
reg = <0x0 0xfd3fe000 0x00001000>;
no-map;
};
bldr_log_reserved: bldr-log-reserved@fd800000 {
reg = <0x0 0xfd800000 0x00100000>;
no-map;
};
bldr_log_hist_reserved: bldr-log-hist-reserved@fd900000 {
reg = <0x0 0xfd900000 0x00002000>;
no-map;
};
};
soc: soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x0 0x40000000>;
cmu_misc: clock-controller@10010000 {
compatible = "google,gs101-cmu-misc";
reg = <0x10010000 0x8000>;
#clock-cells = <1>;
clocks = <&cmu_top CLK_DOUT_CMU_MISC_BUS>,
<&cmu_top CLK_DOUT_CMU_MISC_SSS>;
clock-names = "dout_cmu_misc_bus", "dout_cmu_misc_sss";
};
watchdog_cl0: watchdog@10060000 {
compatible = "google,gs101-wdt";
reg = <0x10060000 0x100>;
interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER0_PCLK>,
<&ext_24_5m>;
clock-names = "watchdog", "watchdog_src";
samsung,syscon-phandle = <&pmu_system_controller>;
samsung,cluster-index = <0>;
status = "disabled";
};
watchdog_cl1: watchdog@10070000 {
compatible = "google,gs101-wdt";
reg = <0x10070000 0x100>;
interrupts = <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER1_PCLK>,
<&ext_24_5m>;
clock-names = "watchdog", "watchdog_src";
samsung,syscon-phandle = <&pmu_system_controller>;
samsung,cluster-index = <1>;
status = "disabled";
};
gic: interrupt-controller@10400000 {
compatible = "arm,gic-v3";
#interrupt-cells = <4>;
interrupt-controller;
reg = <0x10400000 0x10000>, /* GICD */
<0x10440000 0x100000>;/* GICR * 8 */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
ppi-partitions {
ppi_cluster0: interrupt-partition-0 {
affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
};
ppi_cluster1: interrupt-partition-1 {
affinity = <&cpu4 &cpu5>;
};
ppi_cluster2: interrupt-partition-2 {
affinity = <&cpu6 &cpu7>;
};
};
};
sysreg_peric0: syscon@10820000 {
compatible = "google,gs101-peric0-sysreg", "syscon";
reg = <0x10820000 0x10000>;
};
pinctrl_peric0: pinctrl@10840000 {
compatible = "google,gs101-pinctrl";
reg = <0x10840000 0x00001000>;
interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH 0>;
};
usi_uart: usi@10a000c0 {
compatible = "google,gs101-usi",
"samsung,exynos850-usi";
reg = <0x10a000c0 0x20>;
ranges;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&dummy_clk>, <&dummy_clk>;
clock-names = "pclk", "ipclk";
samsung,sysreg = <&sysreg_peric0 0x1020>;
samsung,mode = <USI_V2_UART>;
status = "disabled";
serial_0: serial@10a00000 {
compatible = "google,gs101-uart";
reg = <0x10a00000 0xc0>;
reg-io-width = <4>;
interrupts = <GIC_SPI 634
IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&dummy_clk 0>, <&dummy_clk 0>;
clock-names = "uart", "clk_uart_baud0";
samsung,uart-fifosize = <256>;
status = "disabled";
};
};
sysreg_peric1: syscon@10c20000 {
compatible = "google,gs101-peric1-sysreg", "syscon";
reg = <0x10c20000 0x10000>;
};
pinctrl_peric1: pinctrl@10c40000 {
compatible = "google,gs101-pinctrl";
reg = <0x10c40000 0x00001000>;
interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>;
};
pinctrl_hsi1: pinctrl@11840000 {
compatible = "google,gs101-pinctrl";
reg = <0x11840000 0x00001000>;
interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH 0>;
};
pinctrl_hsi2: pinctrl@14440000 {
compatible = "google,gs101-pinctrl";
reg = <0x14440000 0x00001000>;
interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
};
cmu_apm: clock-controller@17400000 {
compatible = "google,gs101-cmu-apm";
reg = <0x17400000 0x8000>;
#clock-cells = <1>;
clocks = <&ext_24_5m>;
clock-names = "oscclk";
};
sysreg_apm: syscon@174204e0 {
compatible = "google,gs101-apm-sysreg", "syscon";
reg = <0x174204e0 0x1000>;
};
pmu_system_controller: system-controller@17460000 {
compatible = "google,gs101-pmu", "syscon";
reg = <0x17460000 0x10000>;
};
pinctrl_gpio_alive: pinctrl@174d0000 {
compatible = "google,gs101-pinctrl";
reg = <0x174d0000 0x00001000>;
wakeup-interrupt-controller {
compatible = "google,gs101-wakeup-eint",
"samsung,exynos850-wakeup-eint",
"samsung,exynos7-wakeup-eint";
};
};
pinctrl_far_alive: pinctrl@174e0000 {
compatible = "google,gs101-pinctrl";
reg = <0x174e0000 0x00001000>;
wakeup-interrupt-controller {
compatible = "google,gs101-wakeup-eint",
"samsung,exynos850-wakeup-eint",
"samsung,exynos7-wakeup-eint";
};
};
pinctrl_gsactrl: pinctrl@17940000 {
compatible = "google,gs101-pinctrl";
reg = <0x17940000 0x00001000>;
};
pinctrl_gsacore: pinctrl@17a80000 {
compatible = "google,gs101-pinctrl";
reg = <0x17a80000 0x00001000>;
};
cmu_top: clock-controller@1e080000 {
compatible = "google,gs101-cmu-top";
reg = <0x1e080000 0x8000>;
#clock-cells = <1>;
clocks = <&ext_24_5m>;
clock-names = "oscclk";
};
};
timer {
compatible = "arm,armv8-timer";
interrupts =
<GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>;
};
};
#include "gs101-pinctrl.dtsi"

21
arch/arm64/boot/dts/tesla/fsd.dtsi
View File

@ -342,6 +342,18 @@
#clock-cells = <0>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
mfc_left: region@84000000 {
compatible = "shared-dma-pool";
no-map;
reg = <0 0x84000000 0 0x8000000>;
};
};
soc: soc@0 {
compatible = "simple-bus";
#address-cells = <2>;
@ -956,6 +968,15 @@
clock-names = "fin_pll", "mct";
};
mfc: mfc@12880000 {
compatible = "tesla,fsd-mfc";
reg = <0x0 0x12880000 0x0 0x10000>;
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "mfc";
clocks = <&clock_mfc MFC_MFC_IPCLKPORT_ACLK>;
memory-region = <&mfc_left>;
};
ufs: ufs@15120000 {
compatible = "tesla,fsd-ufs";
reg = <0x0 0x15120000 0x0 0x200>, /* 0: HCI standard */