phy: usb: suppress OC condition for 7439b2
We hit a false positive OC for 7439b2 in DRD/device mode for the second port. So disable the OC check for this use case. Add capability to suppress OC condition for specific ports. Signed-off-by: Justin Chen <justin.chen@broadcom.com> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Link: https://lore.kernel.org/r/1686859578-45242-3-git-send-email-justin.chen@broadcom.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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@ -35,6 +35,11 @@
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#define USB_CTRL_SETUP_STRAP_IPP_SEL_MASK BIT(25) /* option */
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#define USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK BIT(26) /* option */
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#define USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK BIT(27) /* opt */
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#define USB_CTRL_SETUP_OC_DISABLE_PORT0_MASK BIT(28)
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#define USB_CTRL_SETUP_OC_DISABLE_PORT1_MASK BIT(29)
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#define USB_CTRL_SETUP_OC_DISABLE_MASK GENMASK(29, 28) /* option */
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#define USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK BIT(30)
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#define USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK BIT(31)
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#define USB_CTRL_SETUP_OC3_DISABLE_MASK GENMASK(31, 30) /* option */
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#define USB_CTRL_PLL_CTL 0x04
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#define USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_MASK BIT(27)
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@ -114,6 +119,8 @@ enum {
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USB_CTRL_SETUP_SCB2_EN_SELECTOR,
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USB_CTRL_SETUP_SS_EHCI64BIT_EN_SELECTOR,
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USB_CTRL_SETUP_STRAP_IPP_SEL_SELECTOR,
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USB_CTRL_SETUP_OC3_DISABLE_PORT0_SELECTOR,
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USB_CTRL_SETUP_OC3_DISABLE_PORT1_SELECTOR,
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USB_CTRL_SETUP_OC3_DISABLE_SELECTOR,
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USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_SELECTOR,
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USB_CTRL_USB_PM_BDC_SOFT_RESETB_SELECTOR,
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@ -190,6 +197,8 @@ usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = {
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USB_CTRL_SETUP_SCB2_EN_MASK,
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USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
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USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
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USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK,
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USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK,
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USB_CTRL_SETUP_OC3_DISABLE_MASK,
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0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
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0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
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@ -232,6 +241,8 @@ usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = {
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USB_CTRL_SETUP_SCB2_EN_MASK,
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USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
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0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */
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USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK,
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USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK,
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USB_CTRL_SETUP_OC3_DISABLE_MASK,
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USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK,
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0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
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@ -253,6 +264,8 @@ usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = {
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0, /* USB_CTRL_SETUP_SCB2_EN_MASK */
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USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
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USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
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USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK,
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USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK,
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USB_CTRL_SETUP_OC3_DISABLE_MASK,
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0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
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USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK,
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@ -274,6 +287,8 @@ usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = {
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USB_CTRL_SETUP_SCB2_EN_MASK,
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USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
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0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */
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USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK,
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USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK,
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USB_CTRL_SETUP_OC3_DISABLE_MASK,
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USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK,
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0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
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@ -295,6 +310,8 @@ usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = {
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USB_CTRL_SETUP_SCB2_EN_MASK,
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USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
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0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */
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USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK,
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USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK,
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USB_CTRL_SETUP_OC3_DISABLE_MASK,
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0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
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0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
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@ -316,6 +333,8 @@ usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = {
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USB_CTRL_SETUP_SCB2_EN_MASK,
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USB_CTRL_SETUP_SS_EHCI64BIT_EN_VAR_MASK,
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0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */
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0, /* USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK */
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0, /* USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK */
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0, /* USB_CTRL_SETUP_OC3_DISABLE_MASK */
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USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK,
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0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
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@ -337,6 +356,8 @@ usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = {
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USB_CTRL_SETUP_SCB2_EN_MASK,
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USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
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USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
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USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK,
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USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK,
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USB_CTRL_SETUP_OC3_DISABLE_MASK,
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0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
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USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK,
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@ -358,6 +379,8 @@ usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = {
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USB_CTRL_SETUP_SCB2_EN_MASK,
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USB_CTRL_SETUP_SS_EHCI64BIT_EN_VAR_MASK,
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0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */
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USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK,
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USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK,
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USB_CTRL_SETUP_OC3_DISABLE_MASK,
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USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK,
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0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
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@ -379,6 +402,8 @@ usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = {
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0, /* USB_CTRL_SETUP_SCB2_EN_MASK */
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USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
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USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
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USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK,
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USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK,
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USB_CTRL_SETUP_OC3_DISABLE_MASK,
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0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
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USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK,
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@ -400,6 +425,8 @@ usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = {
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0, /* USB_CTRL_SETUP_SCB2_EN_MASK */
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0, /*USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK */
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USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
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USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK,
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USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK,
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USB_CTRL_SETUP_OC3_DISABLE_MASK,
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0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
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USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK,
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@ -872,6 +899,13 @@ static void usb_init_common(struct brcm_usb_init_params *params)
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brcmusb_memc_fix(params);
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/* Workaround for false positive OC for 7439b2 in DRD/Device mode */
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if ((params->family_id == 0x74390012) &&
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(params->supported_port_modes != USB_CTLR_MODE_HOST)) {
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USB_CTRL_SET(ctrl, SETUP, OC_DISABLE_PORT1);
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USB_CTRL_SET_FAMILY(params, SETUP, OC3_DISABLE_PORT1);
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}
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if (USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1, PORT_MODE)) {
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reg = brcm_usb_readl(USB_CTRL_REG(ctrl, USB_DEVICE_CTL1));
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reg &= ~USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1,
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