dt-bindings: riscv: fix SiFive l2-cache's cache-sets
commit b60cf8e59e61133b6c9514ff8d8c8d7049d040ef upstream. Fix device tree schema validation error messages for the SiFive Unmatched: ' cache-sets:0:0: 1024 was expected'. The existing bindings allow for just 1024 cache-sets but the fu740 on Unmatched the has 2048 cache-sets. The ISA itself permits any arbitrary power of two, however this is not supported by dt-schema. The RTL for the IP, to which the number of cache-sets is a tunable parameter, has been released publicly so speculatively adding a small number of "reasonable" values seems unwise also. Instead, as the binding only supports two distinct controllers: add 2048 and explicitly lock it to the fu740's l2 cache while limiting 1024 to the l2 cache on the fu540. Fixes: af951c3a113b ("dt-bindings: riscv: Update l2 cache DT documentation to add support for SiFive FU740") Reported-by: Atul Khare <atulkhare@rivosinc.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20220803185359.942928-1-mail@conchuod.ie Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -46,7 +46,7 @@ properties:
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const: 2
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cache-sets:
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const: 1024
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enum: [1024, 2048]
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cache-size:
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const: 2097152
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@ -84,6 +84,8 @@ then:
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description: |
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Must contain entries for DirError, DataError and DataFail signals.
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maxItems: 3
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cache-sets:
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const: 1024
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else:
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properties:
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@ -91,6 +93,8 @@ else:
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description: |
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Must contain entries for DirError, DataError, DataFail, DirFail signals.
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minItems: 4
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cache-sets:
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const: 2048
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additionalProperties: false
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