[ARM] 4311/1: ixp4xx: add KIXRP435 platform
Add Intel KIXRP435 Reference Platform based on IXP43x processor. Fixed after review : access to cp15 removed in identification functions, used access to global processor_id instead Signed-off-by: Vladimir Barinov <vbarinov@ru.mvista.com> Signed-off-by: Ruslan Sushko <rsushko@ru.mvista.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -117,11 +117,13 @@ CONFIG_ARCH_ADI_COYOTE=y
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CONFIG_ARCH_IXDP425=y
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CONFIG_MACH_IXDPG425=y
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CONFIG_MACH_IXDP465=y
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CONFIG_MACH_KIXRP435=y
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CONFIG_ARCH_IXCDP1100=y
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CONFIG_ARCH_PRPMC1100=y
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CONFIG_MACH_NAS100D=y
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CONFIG_ARCH_IXDP4XX=y
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CONFIG_CPU_IXP46X=y
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CONFIG_CPU_IXP43X=y
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# CONFIG_MACH_GTWX5715 is not set
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#
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@ -62,6 +62,12 @@ config MACH_IXDP465
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IXDP465 Development Platform (Also known as BMP).
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For more information on this platform, see <file:Documentation/arm/IXP4xx>.
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config MACH_KIXRP435
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bool "KIXRP435"
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help
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Say 'Y' here if you want your kernel to support Intel's
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KIXRP435 Reference Platform.
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For more information on this platform, see <file:Documentation/arm/IXP4xx>.
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#
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# IXCDP1100 is the exact same HW as IXDP425, but with a different machine
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@ -94,7 +100,7 @@ config MACH_NAS100D
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#
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config ARCH_IXDP4XX
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bool
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depends on ARCH_IXDP425 || MACH_IXDP465
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depends on ARCH_IXDP425 || MACH_IXDP465 || MACH_KIXRP435
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default y
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#
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@ -105,6 +111,11 @@ config CPU_IXP46X
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depends on MACH_IXDP465
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default y
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config CPU_IXP43X
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bool
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depends on MACH_KIXRP435
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default y
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config MACH_GTWX5715
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bool "Gemtek WX5715 (Linksys WRV54G)"
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depends on ARCH_IXP4XX
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@ -374,7 +374,7 @@ void __init ixp4xx_pci_preinit(void)
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* Determine which PCI read method to use.
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* Rev 0 IXP425 requires workaround.
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*/
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if (!(processor_id & 0xf) && !cpu_is_ixp46x()) {
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if (!(processor_id & 0xf) && cpu_is_ixp42x()) {
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printk("PCI: IXP42x A0 silicon detected - "
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"PCI Non-Prefetch Workaround Enabled\n");
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ixp4xx_pci_read = ixp4xx_pci_read_errata;
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@ -480,7 +480,7 @@ int ixp4xx_setup(int nr, struct pci_sys_data *sys)
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res[0].flags = IORESOURCE_IO;
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res[1].name = "PCI Memory Space";
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res[1].start = 0x48000000;
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res[1].start = PCIBIOS_MIN_MEM;
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#ifndef CONFIG_IXP4XX_INDIRECT_PCI
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res[1].end = 0x4bffffff;
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#else
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@ -192,7 +192,7 @@ static int ixp4xx_set_irq_type(unsigned int irq, unsigned int type)
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static void ixp4xx_irq_mask(unsigned int irq)
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{
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if (cpu_is_ixp46x() && irq >= 32)
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if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && irq >= 32)
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*IXP4XX_ICMR2 &= ~(1 << (irq - 32));
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else
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*IXP4XX_ICMR &= ~(1 << irq);
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@ -215,7 +215,7 @@ static void ixp4xx_irq_unmask(unsigned int irq)
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if (!(ixp4xx_irq_edge & (1 << irq)))
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ixp4xx_irq_ack(irq);
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if (cpu_is_ixp46x() && irq >= 32)
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if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && irq >= 32)
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*IXP4XX_ICMR2 |= (1 << (irq - 32));
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else
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*IXP4XX_ICMR |= (1 << irq);
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@ -239,7 +239,7 @@ void __init ixp4xx_init_irq(void)
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/* Disable all interrupt */
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*IXP4XX_ICMR = 0x0;
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if (cpu_is_ixp46x()) {
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if (cpu_is_ixp46x() || cpu_is_ixp43x()) {
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/* Route upper 32 sources to IRQ instead of FIQ */
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*IXP4XX_ICLR2 = 0x00;
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@ -66,7 +66,7 @@ struct hw_pci ixdp425_pci __initdata = {
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int __init ixdp425_pci_init(void)
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{
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if (machine_is_ixdp425() || machine_is_ixcdp1100() ||
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machine_is_ixdp465())
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machine_is_ixdp465() || machine_is_kixrp435())
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pci_common_init(&ixdp425_pci);
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return 0;
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}
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@ -115,6 +115,11 @@ static void __init ixdp425_init(void)
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ixdp425_flash_resource.end =
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IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
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if (cpu_is_ixp43x()) {
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ixdp425_uart.num_resources = 1;
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ixdp425_uart_data[1].flags = 0;
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}
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platform_add_devices(ixdp425_devices, ARRAY_SIZE(ixdp425_devices));
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}
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@ -156,3 +161,16 @@ MACHINE_START(IXCDP1100, "Intel IXCDP1100 Development Platform")
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.init_machine = ixdp425_init,
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MACHINE_END
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#endif
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#ifdef CONFIG_MACH_KIXRP435
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MACHINE_START(KIXRP435, "Intel KIXRP435 Reference Platform")
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/* Maintainer: MontaVista Software, Inc. */
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.phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
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.io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
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.map_io = ixp4xx_map_io,
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.init_irq = ixp4xx_init_irq,
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.timer = &ixp4xx_timer,
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.boot_params = 0x0100,
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.init_machine = ixdp425_init,
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MACHINE_END
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#endif
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@ -584,6 +584,11 @@ cpu_ixp42x_name:
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.asciz "XScale-IXP42x Family"
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.size cpu_ixp42x_name, . - cpu_ixp42x_name
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.type cpu_ixp43x_name, #object
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cpu_ixp43x_name:
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.asciz "XScale-IXP43x Family"
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.size cpu_ixp43x_name, . - cpu_ixp43x_name
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.type cpu_ixp46x_name, #object
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cpu_ixp46x_name:
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.asciz "XScale-IXP46x Family"
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@ -843,6 +848,29 @@ __ixp42x_proc_info:
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.long xscale_cache_fns
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.size __ixp42x_proc_info, . - __ixp42x_proc_info
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.type __ixp43x_proc_info, #object
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__ixp43x_proc_info:
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.long 0x69054040
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.long 0xfffffff0
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.long PMD_TYPE_SECT | \
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PMD_SECT_BUFFERABLE | \
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PMD_SECT_CACHEABLE | \
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PMD_SECT_AP_WRITE | \
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PMD_SECT_AP_READ
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.long PMD_TYPE_SECT | \
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PMD_SECT_AP_WRITE | \
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PMD_SECT_AP_READ
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b __xscale_setup
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.long cpu_arch_name
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.long cpu_elf_name
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.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
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.long cpu_ixp43x_name
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.long xscale_processor_functions
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.long v4wbi_tlb_fns
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.long xscale_mc_user_fns
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.long xscale_cache_fns
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.size __ixp43x_proc_info, . - __ixp43x_proc_info
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.type __ixp46x_proc_info, #object
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__ixp46x_proc_info:
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.long 0x69054200
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@ -31,9 +31,9 @@
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1001:
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/*
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* IXP465 has an upper IRQ status register
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* IXP465/IXP435 has an upper IRQ status register
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*/
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#if defined(CONFIG_CPU_IXP46X)
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#if defined(CONFIG_CPU_IXP46X) || defined(CONFIG_CPU_IXP43X)
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ldr \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP2_OFFSET)
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ldr \irqstat, [\irqstat] @ get upper interrupts
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mov \irqnr, #63
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@ -17,8 +17,8 @@
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#ifndef __ASM_ARCH_HARDWARE_H__
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#define __ASM_ARCH_HARDWARE_H__
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#define PCIBIOS_MIN_IO 0x00001000
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#define PCIBIOS_MIN_MEM 0x48000000
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#define PCIBIOS_MIN_IO 0x00001000
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#define PCIBIOS_MIN_MEM (cpu_is_ixp43x() ? 0x40000000 : 0x48000000)
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/*
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* We override the standard dma-mask routines for bouncing.
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@ -61,7 +61,7 @@ extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
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static inline void __iomem *
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__ixp4xx_ioremap(unsigned long addr, size_t size, unsigned long flags)
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{
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if((addr < 0x48000000) || (addr > 0x4fffffff))
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if((addr < PCIBIOS_MIN_MEM) || (addr > 0x4fffffff))
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return __ioremap(addr, size, flags);
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return (void *)addr;
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@ -62,10 +62,10 @@
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/*
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* Only first 32 sources are valid if running on IXP42x systems
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*/
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#ifndef CONFIG_CPU_IXP46X
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#define NR_IRQS 32
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#else
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#if defined(CONFIG_CPU_IXP46X) || defined(CONFIG_CPU_IXP43X)
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#define NR_IRQS 64
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#else
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#define NR_IRQS 32
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#endif
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#define XSCALE_PMU_IRQ (IRQ_IXP4XX_XSCALE_PMU)
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@ -607,15 +607,43 @@
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#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
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/* Processor id value in CP15 Register 0 */
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#define IXP425_PROCESSOR_ID_VALUE 0x690541c0
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#define IXP435_PROCESSOR_ID_VALUE 0x69054040
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#define IXP465_PROCESSOR_ID_VALUE 0x69054200
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#define IXP4XX_PROCESSOR_ID_MASK 0xfffffff0
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#ifndef __ASSEMBLY__
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static inline int cpu_is_ixp42x(void)
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{
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extern unsigned int processor_id;
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if ((processor_id & IXP4XX_PROCESSOR_ID_MASK) ==
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IXP425_PROCESSOR_ID_VALUE )
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return 1;
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return 0;
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}
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static inline int cpu_is_ixp43x(void)
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{
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#ifdef CONFIG_CPU_IXP43X
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extern unsigned int processor_id;
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if ((processor_id & IXP4XX_PROCESSOR_ID_MASK) ==
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IXP435_PROCESSOR_ID_VALUE )
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return 1;
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#endif
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return 0;
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}
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static inline int cpu_is_ixp46x(void)
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{
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#ifdef CONFIG_CPU_IXP46X
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unsigned int processor_id;
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extern unsigned int processor_id;
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asm("mrc p15, 0, %0, cr0, cr0, 0;" : "=r"(processor_id) :);
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if ((processor_id & 0xffffff00) == 0x69054200)
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if ((processor_id & IXP4XX_PROCESSOR_ID_MASK) ==
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IXP465_PROCESSOR_ID_VALUE )
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return 1;
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#endif
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return 0;
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