interconnect changes for 5.13
These are the interconnect changes for the 5.13-rc1 merge window with the highlights being drivers for two new platforms. Driver changes: - New driver for SM8350 platforms. - New driver for SDM660 platforms. Signed-off-by: Georgi Djakov <djakov@kernel.org> -----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJgd/GZAAoJEIDQzArG2BZjJ3kP/jgsX2Z5J4/PqKgWaK8iFYs7 5DlDkX4Ogb61LXoAZrrKKAW8HLTKGrGB+AdfBMPT8nU865Js+EdWJXRrOmmPlaUn CFYct8ABRfip38VLkfyv6LDbfd43lIk8c809JFQiLQ9uFZSy5ZW/Vvh9ZCsMCSF6 Id7hKNzevTM3i0U8mLYJyhvrQ2G5qQUiiuQNeUJxt6Cl2hdzsk13MhdL5pFYwdJA WAEu3+Wcj3PeMo7+bWJO/VV5MswhHtYhS8hF/HsPYmtDTgNUkkMAXiFArBO1wB8H RgRLPTOUcJq8YgqWYFoaAVn1Gp2SDWyCK/c0CcLuh/rILrpICCJrHPmoS3V/beJk B+GPLilSN51KSvvkO/naiS/30lgF2a2355IXOfT4EKyEgVlmMmM8FmdfLkEfqQbI nTT/mTDghrkCkx+n1mLu1T5o7kty+9PVAz6vz7N2evFSJrUC7VFhsY1ZKDPOBrgY sr34SYS2SnkCyu32hga/nMKEqYmKLyY2WsQuDM0ExJP+MnvgzNj31fdXh6iRb9YB 34/smWyfBnzyIxIhL8bJiRvnHwIerLKdyCMzO2WMaBY436WeNK7xI38zMLqfpqs0 3ntatJeE1E9Y20FUWwdHuHIvqgL0cbw/0JqqdAqLoU8SmPi+nRX4XOFdVu0ckrTy SXCb6lWCHVWDI0/kVYEp =SguC -----END PGP SIGNATURE----- Merge tag 'icc-5.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc into char-misc-next Georgi writes: interconnect changes for 5.13 These are the interconnect changes for the 5.13-rc1 merge window with the highlights being drivers for two new platforms. Driver changes: - New driver for SM8350 platforms. - New driver for SDM660 platforms. Signed-off-by: Georgi Djakov <djakov@kernel.org> * tag 'icc-5.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc: interconnect: qcom: sm8350: Add missing link between nodes interconnect: qcom: sm8350: Use the correct ids interconnect: qcom: sdm660: Fix kerneldoc warning MAINTAINERS: icc: add interconnect tree interconnect: qcom: Add SM8350 interconnect provider driver dt-bindings: interconnect: Add Qualcomm SM8350 DT bindings interconnect: qcom: icc-rpm: record slave RPM id in error log interconnect: qcom: Add SDM660 interconnect provider driver dt-bindings: interconnect: Add bindings for Qualcomm SDM660 NoC
This commit is contained in:
Greg Kroah-Hartman
commit
4615df5df2
@ -71,6 +71,16 @@ properties:
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- qcom,sm8250-mmss-noc
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- qcom,sm8250-npu-noc
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- qcom,sm8250-system-noc
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- qcom,sm8350-aggre1-noc
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- qcom,sm8350-aggre2-noc
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- qcom,sm8350-config-noc
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- qcom,sm8350-dc-noc
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- qcom,sm8350-gem-noc
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- qcom,sm8350-lpass-ag-noc
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- qcom,sm8350-mc-virt
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- qcom,sm8350-mmss-noc
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- qcom,sm8350-compute-noc
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- qcom,sm8350-system-noc
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'#interconnect-cells':
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enum: [ 1, 2 ]
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147
Documentation/devicetree/bindings/interconnect/qcom,sdm660.yaml
Normal file
147
Documentation/devicetree/bindings/interconnect/qcom,sdm660.yaml
Normal file
@ -0,0 +1,147 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interconnect/qcom,sdm660.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm SDM660 Network-On-Chip interconnect
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maintainers:
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- AngeloGioacchino Del Regno <kholk11@gmail.com>
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description: |
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The Qualcomm SDM660 interconnect providers support adjusting the
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bandwidth requirements between the various NoC fabrics.
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properties:
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reg:
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maxItems: 1
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compatible:
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enum:
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- qcom,sdm660-a2noc
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- qcom,sdm660-bimc
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- qcom,sdm660-cnoc
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- qcom,sdm660-gnoc
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- qcom,sdm660-mnoc
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- qcom,sdm660-snoc
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'#interconnect-cells':
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const: 1
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clocks:
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minItems: 1
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maxItems: 3
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clock-names:
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minItems: 1
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maxItems: 3
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required:
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- compatible
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- reg
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- '#interconnect-cells'
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- clock-names
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- clocks
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additionalProperties: false
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,sdm660-mnoc
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then:
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properties:
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clocks:
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items:
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- description: Bus Clock.
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- description: Bus A Clock.
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- description: CPU-NoC High-performance Bus Clock.
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clock-names:
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items:
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- const: bus
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- const: bus_a
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- const: iface
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,sdm660-a2noc
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- qcom,sdm660-bimc
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- qcom,sdm660-cnoc
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- qcom,sdm660-gnoc
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- qcom,sdm660-snoc
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then:
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properties:
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clocks:
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items:
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- description: Bus Clock.
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- description: Bus A Clock.
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clock-names:
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items:
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- const: bus
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- const: bus_a
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmcc.h>
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#include <dt-bindings/clock/qcom,mmcc-sdm660.h>
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bimc: interconnect@1008000 {
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compatible = "qcom,sdm660-bimc";
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reg = <0x01008000 0x78000>;
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#interconnect-cells = <1>;
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clock-names = "bus", "bus_a";
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clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
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<&rpmcc RPM_SMD_BIMC_A_CLK>;
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};
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cnoc: interconnect@1500000 {
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compatible = "qcom,sdm660-cnoc";
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reg = <0x01500000 0x10000>;
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#interconnect-cells = <1>;
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clock-names = "bus", "bus_a";
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clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
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<&rpmcc RPM_SMD_CNOC_A_CLK>;
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};
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snoc: interconnect@1626000 {
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compatible = "qcom,sdm660-snoc";
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reg = <0x01626000 0x7090>;
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#interconnect-cells = <1>;
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clock-names = "bus", "bus_a";
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clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
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<&rpmcc RPM_SMD_SNOC_A_CLK>;
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};
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a2noc: interconnect@1704000 {
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compatible = "qcom,sdm660-a2noc";
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reg = <0x01704000 0xc100>;
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#interconnect-cells = <1>;
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clock-names = "bus", "bus_a";
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clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
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<&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>;
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};
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mnoc: interconnect@1745000 {
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compatible = "qcom,sdm660-mnoc";
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reg = <0x01745000 0xa010>;
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#interconnect-cells = <1>;
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clock-names = "bus", "bus_a", "iface";
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clocks = <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
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<&rpmcc RPM_SMD_MMSSNOC_AXI_CLK_A>,
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<&mmcc AHB_CLK_SRC>;
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};
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gnoc: interconnect@17900000 {
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compatible = "qcom,sdm660-gnoc";
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reg = <0x17900000 0xe000>;
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#interconnect-cells = <1>;
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clock-names = "bus", "bus_a";
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clocks = <&xo_board>, <&xo_board>;
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};
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@ -9297,6 +9297,7 @@ INTERCONNECT API
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M: Georgi Djakov <djakov@kernel.org>
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L: linux-pm@vger.kernel.org
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S: Maintained
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc.git
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F: Documentation/devicetree/bindings/interconnect/
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F: Documentation/driver-api/interconnect.rst
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F: drivers/interconnect/
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@ -74,6 +74,15 @@ config INTERCONNECT_QCOM_SC7180
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This is a driver for the Qualcomm Network-on-Chip on sc7180-based
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platforms.
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config INTERCONNECT_QCOM_SDM660
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tristate "Qualcomm SDM660 interconnect driver"
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depends on INTERCONNECT_QCOM
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depends on QCOM_SMD_RPM
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select INTERCONNECT_QCOM_SMD_RPM
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help
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This is a driver for the Qualcomm Network-on-Chip on sdm660-based
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platforms.
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config INTERCONNECT_QCOM_SDM845
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tristate "Qualcomm SDM845 interconnect driver"
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depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
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@ -110,5 +119,14 @@ config INTERCONNECT_QCOM_SM8250
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This is a driver for the Qualcomm Network-on-Chip on sm8250-based
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platforms.
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config INTERCONNECT_QCOM_SM8350
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tristate "Qualcomm SM8350 interconnect driver"
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depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
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select INTERCONNECT_QCOM_RPMH
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select INTERCONNECT_QCOM_BCM_VOTER
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help
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This is a driver for the Qualcomm Network-on-Chip on SM8350-based
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platforms.
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config INTERCONNECT_QCOM_SMD_RPM
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tristate
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@ -8,10 +8,12 @@ icc-osm-l3-objs := osm-l3.o
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qnoc-qcs404-objs := qcs404.o
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icc-rpmh-obj := icc-rpmh.o
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qnoc-sc7180-objs := sc7180.o
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qnoc-sdm660-objs := sdm660.o
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qnoc-sdm845-objs := sdm845.o
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qnoc-sdx55-objs := sdx55.o
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qnoc-sm8150-objs := sm8150.o
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qnoc-sm8250-objs := sm8250.o
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qnoc-sm8350-objs := sm8350.o
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icc-smd-rpm-objs := smd-rpm.o icc-rpm.o
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obj-$(CONFIG_INTERCONNECT_QCOM_BCM_VOTER) += icc-bcm-voter.o
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@ -22,8 +24,10 @@ obj-$(CONFIG_INTERCONNECT_QCOM_OSM_L3) += icc-osm-l3.o
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obj-$(CONFIG_INTERCONNECT_QCOM_QCS404) += qnoc-qcs404.o
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obj-$(CONFIG_INTERCONNECT_QCOM_RPMH) += icc-rpmh.o
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obj-$(CONFIG_INTERCONNECT_QCOM_SC7180) += qnoc-sc7180.o
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obj-$(CONFIG_INTERCONNECT_QCOM_SDM660) += qnoc-sdm660.o
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obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) += qnoc-sdm845.o
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obj-$(CONFIG_INTERCONNECT_QCOM_SDX55) += qnoc-sdx55.o
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obj-$(CONFIG_INTERCONNECT_QCOM_SM8150) += qnoc-sm8150.o
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obj-$(CONFIG_INTERCONNECT_QCOM_SM8250) += qnoc-sm8250.o
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obj-$(CONFIG_INTERCONNECT_QCOM_SM8350) += qnoc-sm8350.o
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obj-$(CONFIG_INTERCONNECT_QCOM_SMD_RPM) += icc-smd-rpm.o
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@ -59,8 +59,8 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
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qn->slv_rpm_id,
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sum_bw);
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if (ret) {
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pr_err("qcom_icc_rpm_smd_send slv error %d\n",
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ret);
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pr_err("qcom_icc_rpm_smd_send slv %d error %d\n",
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qn->slv_rpm_id, ret);
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return ret;
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}
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}
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923
drivers/interconnect/qcom/sdm660.c
Normal file
923
drivers/interconnect/qcom/sdm660.c
Normal file
@ -0,0 +1,923 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Qualcomm SDM630/SDM636/SDM660 Network-on-Chip (NoC) QoS driver
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* Copyright (C) 2020, AngeloGioacchino Del Regno <kholk11@gmail.com>
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*/
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#include <dt-bindings/interconnect/qcom,sdm660.h>
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/interconnect-provider.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include "smd-rpm.h"
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#define RPM_BUS_MASTER_REQ 0x73616d62
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#define RPM_BUS_SLAVE_REQ 0x766c7362
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/* BIMC QoS */
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#define M_BKE_REG_BASE(n) (0x300 + (0x4000 * n))
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#define M_BKE_EN_ADDR(n) (M_BKE_REG_BASE(n))
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#define M_BKE_HEALTH_CFG_ADDR(i, n) (M_BKE_REG_BASE(n) + 0x40 + (0x4 * i))
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#define M_BKE_HEALTH_CFG_LIMITCMDS_MASK 0x80000000
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#define M_BKE_HEALTH_CFG_AREQPRIO_MASK 0x300
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#define M_BKE_HEALTH_CFG_PRIOLVL_MASK 0x3
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#define M_BKE_HEALTH_CFG_AREQPRIO_SHIFT 0x8
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#define M_BKE_HEALTH_CFG_LIMITCMDS_SHIFT 0x1f
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#define M_BKE_EN_EN_BMASK 0x1
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/* Valid for both NoC and BIMC */
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#define NOC_QOS_MODE_FIXED 0x0
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#define NOC_QOS_MODE_LIMITER 0x1
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#define NOC_QOS_MODE_BYPASS 0x2
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/* NoC QoS */
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#define NOC_PERM_MODE_FIXED 1
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#define NOC_PERM_MODE_BYPASS (1 << NOC_QOS_MODE_BYPASS)
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#define NOC_QOS_PRIORITYn_ADDR(n) (0x8 + (n * 0x1000))
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#define NOC_QOS_PRIORITY_MASK 0xf
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#define NOC_QOS_PRIORITY_P1_SHIFT 0x2
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#define NOC_QOS_PRIORITY_P0_SHIFT 0x3
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#define NOC_QOS_MODEn_ADDR(n) (0xc + (n * 0x1000))
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#define NOC_QOS_MODEn_MASK 0x3
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enum {
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SDM660_MASTER_IPA = 1,
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SDM660_MASTER_CNOC_A2NOC,
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SDM660_MASTER_SDCC_1,
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SDM660_MASTER_SDCC_2,
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SDM660_MASTER_BLSP_1,
|
||||
SDM660_MASTER_BLSP_2,
|
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SDM660_MASTER_UFS,
|
||||
SDM660_MASTER_USB_HS,
|
||||
SDM660_MASTER_USB3,
|
||||
SDM660_MASTER_CRYPTO_C0,
|
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SDM660_MASTER_GNOC_BIMC,
|
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SDM660_MASTER_OXILI,
|
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SDM660_MASTER_MNOC_BIMC,
|
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SDM660_MASTER_SNOC_BIMC,
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SDM660_MASTER_PIMEM,
|
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SDM660_MASTER_SNOC_CNOC,
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SDM660_MASTER_QDSS_DAP,
|
||||
SDM660_MASTER_APPS_PROC,
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SDM660_MASTER_CNOC_MNOC_MMSS_CFG,
|
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SDM660_MASTER_CNOC_MNOC_CFG,
|
||||
SDM660_MASTER_CPP,
|
||||
SDM660_MASTER_JPEG,
|
||||
SDM660_MASTER_MDP_P0,
|
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SDM660_MASTER_MDP_P1,
|
||||
SDM660_MASTER_VENUS,
|
||||
SDM660_MASTER_VFE,
|
||||
SDM660_MASTER_QDSS_ETR,
|
||||
SDM660_MASTER_QDSS_BAM,
|
||||
SDM660_MASTER_SNOC_CFG,
|
||||
SDM660_MASTER_BIMC_SNOC,
|
||||
SDM660_MASTER_A2NOC_SNOC,
|
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SDM660_MASTER_GNOC_SNOC,
|
||||
|
||||
SDM660_SLAVE_A2NOC_SNOC,
|
||||
SDM660_SLAVE_EBI,
|
||||
SDM660_SLAVE_HMSS_L3,
|
||||
SDM660_SLAVE_BIMC_SNOC,
|
||||
SDM660_SLAVE_CNOC_A2NOC,
|
||||
SDM660_SLAVE_MPM,
|
||||
SDM660_SLAVE_PMIC_ARB,
|
||||
SDM660_SLAVE_TLMM_NORTH,
|
||||
SDM660_SLAVE_TCSR,
|
||||
SDM660_SLAVE_PIMEM_CFG,
|
||||
SDM660_SLAVE_IMEM_CFG,
|
||||
SDM660_SLAVE_MESSAGE_RAM,
|
||||
SDM660_SLAVE_GLM,
|
||||
SDM660_SLAVE_BIMC_CFG,
|
||||
SDM660_SLAVE_PRNG,
|
||||
SDM660_SLAVE_SPDM,
|
||||
SDM660_SLAVE_QDSS_CFG,
|
||||
SDM660_SLAVE_CNOC_MNOC_CFG,
|
||||
SDM660_SLAVE_SNOC_CFG,
|
||||
SDM660_SLAVE_QM_CFG,
|
||||
SDM660_SLAVE_CLK_CTL,
|
||||
SDM660_SLAVE_MSS_CFG,
|
||||
SDM660_SLAVE_TLMM_SOUTH,
|
||||
SDM660_SLAVE_UFS_CFG,
|
||||
SDM660_SLAVE_A2NOC_CFG,
|
||||
SDM660_SLAVE_A2NOC_SMMU_CFG,
|
||||
SDM660_SLAVE_GPUSS_CFG,
|
||||
SDM660_SLAVE_AHB2PHY,
|
||||
SDM660_SLAVE_BLSP_1,
|
||||
SDM660_SLAVE_SDCC_1,
|
||||
SDM660_SLAVE_SDCC_2,
|
||||
SDM660_SLAVE_TLMM_CENTER,
|
||||
SDM660_SLAVE_BLSP_2,
|
||||
SDM660_SLAVE_PDM,
|
||||
SDM660_SLAVE_CNOC_MNOC_MMSS_CFG,
|
||||
SDM660_SLAVE_USB_HS,
|
||||
SDM660_SLAVE_USB3_0,
|
||||
SDM660_SLAVE_SRVC_CNOC,
|
||||
SDM660_SLAVE_GNOC_BIMC,
|
||||
SDM660_SLAVE_GNOC_SNOC,
|
||||
SDM660_SLAVE_CAMERA_CFG,
|
||||
SDM660_SLAVE_CAMERA_THROTTLE_CFG,
|
||||
SDM660_SLAVE_MISC_CFG,
|
||||
SDM660_SLAVE_VENUS_THROTTLE_CFG,
|
||||
SDM660_SLAVE_VENUS_CFG,
|
||||
SDM660_SLAVE_MMSS_CLK_XPU_CFG,
|
||||
SDM660_SLAVE_MMSS_CLK_CFG,
|
||||
SDM660_SLAVE_MNOC_MPU_CFG,
|
||||
SDM660_SLAVE_DISPLAY_CFG,
|
||||
SDM660_SLAVE_CSI_PHY_CFG,
|
||||
SDM660_SLAVE_DISPLAY_THROTTLE_CFG,
|
||||
SDM660_SLAVE_SMMU_CFG,
|
||||
SDM660_SLAVE_MNOC_BIMC,
|
||||
SDM660_SLAVE_SRVC_MNOC,
|
||||
SDM660_SLAVE_HMSS,
|
||||
SDM660_SLAVE_LPASS,
|
||||
SDM660_SLAVE_WLAN,
|
||||
SDM660_SLAVE_CDSP,
|
||||
SDM660_SLAVE_IPA,
|
||||
SDM660_SLAVE_SNOC_BIMC,
|
||||
SDM660_SLAVE_SNOC_CNOC,
|
||||
SDM660_SLAVE_IMEM,
|
||||
SDM660_SLAVE_PIMEM,
|
||||
SDM660_SLAVE_QDSS_STM,
|
||||
SDM660_SLAVE_SRVC_SNOC,
|
||||
|
||||
SDM660_A2NOC,
|
||||
SDM660_BIMC,
|
||||
SDM660_CNOC,
|
||||
SDM660_GNOC,
|
||||
SDM660_MNOC,
|
||||
SDM660_SNOC,
|
||||
};
|
||||
|
||||
#define to_qcom_provider(_provider) \
|
||||
container_of(_provider, struct qcom_icc_provider, provider)
|
||||
|
||||
static const struct clk_bulk_data bus_clocks[] = {
|
||||
{ .id = "bus" },
|
||||
{ .id = "bus_a" },
|
||||
};
|
||||
|
||||
static const struct clk_bulk_data bus_mm_clocks[] = {
|
||||
{ .id = "bus" },
|
||||
{ .id = "bus_a" },
|
||||
{ .id = "iface" },
|
||||
};
|
||||
|
||||
/**
|
||||
* struct qcom_icc_provider - Qualcomm specific interconnect provider
|
||||
* @provider: generic interconnect provider
|
||||
* @bus_clks: the clk_bulk_data table of bus clocks
|
||||
* @num_clks: the total number of clk_bulk_data entries
|
||||
* @is_bimc_node: indicates whether to use bimc specific setting
|
||||
* @regmap: regmap for QoS registers read/write access
|
||||
* @mmio: NoC base iospace
|
||||
*/
|
||||
struct qcom_icc_provider {
|
||||
struct icc_provider provider;
|
||||
struct clk_bulk_data *bus_clks;
|
||||
int num_clks;
|
||||
bool is_bimc_node;
|
||||
struct regmap *regmap;
|
||||
void __iomem *mmio;
|
||||
};
|
||||
|
||||
#define SDM660_MAX_LINKS 34
|
||||
|
||||
/**
|
||||
* struct qcom_icc_qos - Qualcomm specific interconnect QoS parameters
|
||||
* @areq_prio: node requests priority
|
||||
* @prio_level: priority level for bus communication
|
||||
* @limit_commands: activate/deactivate limiter mode during runtime
|
||||
* @ap_owned: indicates if the node is owned by the AP or by the RPM
|
||||
* @qos_mode: default qos mode for this node
|
||||
* @qos_port: qos port number for finding qos registers of this node
|
||||
*/
|
||||
struct qcom_icc_qos {
|
||||
u32 areq_prio;
|
||||
u32 prio_level;
|
||||
bool limit_commands;
|
||||
bool ap_owned;
|
||||
int qos_mode;
|
||||
int qos_port;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct qcom_icc_node - Qualcomm specific interconnect nodes
|
||||
* @name: the node name used in debugfs
|
||||
* @id: a unique node identifier
|
||||
* @links: an array of nodes where we can go next while traversing
|
||||
* @num_links: the total number of @links
|
||||
* @buswidth: width of the interconnect between a node and the bus (bytes)
|
||||
* @mas_rpm_id: RPM id for devices that are bus masters
|
||||
* @slv_rpm_id: RPM id for devices that are bus slaves
|
||||
* @qos: NoC QoS setting parameters
|
||||
* @rate: current bus clock rate in Hz
|
||||
*/
|
||||
struct qcom_icc_node {
|
||||
unsigned char *name;
|
||||
u16 id;
|
||||
u16 links[SDM660_MAX_LINKS];
|
||||
u16 num_links;
|
||||
u16 buswidth;
|
||||
int mas_rpm_id;
|
||||
int slv_rpm_id;
|
||||
struct qcom_icc_qos qos;
|
||||
u64 rate;
|
||||
};
|
||||
|
||||
struct qcom_icc_desc {
|
||||
struct qcom_icc_node **nodes;
|
||||
size_t num_nodes;
|
||||
const struct regmap_config *regmap_cfg;
|
||||
};
|
||||
|
||||
#define DEFINE_QNODE(_name, _id, _buswidth, _mas_rpm_id, _slv_rpm_id, \
|
||||
_ap_owned, _qos_mode, _qos_prio, _qos_port, ...) \
|
||||
static struct qcom_icc_node _name = { \
|
||||
.name = #_name, \
|
||||
.id = _id, \
|
||||
.buswidth = _buswidth, \
|
||||
.mas_rpm_id = _mas_rpm_id, \
|
||||
.slv_rpm_id = _slv_rpm_id, \
|
||||
.qos.ap_owned = _ap_owned, \
|
||||
.qos.qos_mode = _qos_mode, \
|
||||
.qos.areq_prio = _qos_prio, \
|
||||
.qos.prio_level = _qos_prio, \
|
||||
.qos.qos_port = _qos_port, \
|
||||
.num_links = ARRAY_SIZE(((int[]){ __VA_ARGS__ })), \
|
||||
.links = { __VA_ARGS__ }, \
|
||||
}
|
||||
|
||||
DEFINE_QNODE(mas_ipa, SDM660_MASTER_IPA, 8, 59, -1, true, NOC_QOS_MODE_FIXED, 1, 3, SDM660_SLAVE_A2NOC_SNOC);
|
||||
DEFINE_QNODE(mas_cnoc_a2noc, SDM660_MASTER_CNOC_A2NOC, 8, 146, -1, true, -1, 0, -1, SDM660_SLAVE_A2NOC_SNOC);
|
||||
DEFINE_QNODE(mas_sdcc_1, SDM660_MASTER_SDCC_1, 8, 33, -1, false, -1, 0, -1, SDM660_SLAVE_A2NOC_SNOC);
|
||||
DEFINE_QNODE(mas_sdcc_2, SDM660_MASTER_SDCC_2, 8, 35, -1, false, -1, 0, -1, SDM660_SLAVE_A2NOC_SNOC);
|
||||
DEFINE_QNODE(mas_blsp_1, SDM660_MASTER_BLSP_1, 4, 41, -1, false, -1, 0, -1, SDM660_SLAVE_A2NOC_SNOC);
|
||||
DEFINE_QNODE(mas_blsp_2, SDM660_MASTER_BLSP_2, 4, 39, -1, false, -1, 0, -1, SDM660_SLAVE_A2NOC_SNOC);
|
||||
DEFINE_QNODE(mas_ufs, SDM660_MASTER_UFS, 8, 68, -1, true, NOC_QOS_MODE_FIXED, 1, 4, SDM660_SLAVE_A2NOC_SNOC);
|
||||
DEFINE_QNODE(mas_usb_hs, SDM660_MASTER_USB_HS, 8, 42, -1, true, NOC_QOS_MODE_FIXED, 1, 1, SDM660_SLAVE_A2NOC_SNOC);
|
||||
DEFINE_QNODE(mas_usb3, SDM660_MASTER_USB3, 8, 32, -1, true, NOC_QOS_MODE_FIXED, 1, 2, SDM660_SLAVE_A2NOC_SNOC);
|
||||
DEFINE_QNODE(mas_crypto, SDM660_MASTER_CRYPTO_C0, 8, 23, -1, true, NOC_QOS_MODE_FIXED, 1, 11, SDM660_SLAVE_A2NOC_SNOC);
|
||||
DEFINE_QNODE(mas_gnoc_bimc, SDM660_MASTER_GNOC_BIMC, 4, 144, -1, true, NOC_QOS_MODE_FIXED, 0, 0, SDM660_SLAVE_EBI);
|
||||
DEFINE_QNODE(mas_oxili, SDM660_MASTER_OXILI, 4, 6, -1, true, NOC_QOS_MODE_BYPASS, 0, 1, SDM660_SLAVE_HMSS_L3, SDM660_SLAVE_EBI, SDM660_SLAVE_BIMC_SNOC);
|
||||
DEFINE_QNODE(mas_mnoc_bimc, SDM660_MASTER_MNOC_BIMC, 4, 2, -1, true, NOC_QOS_MODE_BYPASS, 0, 2, SDM660_SLAVE_HMSS_L3, SDM660_SLAVE_EBI, SDM660_SLAVE_BIMC_SNOC);
|
||||
DEFINE_QNODE(mas_snoc_bimc, SDM660_MASTER_SNOC_BIMC, 4, 3, -1, false, -1, 0, -1, SDM660_SLAVE_HMSS_L3, SDM660_SLAVE_EBI);
|
||||
DEFINE_QNODE(mas_pimem, SDM660_MASTER_PIMEM, 4, 113, -1, true, NOC_QOS_MODE_FIXED, 1, 4, SDM660_SLAVE_HMSS_L3, SDM660_SLAVE_EBI);
|
||||
DEFINE_QNODE(mas_snoc_cnoc, SDM660_MASTER_SNOC_CNOC, 8, 52, -1, true, -1, 0, -1, SDM660_SLAVE_CLK_CTL, SDM660_SLAVE_QDSS_CFG, SDM660_SLAVE_QM_CFG, SDM660_SLAVE_SRVC_CNOC, SDM660_SLAVE_UFS_CFG, SDM660_SLAVE_TCSR, SDM660_SLAVE_A2NOC_SMMU_CFG, SDM660_SLAVE_SNOC_CFG, SDM660_SLAVE_TLMM_SOUTH, SDM660_SLAVE_MPM, SDM660_SLAVE_CNOC_MNOC_MMSS_CFG, SDM660_SLAVE_SDCC_2, SDM660_SLAVE_SDCC_1, SDM660_SLAVE_SPDM, SDM660_SLAVE_PMIC_ARB, SDM660_SLAVE_PRNG, SDM660_SLAVE_MSS_CFG, SDM660_SLAVE_GPUSS_CFG, SDM660_SLAVE_IMEM_CFG, SDM660_SLAVE_USB3_0, SDM660_SLAVE_A2NOC_CFG, SDM660_SLAVE_TLMM_NORTH, SDM660_SLAVE_USB_HS, SDM660_SLAVE_PDM, SDM660_SLAVE_TLMM_CENTER, SDM660_SLAVE_AHB2PHY, SDM660_SLAVE_BLSP_2, SDM660_SLAVE_BLSP_1, SDM660_SLAVE_PIMEM_CFG, SDM660_SLAVE_GLM, SDM660_SLAVE_MESSAGE_RAM, SDM660_SLAVE_BIMC_CFG, SDM660_SLAVE_CNOC_MNOC_CFG);
|
||||
DEFINE_QNODE(mas_qdss_dap, SDM660_MASTER_QDSS_DAP, 8, 49, -1, true, -1, 0, -1, SDM660_SLAVE_CLK_CTL, SDM660_SLAVE_QDSS_CFG, SDM660_SLAVE_QM_CFG, SDM660_SLAVE_SRVC_CNOC, SDM660_SLAVE_UFS_CFG, SDM660_SLAVE_TCSR, SDM660_SLAVE_A2NOC_SMMU_CFG, SDM660_SLAVE_SNOC_CFG, SDM660_SLAVE_TLMM_SOUTH, SDM660_SLAVE_MPM, SDM660_SLAVE_CNOC_MNOC_MMSS_CFG, SDM660_SLAVE_SDCC_2, SDM660_SLAVE_SDCC_1, SDM660_SLAVE_SPDM, SDM660_SLAVE_PMIC_ARB, SDM660_SLAVE_PRNG, SDM660_SLAVE_MSS_CFG, SDM660_SLAVE_GPUSS_CFG, SDM660_SLAVE_IMEM_CFG, SDM660_SLAVE_USB3_0, SDM660_SLAVE_A2NOC_CFG, SDM660_SLAVE_TLMM_NORTH, SDM660_SLAVE_USB_HS, SDM660_SLAVE_PDM, SDM660_SLAVE_TLMM_CENTER, SDM660_SLAVE_AHB2PHY, SDM660_SLAVE_BLSP_2, SDM660_SLAVE_BLSP_1, SDM660_SLAVE_PIMEM_CFG, SDM660_SLAVE_GLM, SDM660_SLAVE_MESSAGE_RAM, SDM660_SLAVE_CNOC_A2NOC, SDM660_SLAVE_BIMC_CFG, SDM660_SLAVE_CNOC_MNOC_CFG);
|
||||
DEFINE_QNODE(mas_apss_proc, SDM660_MASTER_APPS_PROC, 16, 0, -1, true, -1, 0, -1, SDM660_SLAVE_GNOC_SNOC, SDM660_SLAVE_GNOC_BIMC);
|
||||
DEFINE_QNODE(mas_cnoc_mnoc_mmss_cfg, SDM660_MASTER_CNOC_MNOC_MMSS_CFG, 8, 4, -1, true, -1, 0, -1, SDM660_SLAVE_VENUS_THROTTLE_CFG, SDM660_SLAVE_VENUS_CFG, SDM660_SLAVE_CAMERA_THROTTLE_CFG, SDM660_SLAVE_SMMU_CFG, SDM660_SLAVE_CAMERA_CFG, SDM660_SLAVE_CSI_PHY_CFG, SDM660_SLAVE_DISPLAY_THROTTLE_CFG, SDM660_SLAVE_DISPLAY_CFG, SDM660_SLAVE_MMSS_CLK_CFG, SDM660_SLAVE_MNOC_MPU_CFG, SDM660_SLAVE_MISC_CFG, SDM660_SLAVE_MMSS_CLK_XPU_CFG);
|
||||
DEFINE_QNODE(mas_cnoc_mnoc_cfg, SDM660_MASTER_CNOC_MNOC_CFG, 4, 5, -1, true, -1, 0, -1, SDM660_SLAVE_SRVC_MNOC);
|
||||
DEFINE_QNODE(mas_cpp, SDM660_MASTER_CPP, 16, 115, -1, true, NOC_QOS_MODE_BYPASS, 0, 4, SDM660_SLAVE_MNOC_BIMC);
|
||||
DEFINE_QNODE(mas_jpeg, SDM660_MASTER_JPEG, 16, 7, -1, true, NOC_QOS_MODE_BYPASS, 0, 6, SDM660_SLAVE_MNOC_BIMC);
|
||||
DEFINE_QNODE(mas_mdp_p0, SDM660_MASTER_MDP_P0, 16, 8, -1, true, NOC_QOS_MODE_BYPASS, 0, 0, SDM660_SLAVE_MNOC_BIMC); /* vrail-comp???? */
|
||||
DEFINE_QNODE(mas_mdp_p1, SDM660_MASTER_MDP_P1, 16, 61, -1, true, NOC_QOS_MODE_BYPASS, 0, 1, SDM660_SLAVE_MNOC_BIMC); /* vrail-comp??? */
|
||||
DEFINE_QNODE(mas_venus, SDM660_MASTER_VENUS, 16, 9, -1, true, NOC_QOS_MODE_BYPASS, 0, 1, SDM660_SLAVE_MNOC_BIMC);
|
||||
DEFINE_QNODE(mas_vfe, SDM660_MASTER_VFE, 16, 11, -1, true, NOC_QOS_MODE_BYPASS, 0, 5, SDM660_SLAVE_MNOC_BIMC);
|
||||
DEFINE_QNODE(mas_qdss_etr, SDM660_MASTER_QDSS_ETR, 8, 31, -1, true, NOC_QOS_MODE_FIXED, 1, 1, SDM660_SLAVE_PIMEM, SDM660_SLAVE_IMEM, SDM660_SLAVE_SNOC_CNOC, SDM660_SLAVE_SNOC_BIMC);
|
||||
DEFINE_QNODE(mas_qdss_bam, SDM660_MASTER_QDSS_BAM, 4, 19, -1, true, NOC_QOS_MODE_FIXED, 1, 0, SDM660_SLAVE_PIMEM, SDM660_SLAVE_IMEM, SDM660_SLAVE_SNOC_CNOC, SDM660_SLAVE_SNOC_BIMC);
|
||||
DEFINE_QNODE(mas_snoc_cfg, SDM660_MASTER_SNOC_CFG, 4, 20, -1, false, -1, 0, -1, SDM660_SLAVE_SRVC_SNOC);
|
||||
DEFINE_QNODE(mas_bimc_snoc, SDM660_MASTER_BIMC_SNOC, 8, 21, -1, false, -1, 0, -1, SDM660_SLAVE_PIMEM, SDM660_SLAVE_IPA, SDM660_SLAVE_QDSS_STM, SDM660_SLAVE_LPASS, SDM660_SLAVE_HMSS, SDM660_SLAVE_CDSP, SDM660_SLAVE_SNOC_CNOC, SDM660_SLAVE_WLAN, SDM660_SLAVE_IMEM);
|
||||
DEFINE_QNODE(mas_gnoc_snoc, SDM660_MASTER_GNOC_SNOC, 8, 150, -1, false, -1, 0, -1, SDM660_SLAVE_PIMEM, SDM660_SLAVE_IPA, SDM660_SLAVE_QDSS_STM, SDM660_SLAVE_LPASS, SDM660_SLAVE_HMSS, SDM660_SLAVE_CDSP, SDM660_SLAVE_SNOC_CNOC, SDM660_SLAVE_WLAN, SDM660_SLAVE_IMEM);
|
||||
DEFINE_QNODE(mas_a2noc_snoc, SDM660_MASTER_A2NOC_SNOC, 16, 112, -1, false, -1, 0, -1, SDM660_SLAVE_PIMEM, SDM660_SLAVE_IPA, SDM660_SLAVE_QDSS_STM, SDM660_SLAVE_LPASS, SDM660_SLAVE_HMSS, SDM660_SLAVE_SNOC_BIMC, SDM660_SLAVE_CDSP, SDM660_SLAVE_SNOC_CNOC, SDM660_SLAVE_WLAN, SDM660_SLAVE_IMEM);
|
||||
DEFINE_QNODE(slv_a2noc_snoc, SDM660_SLAVE_A2NOC_SNOC, 16, -1, 143, false, -1, 0, -1, SDM660_MASTER_A2NOC_SNOC);
|
||||
DEFINE_QNODE(slv_ebi, SDM660_SLAVE_EBI, 4, -1, 0, false, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_hmss_l3, SDM660_SLAVE_HMSS_L3, 4, -1, 160, false, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_bimc_snoc, SDM660_SLAVE_BIMC_SNOC, 4, -1, 2, false, -1, 0, -1, SDM660_MASTER_BIMC_SNOC);
|
||||
DEFINE_QNODE(slv_cnoc_a2noc, SDM660_SLAVE_CNOC_A2NOC, 8, -1, 208, true, -1, 0, -1, SDM660_MASTER_CNOC_A2NOC);
|
||||
DEFINE_QNODE(slv_mpm, SDM660_SLAVE_MPM, 4, -1, 62, true, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_pmic_arb, SDM660_SLAVE_PMIC_ARB, 4, -1, 59, true, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_tlmm_north, SDM660_SLAVE_TLMM_NORTH, 8, -1, 214, true, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_tcsr, SDM660_SLAVE_TCSR, 4, -1, 50, true, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_pimem_cfg, SDM660_SLAVE_PIMEM_CFG, 4, -1, 167, true, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_imem_cfg, SDM660_SLAVE_IMEM_CFG, 4, -1, 54, true, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_message_ram, SDM660_SLAVE_MESSAGE_RAM, 4, -1, 55, true, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_glm, SDM660_SLAVE_GLM, 4, -1, 209, true, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_bimc_cfg, SDM660_SLAVE_BIMC_CFG, 4, -1, 56, true, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_prng, SDM660_SLAVE_PRNG, 4, -1, 44, true, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_spdm, SDM660_SLAVE_SPDM, 4, -1, 60, true, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_qdss_cfg, SDM660_SLAVE_QDSS_CFG, 4, -1, 63, true, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_cnoc_mnoc_cfg, SDM660_SLAVE_BLSP_1, 4, -1, 66, true, -1, 0, -1, SDM660_MASTER_CNOC_MNOC_CFG);
|
||||
DEFINE_QNODE(slv_snoc_cfg, SDM660_SLAVE_SNOC_CFG, 4, -1, 70, true, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_qm_cfg, SDM660_SLAVE_QM_CFG, 4, -1, 212, true, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_clk_ctl, SDM660_SLAVE_CLK_CTL, 4, -1, 47, true, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_mss_cfg, SDM660_SLAVE_MSS_CFG, 4, -1, 48, true, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_tlmm_south, SDM660_SLAVE_TLMM_SOUTH, 4, -1, 217, true, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_ufs_cfg, SDM660_SLAVE_UFS_CFG, 4, -1, 92, true, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_a2noc_cfg, SDM660_SLAVE_A2NOC_CFG, 4, -1, 150, true, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_a2noc_smmu_cfg, SDM660_SLAVE_A2NOC_SMMU_CFG, 8, -1, 152, true, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_gpuss_cfg, SDM660_SLAVE_GPUSS_CFG, 8, -1, 11, true, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_ahb2phy, SDM660_SLAVE_AHB2PHY, 4, -1, 163, true, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_blsp_1, SDM660_SLAVE_BLSP_1, 4, -1, 39, true, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_sdcc_1, SDM660_SLAVE_SDCC_1, 4, -1, 31, true, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_sdcc_2, SDM660_SLAVE_SDCC_2, 4, -1, 33, true, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_tlmm_center, SDM660_SLAVE_TLMM_CENTER, 4, -1, 218, true, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_blsp_2, SDM660_SLAVE_BLSP_2, 4, -1, 37, true, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_pdm, SDM660_SLAVE_PDM, 4, -1, 41, true, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_cnoc_mnoc_mmss_cfg, SDM660_SLAVE_CNOC_MNOC_MMSS_CFG, 8, -1, 58, true, -1, 0, -1, SDM660_MASTER_CNOC_MNOC_MMSS_CFG);
|
||||
DEFINE_QNODE(slv_usb_hs, SDM660_SLAVE_USB_HS, 4, -1, 40, true, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_usb3_0, SDM660_SLAVE_USB3_0, 4, -1, 22, true, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_srvc_cnoc, SDM660_SLAVE_SRVC_CNOC, 4, -1, 76, true, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_gnoc_bimc, SDM660_SLAVE_GNOC_BIMC, 16, -1, 210, true, -1, 0, -1, SDM660_MASTER_GNOC_BIMC);
|
||||
DEFINE_QNODE(slv_gnoc_snoc, SDM660_SLAVE_GNOC_SNOC, 8, -1, 211, true, -1, 0, -1, SDM660_MASTER_GNOC_SNOC);
|
||||
DEFINE_QNODE(slv_camera_cfg, SDM660_SLAVE_CAMERA_CFG, 4, -1, 3, true, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_camera_throttle_cfg, SDM660_SLAVE_CAMERA_THROTTLE_CFG, 4, -1, 154, true, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_misc_cfg, SDM660_SLAVE_MISC_CFG, 4, -1, 8, true, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_venus_throttle_cfg, SDM660_SLAVE_VENUS_THROTTLE_CFG, 4, -1, 178, true, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_venus_cfg, SDM660_SLAVE_VENUS_CFG, 4, -1, 10, true, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_mmss_clk_xpu_cfg, SDM660_SLAVE_MMSS_CLK_XPU_CFG, 4, -1, 13, true, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_mmss_clk_cfg, SDM660_SLAVE_MMSS_CLK_CFG, 4, -1, 12, true, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_mnoc_mpu_cfg, SDM660_SLAVE_MNOC_MPU_CFG, 4, -1, 14, true, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_display_cfg, SDM660_SLAVE_DISPLAY_CFG, 4, -1, 4, true, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_csi_phy_cfg, SDM660_SLAVE_CSI_PHY_CFG, 4, -1, 224, true, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_display_throttle_cfg, SDM660_SLAVE_DISPLAY_THROTTLE_CFG, 4, -1, 156, true, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_smmu_cfg, SDM660_SLAVE_SMMU_CFG, 8, -1, 205, true, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_mnoc_bimc, SDM660_SLAVE_MNOC_BIMC, 16, -1, 16, true, -1, 0, -1, SDM660_MASTER_MNOC_BIMC);
|
||||
DEFINE_QNODE(slv_srvc_mnoc, SDM660_SLAVE_SRVC_MNOC, 8, -1, 17, true, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_hmss, SDM660_SLAVE_HMSS, 8, -1, 20, true, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_lpass, SDM660_SLAVE_LPASS, 4, -1, 21, true, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_wlan, SDM660_SLAVE_WLAN, 4, -1, 206, false, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_cdsp, SDM660_SLAVE_CDSP, 4, -1, 221, true, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_ipa, SDM660_SLAVE_IPA, 4, -1, 183, true, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_snoc_bimc, SDM660_SLAVE_SNOC_BIMC, 16, -1, 24, false, -1, 0, -1, SDM660_MASTER_SNOC_BIMC);
|
||||
DEFINE_QNODE(slv_snoc_cnoc, SDM660_SLAVE_SNOC_CNOC, 8, -1, 25, false, -1, 0, -1, SDM660_MASTER_SNOC_CNOC);
|
||||
DEFINE_QNODE(slv_imem, SDM660_SLAVE_IMEM, 8, -1, 26, false, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_pimem, SDM660_SLAVE_PIMEM, 8, -1, 166, false, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_qdss_stm, SDM660_SLAVE_QDSS_STM, 4, -1, 30, false, -1, 0, -1, 0);
|
||||
DEFINE_QNODE(slv_srvc_snoc, SDM660_SLAVE_SRVC_SNOC, 16, -1, 29, false, -1, 0, -1, 0);
|
||||
|
||||
static struct qcom_icc_node *sdm660_a2noc_nodes[] = {
|
||||
[MASTER_IPA] = &mas_ipa,
|
||||
[MASTER_CNOC_A2NOC] = &mas_cnoc_a2noc,
|
||||
[MASTER_SDCC_1] = &mas_sdcc_1,
|
||||
[MASTER_SDCC_2] = &mas_sdcc_2,
|
||||
[MASTER_BLSP_1] = &mas_blsp_1,
|
||||
[MASTER_BLSP_2] = &mas_blsp_2,
|
||||
[MASTER_UFS] = &mas_ufs,
|
||||
[MASTER_USB_HS] = &mas_usb_hs,
|
||||
[MASTER_USB3] = &mas_usb3,
|
||||
[MASTER_CRYPTO_C0] = &mas_crypto,
|
||||
[SLAVE_A2NOC_SNOC] = &slv_a2noc_snoc,
|
||||
};
|
||||
|
||||
static const struct regmap_config sdm660_a2noc_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0x20000,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static struct qcom_icc_desc sdm660_a2noc = {
|
||||
.nodes = sdm660_a2noc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(sdm660_a2noc_nodes),
|
||||
.regmap_cfg = &sdm660_a2noc_regmap_config,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node *sdm660_bimc_nodes[] = {
|
||||
[MASTER_GNOC_BIMC] = &mas_gnoc_bimc,
|
||||
[MASTER_OXILI] = &mas_oxili,
|
||||
[MASTER_MNOC_BIMC] = &mas_mnoc_bimc,
|
||||
[MASTER_SNOC_BIMC] = &mas_snoc_bimc,
|
||||
[MASTER_PIMEM] = &mas_pimem,
|
||||
[SLAVE_EBI] = &slv_ebi,
|
||||
[SLAVE_HMSS_L3] = &slv_hmss_l3,
|
||||
[SLAVE_BIMC_SNOC] = &slv_bimc_snoc,
|
||||
};
|
||||
|
||||
static const struct regmap_config sdm660_bimc_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0x80000,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static struct qcom_icc_desc sdm660_bimc = {
|
||||
.nodes = sdm660_bimc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(sdm660_bimc_nodes),
|
||||
.regmap_cfg = &sdm660_bimc_regmap_config,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node *sdm660_cnoc_nodes[] = {
|
||||
[MASTER_SNOC_CNOC] = &mas_snoc_cnoc,
|
||||
[MASTER_QDSS_DAP] = &mas_qdss_dap,
|
||||
[SLAVE_CNOC_A2NOC] = &slv_cnoc_a2noc,
|
||||
[SLAVE_MPM] = &slv_mpm,
|
||||
[SLAVE_PMIC_ARB] = &slv_pmic_arb,
|
||||
[SLAVE_TLMM_NORTH] = &slv_tlmm_north,
|
||||
[SLAVE_TCSR] = &slv_tcsr,
|
||||
[SLAVE_PIMEM_CFG] = &slv_pimem_cfg,
|
||||
[SLAVE_IMEM_CFG] = &slv_imem_cfg,
|
||||
[SLAVE_MESSAGE_RAM] = &slv_message_ram,
|
||||
[SLAVE_GLM] = &slv_glm,
|
||||
[SLAVE_BIMC_CFG] = &slv_bimc_cfg,
|
||||
[SLAVE_PRNG] = &slv_prng,
|
||||
[SLAVE_SPDM] = &slv_spdm,
|
||||
[SLAVE_QDSS_CFG] = &slv_qdss_cfg,
|
||||
[SLAVE_CNOC_MNOC_CFG] = &slv_cnoc_mnoc_cfg,
|
||||
[SLAVE_SNOC_CFG] = &slv_snoc_cfg,
|
||||
[SLAVE_QM_CFG] = &slv_qm_cfg,
|
||||
[SLAVE_CLK_CTL] = &slv_clk_ctl,
|
||||
[SLAVE_MSS_CFG] = &slv_mss_cfg,
|
||||
[SLAVE_TLMM_SOUTH] = &slv_tlmm_south,
|
||||
[SLAVE_UFS_CFG] = &slv_ufs_cfg,
|
||||
[SLAVE_A2NOC_CFG] = &slv_a2noc_cfg,
|
||||
[SLAVE_A2NOC_SMMU_CFG] = &slv_a2noc_smmu_cfg,
|
||||
[SLAVE_GPUSS_CFG] = &slv_gpuss_cfg,
|
||||
[SLAVE_AHB2PHY] = &slv_ahb2phy,
|
||||
[SLAVE_BLSP_1] = &slv_blsp_1,
|
||||
[SLAVE_SDCC_1] = &slv_sdcc_1,
|
||||
[SLAVE_SDCC_2] = &slv_sdcc_2,
|
||||
[SLAVE_TLMM_CENTER] = &slv_tlmm_center,
|
||||
[SLAVE_BLSP_2] = &slv_blsp_2,
|
||||
[SLAVE_PDM] = &slv_pdm,
|
||||
[SLAVE_CNOC_MNOC_MMSS_CFG] = &slv_cnoc_mnoc_mmss_cfg,
|
||||
[SLAVE_USB_HS] = &slv_usb_hs,
|
||||
[SLAVE_USB3_0] = &slv_usb3_0,
|
||||
[SLAVE_SRVC_CNOC] = &slv_srvc_cnoc,
|
||||
};
|
||||
|
||||
static const struct regmap_config sdm660_cnoc_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0x10000,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static struct qcom_icc_desc sdm660_cnoc = {
|
||||
.nodes = sdm660_cnoc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(sdm660_cnoc_nodes),
|
||||
.regmap_cfg = &sdm660_cnoc_regmap_config,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node *sdm660_gnoc_nodes[] = {
|
||||
[MASTER_APSS_PROC] = &mas_apss_proc,
|
||||
[SLAVE_GNOC_BIMC] = &slv_gnoc_bimc,
|
||||
[SLAVE_GNOC_SNOC] = &slv_gnoc_snoc,
|
||||
};
|
||||
|
||||
static const struct regmap_config sdm660_gnoc_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0xe000,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static struct qcom_icc_desc sdm660_gnoc = {
|
||||
.nodes = sdm660_gnoc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(sdm660_gnoc_nodes),
|
||||
.regmap_cfg = &sdm660_gnoc_regmap_config,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node *sdm660_mnoc_nodes[] = {
|
||||
[MASTER_CPP] = &mas_cpp,
|
||||
[MASTER_JPEG] = &mas_jpeg,
|
||||
[MASTER_MDP_P0] = &mas_mdp_p0,
|
||||
[MASTER_MDP_P1] = &mas_mdp_p1,
|
||||
[MASTER_VENUS] = &mas_venus,
|
||||
[MASTER_VFE] = &mas_vfe,
|
||||
[MASTER_CNOC_MNOC_MMSS_CFG] = &mas_cnoc_mnoc_mmss_cfg,
|
||||
[MASTER_CNOC_MNOC_CFG] = &mas_cnoc_mnoc_cfg,
|
||||
[SLAVE_CAMERA_CFG] = &slv_camera_cfg,
|
||||
[SLAVE_CAMERA_THROTTLE_CFG] = &slv_camera_throttle_cfg,
|
||||
[SLAVE_MISC_CFG] = &slv_misc_cfg,
|
||||
[SLAVE_VENUS_THROTTLE_CFG] = &slv_venus_throttle_cfg,
|
||||
[SLAVE_VENUS_CFG] = &slv_venus_cfg,
|
||||
[SLAVE_MMSS_CLK_XPU_CFG] = &slv_mmss_clk_xpu_cfg,
|
||||
[SLAVE_MMSS_CLK_CFG] = &slv_mmss_clk_cfg,
|
||||
[SLAVE_MNOC_MPU_CFG] = &slv_mnoc_mpu_cfg,
|
||||
[SLAVE_DISPLAY_CFG] = &slv_display_cfg,
|
||||
[SLAVE_CSI_PHY_CFG] = &slv_csi_phy_cfg,
|
||||
[SLAVE_DISPLAY_THROTTLE_CFG] = &slv_display_throttle_cfg,
|
||||
[SLAVE_SMMU_CFG] = &slv_smmu_cfg,
|
||||
[SLAVE_SRVC_MNOC] = &slv_srvc_mnoc,
|
||||
[SLAVE_MNOC_BIMC] = &slv_mnoc_bimc,
|
||||
};
|
||||
|
||||
static const struct regmap_config sdm660_mnoc_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0x10000,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static struct qcom_icc_desc sdm660_mnoc = {
|
||||
.nodes = sdm660_mnoc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(sdm660_mnoc_nodes),
|
||||
.regmap_cfg = &sdm660_mnoc_regmap_config,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node *sdm660_snoc_nodes[] = {
|
||||
[MASTER_QDSS_ETR] = &mas_qdss_etr,
|
||||
[MASTER_QDSS_BAM] = &mas_qdss_bam,
|
||||
[MASTER_SNOC_CFG] = &mas_snoc_cfg,
|
||||
[MASTER_BIMC_SNOC] = &mas_bimc_snoc,
|
||||
[MASTER_A2NOC_SNOC] = &mas_a2noc_snoc,
|
||||
[MASTER_GNOC_SNOC] = &mas_gnoc_snoc,
|
||||
[SLAVE_HMSS] = &slv_hmss,
|
||||
[SLAVE_LPASS] = &slv_lpass,
|
||||
[SLAVE_WLAN] = &slv_wlan,
|
||||
[SLAVE_CDSP] = &slv_cdsp,
|
||||
[SLAVE_IPA] = &slv_ipa,
|
||||
[SLAVE_SNOC_BIMC] = &slv_snoc_bimc,
|
||||
[SLAVE_SNOC_CNOC] = &slv_snoc_cnoc,
|
||||
[SLAVE_IMEM] = &slv_imem,
|
||||
[SLAVE_PIMEM] = &slv_pimem,
|
||||
[SLAVE_QDSS_STM] = &slv_qdss_stm,
|
||||
[SLAVE_SRVC_SNOC] = &slv_srvc_snoc,
|
||||
};
|
||||
|
||||
static const struct regmap_config sdm660_snoc_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0x20000,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static struct qcom_icc_desc sdm660_snoc = {
|
||||
.nodes = sdm660_snoc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(sdm660_snoc_nodes),
|
||||
.regmap_cfg = &sdm660_snoc_regmap_config,
|
||||
};
|
||||
|
||||
static int qcom_icc_bimc_set_qos_health(struct regmap *rmap,
|
||||
struct qcom_icc_qos *qos,
|
||||
int regnum)
|
||||
{
|
||||
u32 val;
|
||||
u32 mask;
|
||||
|
||||
val = qos->prio_level;
|
||||
mask = M_BKE_HEALTH_CFG_PRIOLVL_MASK;
|
||||
|
||||
val |= qos->areq_prio << M_BKE_HEALTH_CFG_AREQPRIO_SHIFT;
|
||||
mask |= M_BKE_HEALTH_CFG_AREQPRIO_MASK;
|
||||
|
||||
/* LIMITCMDS is not present on M_BKE_HEALTH_3 */
|
||||
if (regnum != 3) {
|
||||
val |= qos->limit_commands << M_BKE_HEALTH_CFG_LIMITCMDS_SHIFT;
|
||||
mask |= M_BKE_HEALTH_CFG_LIMITCMDS_MASK;
|
||||
}
|
||||
|
||||
return regmap_update_bits(rmap,
|
||||
M_BKE_HEALTH_CFG_ADDR(regnum, qos->qos_port),
|
||||
mask, val);
|
||||
}
|
||||
|
||||
static int qcom_icc_set_bimc_qos(struct icc_node *src, u64 max_bw,
|
||||
bool bypass_mode)
|
||||
{
|
||||
struct qcom_icc_provider *qp;
|
||||
struct qcom_icc_node *qn;
|
||||
struct icc_provider *provider;
|
||||
u32 mode = NOC_QOS_MODE_BYPASS;
|
||||
u32 val = 0;
|
||||
int i, rc = 0;
|
||||
|
||||
qn = src->data;
|
||||
provider = src->provider;
|
||||
qp = to_qcom_provider(provider);
|
||||
|
||||
if (qn->qos.qos_mode != -1)
|
||||
mode = qn->qos.qos_mode;
|
||||
|
||||
/* QoS Priority: The QoS Health parameters are getting considered
|
||||
* only if we are NOT in Bypass Mode.
|
||||
*/
|
||||
if (mode != NOC_QOS_MODE_BYPASS) {
|
||||
for (i = 3; i >= 0; i--) {
|
||||
rc = qcom_icc_bimc_set_qos_health(qp->regmap,
|
||||
&qn->qos, i);
|
||||
if (rc)
|
||||
return rc;
|
||||
}
|
||||
|
||||
/* Set BKE_EN to 1 when Fixed, Regulator or Limiter Mode */
|
||||
val = 1;
|
||||
}
|
||||
|
||||
return regmap_update_bits(qp->regmap, M_BKE_EN_ADDR(qn->qos.qos_port),
|
||||
M_BKE_EN_EN_BMASK, val);
|
||||
}
|
||||
|
||||
static int qcom_icc_noc_set_qos_priority(struct regmap *rmap,
|
||||
struct qcom_icc_qos *qos)
|
||||
{
|
||||
u32 val;
|
||||
int rc;
|
||||
|
||||
/* Must be updated one at a time, P1 first, P0 last */
|
||||
val = qos->areq_prio << NOC_QOS_PRIORITY_P1_SHIFT;
|
||||
rc = regmap_update_bits(rmap, NOC_QOS_PRIORITYn_ADDR(qos->qos_port),
|
||||
NOC_QOS_PRIORITY_MASK, val);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
val = qos->prio_level << NOC_QOS_PRIORITY_P0_SHIFT;
|
||||
return regmap_update_bits(rmap, NOC_QOS_PRIORITYn_ADDR(qos->qos_port),
|
||||
NOC_QOS_PRIORITY_MASK, val);
|
||||
}
|
||||
|
||||
static int qcom_icc_set_noc_qos(struct icc_node *src, u64 max_bw)
|
||||
{
|
||||
struct qcom_icc_provider *qp;
|
||||
struct qcom_icc_node *qn;
|
||||
struct icc_provider *provider;
|
||||
u32 mode = NOC_QOS_MODE_BYPASS;
|
||||
int rc = 0;
|
||||
|
||||
qn = src->data;
|
||||
provider = src->provider;
|
||||
qp = to_qcom_provider(provider);
|
||||
|
||||
if (qn->qos.qos_port < 0) {
|
||||
dev_dbg(src->provider->dev,
|
||||
"NoC QoS: Skipping %s: vote aggregated on parent.\n",
|
||||
qn->name);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (qn->qos.qos_mode != -1)
|
||||
mode = qn->qos.qos_mode;
|
||||
|
||||
if (mode == NOC_QOS_MODE_FIXED) {
|
||||
dev_dbg(src->provider->dev, "NoC QoS: %s: Set Fixed mode\n",
|
||||
qn->name);
|
||||
rc = qcom_icc_noc_set_qos_priority(qp->regmap, &qn->qos);
|
||||
if (rc)
|
||||
return rc;
|
||||
} else if (mode == NOC_QOS_MODE_BYPASS) {
|
||||
dev_dbg(src->provider->dev, "NoC QoS: %s: Set Bypass mode\n",
|
||||
qn->name);
|
||||
}
|
||||
|
||||
return regmap_update_bits(qp->regmap,
|
||||
NOC_QOS_MODEn_ADDR(qn->qos.qos_port),
|
||||
NOC_QOS_MODEn_MASK, mode);
|
||||
}
|
||||
|
||||
static int qcom_icc_qos_set(struct icc_node *node, u64 sum_bw)
|
||||
{
|
||||
struct qcom_icc_provider *qp = to_qcom_provider(node->provider);
|
||||
struct qcom_icc_node *qn = node->data;
|
||||
|
||||
dev_dbg(node->provider->dev, "Setting QoS for %s\n", qn->name);
|
||||
|
||||
if (qp->is_bimc_node)
|
||||
return qcom_icc_set_bimc_qos(node, sum_bw,
|
||||
(qn->qos.qos_mode == NOC_QOS_MODE_BYPASS));
|
||||
|
||||
return qcom_icc_set_noc_qos(node, sum_bw);
|
||||
}
|
||||
|
||||
static int qcom_icc_rpm_set(int mas_rpm_id, int slv_rpm_id, u64 sum_bw)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
if (mas_rpm_id != -1) {
|
||||
ret = qcom_icc_rpm_smd_send(QCOM_SMD_RPM_ACTIVE_STATE,
|
||||
RPM_BUS_MASTER_REQ,
|
||||
mas_rpm_id,
|
||||
sum_bw);
|
||||
if (ret) {
|
||||
pr_err("qcom_icc_rpm_smd_send mas %d error %d\n",
|
||||
mas_rpm_id, ret);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
if (slv_rpm_id != -1) {
|
||||
ret = qcom_icc_rpm_smd_send(QCOM_SMD_RPM_ACTIVE_STATE,
|
||||
RPM_BUS_SLAVE_REQ,
|
||||
slv_rpm_id,
|
||||
sum_bw);
|
||||
if (ret) {
|
||||
pr_err("qcom_icc_rpm_smd_send slv %d error %d\n",
|
||||
slv_rpm_id, ret);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
|
||||
{
|
||||
struct qcom_icc_provider *qp;
|
||||
struct qcom_icc_node *qn;
|
||||
struct icc_provider *provider;
|
||||
struct icc_node *n;
|
||||
u64 sum_bw;
|
||||
u64 max_peak_bw;
|
||||
u64 rate;
|
||||
u32 agg_avg = 0;
|
||||
u32 agg_peak = 0;
|
||||
int ret, i;
|
||||
|
||||
qn = src->data;
|
||||
provider = src->provider;
|
||||
qp = to_qcom_provider(provider);
|
||||
|
||||
list_for_each_entry(n, &provider->nodes, node_list)
|
||||
provider->aggregate(n, 0, n->avg_bw, n->peak_bw,
|
||||
&agg_avg, &agg_peak);
|
||||
|
||||
sum_bw = icc_units_to_bps(agg_avg);
|
||||
max_peak_bw = icc_units_to_bps(agg_peak);
|
||||
|
||||
if (!qn->qos.ap_owned) {
|
||||
/* send bandwidth request message to the RPM processor */
|
||||
ret = qcom_icc_rpm_set(qn->mas_rpm_id, qn->slv_rpm_id, sum_bw);
|
||||
if (ret)
|
||||
return ret;
|
||||
} else if (qn->qos.qos_mode != -1) {
|
||||
/* set bandwidth directly from the AP */
|
||||
ret = qcom_icc_qos_set(src, sum_bw);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
rate = max(sum_bw, max_peak_bw);
|
||||
|
||||
do_div(rate, qn->buswidth);
|
||||
|
||||
if (qn->rate == rate)
|
||||
return 0;
|
||||
|
||||
for (i = 0; i < qp->num_clks; i++) {
|
||||
ret = clk_set_rate(qp->bus_clks[i].clk, rate);
|
||||
if (ret) {
|
||||
pr_err("%s clk_set_rate error: %d\n",
|
||||
qp->bus_clks[i].id, ret);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
qn->rate = rate;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int qnoc_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
const struct qcom_icc_desc *desc;
|
||||
struct icc_onecell_data *data;
|
||||
struct icc_provider *provider;
|
||||
struct qcom_icc_node **qnodes;
|
||||
struct qcom_icc_provider *qp;
|
||||
struct icc_node *node;
|
||||
struct resource *res;
|
||||
size_t num_nodes, i;
|
||||
int ret;
|
||||
|
||||
/* wait for the RPM proxy */
|
||||
if (!qcom_icc_rpm_smd_available())
|
||||
return -EPROBE_DEFER;
|
||||
|
||||
desc = of_device_get_match_data(dev);
|
||||
if (!desc)
|
||||
return -EINVAL;
|
||||
|
||||
qnodes = desc->nodes;
|
||||
num_nodes = desc->num_nodes;
|
||||
|
||||
qp = devm_kzalloc(dev, sizeof(*qp), GFP_KERNEL);
|
||||
if (!qp)
|
||||
return -ENOMEM;
|
||||
|
||||
data = devm_kzalloc(dev, struct_size(data, nodes, num_nodes),
|
||||
GFP_KERNEL);
|
||||
if (!data)
|
||||
return -ENOMEM;
|
||||
|
||||
if (of_device_is_compatible(dev->of_node, "qcom,sdm660-mnoc")) {
|
||||
qp->bus_clks = devm_kmemdup(dev, bus_mm_clocks,
|
||||
sizeof(bus_mm_clocks), GFP_KERNEL);
|
||||
qp->num_clks = ARRAY_SIZE(bus_mm_clocks);
|
||||
} else {
|
||||
if (of_device_is_compatible(dev->of_node, "qcom,sdm660-bimc"))
|
||||
qp->is_bimc_node = true;
|
||||
|
||||
qp->bus_clks = devm_kmemdup(dev, bus_clocks, sizeof(bus_clocks),
|
||||
GFP_KERNEL);
|
||||
qp->num_clks = ARRAY_SIZE(bus_clocks);
|
||||
}
|
||||
if (!qp->bus_clks)
|
||||
return -ENOMEM;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!res)
|
||||
return -ENODEV;
|
||||
|
||||
qp->mmio = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(qp->mmio)) {
|
||||
dev_err(dev, "Cannot ioremap interconnect bus resource\n");
|
||||
return PTR_ERR(qp->mmio);
|
||||
}
|
||||
|
||||
qp->regmap = devm_regmap_init_mmio(dev, qp->mmio, desc->regmap_cfg);
|
||||
if (IS_ERR(qp->regmap)) {
|
||||
dev_err(dev, "Cannot regmap interconnect bus resource\n");
|
||||
return PTR_ERR(qp->regmap);
|
||||
}
|
||||
|
||||
ret = devm_clk_bulk_get(dev, qp->num_clks, qp->bus_clks);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = clk_bulk_prepare_enable(qp->num_clks, qp->bus_clks);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
provider = &qp->provider;
|
||||
INIT_LIST_HEAD(&provider->nodes);
|
||||
provider->dev = dev;
|
||||
provider->set = qcom_icc_set;
|
||||
provider->aggregate = icc_std_aggregate;
|
||||
provider->xlate = of_icc_xlate_onecell;
|
||||
provider->data = data;
|
||||
|
||||
ret = icc_provider_add(provider);
|
||||
if (ret) {
|
||||
dev_err(dev, "error adding interconnect provider: %d\n", ret);
|
||||
clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks);
|
||||
return ret;
|
||||
}
|
||||
|
||||
for (i = 0; i < num_nodes; i++) {
|
||||
size_t j;
|
||||
|
||||
node = icc_node_create(qnodes[i]->id);
|
||||
if (IS_ERR(node)) {
|
||||
ret = PTR_ERR(node);
|
||||
goto err;
|
||||
}
|
||||
|
||||
node->name = qnodes[i]->name;
|
||||
node->data = qnodes[i];
|
||||
icc_node_add(node, provider);
|
||||
|
||||
for (j = 0; j < qnodes[i]->num_links; j++)
|
||||
icc_link_create(node, qnodes[i]->links[j]);
|
||||
|
||||
data->nodes[i] = node;
|
||||
}
|
||||
data->num_nodes = num_nodes;
|
||||
platform_set_drvdata(pdev, qp);
|
||||
|
||||
return 0;
|
||||
err:
|
||||
icc_nodes_remove(provider);
|
||||
clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks);
|
||||
icc_provider_del(provider);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int qnoc_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct qcom_icc_provider *qp = platform_get_drvdata(pdev);
|
||||
|
||||
icc_nodes_remove(&qp->provider);
|
||||
clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks);
|
||||
return icc_provider_del(&qp->provider);
|
||||
}
|
||||
|
||||
static const struct of_device_id sdm660_noc_of_match[] = {
|
||||
{ .compatible = "qcom,sdm660-a2noc", .data = &sdm660_a2noc },
|
||||
{ .compatible = "qcom,sdm660-bimc", .data = &sdm660_bimc },
|
||||
{ .compatible = "qcom,sdm660-cnoc", .data = &sdm660_cnoc },
|
||||
{ .compatible = "qcom,sdm660-gnoc", .data = &sdm660_gnoc },
|
||||
{ .compatible = "qcom,sdm660-mnoc", .data = &sdm660_mnoc },
|
||||
{ .compatible = "qcom,sdm660-snoc", .data = &sdm660_snoc },
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, sdm660_noc_of_match);
|
||||
|
||||
static struct platform_driver sdm660_noc_driver = {
|
||||
.probe = qnoc_probe,
|
||||
.remove = qnoc_remove,
|
||||
.driver = {
|
||||
.name = "qnoc-sdm660",
|
||||
.of_match_table = sdm660_noc_of_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(sdm660_noc_driver);
|
||||
MODULE_DESCRIPTION("Qualcomm sdm660 NoC driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
633
drivers/interconnect/qcom/sm8350.c
Normal file
633
drivers/interconnect/qcom/sm8350.c
Normal file
@ -0,0 +1,633 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2021, Linaro Limited
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/interconnect-provider.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <dt-bindings/interconnect/qcom,sm8350.h>
|
||||
|
||||
#include "bcm-voter.h"
|
||||
#include "icc-rpmh.h"
|
||||
#include "sm8350.h"
|
||||
|
||||
DEFINE_QNODE(qhm_qspi, SM8350_MASTER_QSPI_0, 1, 4, SM8350_SLAVE_A1NOC_SNOC);
|
||||
DEFINE_QNODE(qhm_qup0, SM8350_MASTER_QUP_0, 1, 4, SM8350_SLAVE_A2NOC_SNOC);
|
||||
DEFINE_QNODE(qhm_qup1, SM8350_MASTER_QUP_1, 1, 4, SM8350_SLAVE_A1NOC_SNOC);
|
||||
DEFINE_QNODE(qhm_qup2, SM8350_MASTER_QUP_2, 1, 4, SM8350_SLAVE_A2NOC_SNOC);
|
||||
DEFINE_QNODE(qnm_a1noc_cfg, SM8350_MASTER_A1NOC_CFG, 1, 4, SM8350_SLAVE_SERVICE_A1NOC);
|
||||
DEFINE_QNODE(xm_sdc4, SM8350_MASTER_SDCC_4, 1, 8, SM8350_SLAVE_A1NOC_SNOC);
|
||||
DEFINE_QNODE(xm_ufs_mem, SM8350_MASTER_UFS_MEM, 1, 8, SM8350_SLAVE_A1NOC_SNOC);
|
||||
DEFINE_QNODE(xm_usb3_0, SM8350_MASTER_USB3_0, 1, 8, SM8350_SLAVE_A1NOC_SNOC);
|
||||
DEFINE_QNODE(xm_usb3_1, SM8350_MASTER_USB3_1, 1, 8, SM8350_SLAVE_A1NOC_SNOC);
|
||||
DEFINE_QNODE(qhm_qdss_bam, SM8350_MASTER_QDSS_BAM, 1, 4, SM8350_SLAVE_A2NOC_SNOC);
|
||||
DEFINE_QNODE(qnm_a2noc_cfg, SM8350_MASTER_A2NOC_CFG, 1, 4, SM8350_SLAVE_SERVICE_A2NOC);
|
||||
DEFINE_QNODE(qxm_crypto, SM8350_MASTER_CRYPTO, 1, 8, SM8350_SLAVE_A2NOC_SNOC);
|
||||
DEFINE_QNODE(qxm_ipa, SM8350_MASTER_IPA, 1, 8, SM8350_SLAVE_A2NOC_SNOC);
|
||||
DEFINE_QNODE(xm_pcie3_0, SM8350_MASTER_PCIE_0, 1, 8, SM8350_SLAVE_ANOC_PCIE_GEM_NOC);
|
||||
DEFINE_QNODE(xm_pcie3_1, SM8350_MASTER_PCIE_1, 1, 8, SM8350_SLAVE_ANOC_PCIE_GEM_NOC);
|
||||
DEFINE_QNODE(xm_qdss_etr, SM8350_MASTER_QDSS_ETR, 1, 8, SM8350_SLAVE_A2NOC_SNOC);
|
||||
DEFINE_QNODE(xm_sdc2, SM8350_MASTER_SDCC_2, 1, 8, SM8350_SLAVE_A2NOC_SNOC);
|
||||
DEFINE_QNODE(xm_ufs_card, SM8350_MASTER_UFS_CARD, 1, 8, SM8350_SLAVE_A2NOC_SNOC);
|
||||
DEFINE_QNODE(qnm_gemnoc_cnoc, SM8350_MASTER_GEM_NOC_CNOC, 1, 16, SM8350_SLAVE_AHB2PHY_SOUTH, SM8350_SLAVE_AHB2PHY_NORTH, SM8350_SLAVE_AOSS, SM8350_SLAVE_APPSS, SM8350_SLAVE_CAMERA_CFG, SM8350_SLAVE_CLK_CTL, SM8350_SLAVE_CDSP_CFG, SM8350_SLAVE_RBCPR_CX_CFG, SM8350_SLAVE_RBCPR_MMCX_CFG, SM8350_SLAVE_RBCPR_MX_CFG, SM8350_SLAVE_CRYPTO_0_CFG, SM8350_SLAVE_CX_RDPM, SM8350_SLAVE_DCC_CFG, SM8350_SLAVE_DISPLAY_CFG, SM8350_SLAVE_GFX3D_CFG, SM8350_SLAVE_HWKM, SM8350_SLAVE_IMEM_CFG, SM8350_SLAVE_IPA_CFG, SM8350_SLAVE_IPC_ROUTER_CFG, SM8350_SLAVE_LPASS, SM8350_SLAVE_CNOC_MSS, SM8350_SLAVE_MX_RDPM, SM8350_SLAVE_PCIE_0_CFG, SM8350_SLAVE_PCIE_1_CFG, SM8350_SLAVE_PDM, SM8350_SLAVE_PIMEM_CFG, SM8350_SLAVE_PKA_WRAPPER_CFG, SM8350_SLAVE_PMU_WRAPPER_CFG, SM8350_SLAVE_QDSS_CFG, SM8350_SLAVE_QSPI_0, SM8350_SLAVE_QUP_0, SM8350_SLAVE_QUP_1, SM8350_SLAVE_QUP_2, SM8350_SLAVE_SDCC_2, SM8350_SLAVE_SDCC_4, SM8350_SLAVE_SECURITY, SM8350_SLAVE_SPSS_CFG, SM8350_SLAVE_TCSR, SM8350_SLAVE_TLMM, SM8350_SLAVE_UFS_CARD_CFG, SM8350_SLAVE_UFS_MEM_CFG, SM8350_SLAVE_USB3_0, SM8350_SLAVE_USB3_1, SM8350_SLAVE_VENUS_CFG, SM8350_SLAVE_VSENSE_CTRL_CFG, SM8350_SLAVE_A1NOC_CFG, SM8350_SLAVE_A2NOC_CFG, SM8350_SLAVE_DDRSS_CFG, SM8350_SLAVE_CNOC_MNOC_CFG, SM8350_SLAVE_SNOC_CFG, SM8350_SLAVE_BOOT_IMEM, SM8350_SLAVE_IMEM, SM8350_SLAVE_PIMEM, SM8350_SLAVE_SERVICE_CNOC, SM8350_SLAVE_QDSS_STM, SM8350_SLAVE_TCU);
|
||||
DEFINE_QNODE(qnm_gemnoc_pcie, SM8350_MASTER_GEM_NOC_PCIE_SNOC, 1, 8, SM8350_SLAVE_PCIE_0, SM8350_SLAVE_PCIE_1);
|
||||
DEFINE_QNODE(xm_qdss_dap, SM8350_MASTER_QDSS_DAP, 1, 8, SM8350_SLAVE_AHB2PHY_SOUTH, SM8350_SLAVE_AHB2PHY_NORTH, SM8350_SLAVE_AOSS, SM8350_SLAVE_APPSS, SM8350_SLAVE_CAMERA_CFG, SM8350_SLAVE_CLK_CTL, SM8350_SLAVE_CDSP_CFG, SM8350_SLAVE_RBCPR_CX_CFG, SM8350_SLAVE_RBCPR_MMCX_CFG, SM8350_SLAVE_RBCPR_MX_CFG, SM8350_SLAVE_CRYPTO_0_CFG, SM8350_SLAVE_CX_RDPM, SM8350_SLAVE_DCC_CFG, SM8350_SLAVE_DISPLAY_CFG, SM8350_SLAVE_GFX3D_CFG, SM8350_SLAVE_HWKM, SM8350_SLAVE_IMEM_CFG, SM8350_SLAVE_IPA_CFG, SM8350_SLAVE_IPC_ROUTER_CFG, SM8350_SLAVE_LPASS, SM8350_SLAVE_CNOC_MSS, SM8350_SLAVE_MX_RDPM, SM8350_SLAVE_PCIE_0_CFG, SM8350_SLAVE_PCIE_1_CFG, SM8350_SLAVE_PDM, SM8350_SLAVE_PIMEM_CFG, SM8350_SLAVE_PKA_WRAPPER_CFG, SM8350_SLAVE_PMU_WRAPPER_CFG, SM8350_SLAVE_QDSS_CFG, SM8350_SLAVE_QSPI_0, SM8350_SLAVE_QUP_0, SM8350_SLAVE_QUP_1, SM8350_SLAVE_QUP_2, SM8350_SLAVE_SDCC_2, SM8350_SLAVE_SDCC_4, SM8350_SLAVE_SECURITY, SM8350_SLAVE_SPSS_CFG, SM8350_SLAVE_TCSR, SM8350_SLAVE_TLMM, SM8350_SLAVE_UFS_CARD_CFG, SM8350_SLAVE_UFS_MEM_CFG, SM8350_SLAVE_USB3_0, SM8350_SLAVE_USB3_1, SM8350_SLAVE_VENUS_CFG, SM8350_SLAVE_VSENSE_CTRL_CFG, SM8350_SLAVE_A1NOC_CFG, SM8350_SLAVE_A2NOC_CFG, SM8350_SLAVE_DDRSS_CFG, SM8350_SLAVE_CNOC_MNOC_CFG, SM8350_SLAVE_SNOC_CFG, SM8350_SLAVE_BOOT_IMEM, SM8350_SLAVE_IMEM, SM8350_SLAVE_PIMEM, SM8350_SLAVE_SERVICE_CNOC, SM8350_SLAVE_QDSS_STM, SM8350_SLAVE_TCU);
|
||||
DEFINE_QNODE(qnm_cnoc_dc_noc, SM8350_MASTER_CNOC_DC_NOC, 1, 4, SM8350_SLAVE_LLCC_CFG, SM8350_SLAVE_GEM_NOC_CFG);
|
||||
DEFINE_QNODE(alm_gpu_tcu, SM8350_MASTER_GPU_TCU, 1, 8, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC);
|
||||
DEFINE_QNODE(alm_sys_tcu, SM8350_MASTER_SYS_TCU, 1, 8, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC);
|
||||
DEFINE_QNODE(chm_apps, SM8350_MASTER_APPSS_PROC, 2, 32, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC, SM8350_SLAVE_MEM_NOC_PCIE_SNOC);
|
||||
DEFINE_QNODE(qnm_cmpnoc, SM8350_MASTER_COMPUTE_NOC, 2, 32, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC);
|
||||
DEFINE_QNODE(qnm_gemnoc_cfg, SM8350_MASTER_GEM_NOC_CFG, 1, 4, SM8350_SLAVE_MSS_PROC_MS_MPU_CFG, SM8350_SLAVE_MCDMA_MS_MPU_CFG, SM8350_SLAVE_SERVICE_GEM_NOC_1, SM8350_SLAVE_SERVICE_GEM_NOC_2, SM8350_SLAVE_SERVICE_GEM_NOC);
|
||||
DEFINE_QNODE(qnm_gpu, SM8350_MASTER_GFX3D, 2, 32, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC);
|
||||
DEFINE_QNODE(qnm_mnoc_hf, SM8350_MASTER_MNOC_HF_MEM_NOC, 2, 32, SM8350_SLAVE_LLCC);
|
||||
DEFINE_QNODE(qnm_mnoc_sf, SM8350_MASTER_MNOC_SF_MEM_NOC, 2, 32, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC);
|
||||
DEFINE_QNODE(qnm_pcie, SM8350_MASTER_ANOC_PCIE_GEM_NOC, 1, 16, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC);
|
||||
DEFINE_QNODE(qnm_snoc_gc, SM8350_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM8350_SLAVE_LLCC);
|
||||
DEFINE_QNODE(qnm_snoc_sf, SM8350_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC, SM8350_SLAVE_MEM_NOC_PCIE_SNOC);
|
||||
DEFINE_QNODE(qhm_config_noc, SM8350_MASTER_CNOC_LPASS_AG_NOC, 1, 4, SM8350_SLAVE_LPASS_CORE_CFG, SM8350_SLAVE_LPASS_LPI_CFG, SM8350_SLAVE_LPASS_MPU_CFG, SM8350_SLAVE_LPASS_TOP_CFG, SM8350_SLAVE_SERVICES_LPASS_AML_NOC, SM8350_SLAVE_SERVICE_LPASS_AG_NOC);
|
||||
DEFINE_QNODE(llcc_mc, SM8350_MASTER_LLCC, 4, 4, SM8350_SLAVE_EBI1);
|
||||
DEFINE_QNODE(qnm_camnoc_hf, SM8350_MASTER_CAMNOC_HF, 2, 32, SM8350_SLAVE_MNOC_HF_MEM_NOC);
|
||||
DEFINE_QNODE(qnm_camnoc_icp, SM8350_MASTER_CAMNOC_ICP, 1, 8, SM8350_SLAVE_MNOC_SF_MEM_NOC);
|
||||
DEFINE_QNODE(qnm_camnoc_sf, SM8350_MASTER_CAMNOC_SF, 2, 32, SM8350_SLAVE_MNOC_SF_MEM_NOC);
|
||||
DEFINE_QNODE(qnm_mnoc_cfg, SM8350_MASTER_CNOC_MNOC_CFG, 1, 4, SM8350_SLAVE_SERVICE_MNOC);
|
||||
DEFINE_QNODE(qnm_video0, SM8350_MASTER_VIDEO_P0, 1, 32, SM8350_SLAVE_MNOC_SF_MEM_NOC);
|
||||
DEFINE_QNODE(qnm_video1, SM8350_MASTER_VIDEO_P1, 1, 32, SM8350_SLAVE_MNOC_SF_MEM_NOC);
|
||||
DEFINE_QNODE(qnm_video_cvp, SM8350_MASTER_VIDEO_PROC, 1, 32, SM8350_SLAVE_MNOC_SF_MEM_NOC);
|
||||
DEFINE_QNODE(qxm_mdp0, SM8350_MASTER_MDP0, 1, 32, SM8350_SLAVE_MNOC_HF_MEM_NOC);
|
||||
DEFINE_QNODE(qxm_mdp1, SM8350_MASTER_MDP1, 1, 32, SM8350_SLAVE_MNOC_HF_MEM_NOC);
|
||||
DEFINE_QNODE(qxm_rot, SM8350_MASTER_ROTATOR, 1, 32, SM8350_SLAVE_MNOC_SF_MEM_NOC);
|
||||
DEFINE_QNODE(qhm_nsp_noc_config, SM8350_MASTER_CDSP_NOC_CFG, 1, 4, SM8350_SLAVE_SERVICE_NSP_NOC);
|
||||
DEFINE_QNODE(qxm_nsp, SM8350_MASTER_CDSP_PROC, 2, 32, SM8350_SLAVE_CDSP_MEM_NOC);
|
||||
DEFINE_QNODE(qnm_aggre1_noc, SM8350_MASTER_A1NOC_SNOC, 1, 16, SM8350_SLAVE_SNOC_GEM_NOC_SF);
|
||||
DEFINE_QNODE(qnm_aggre2_noc, SM8350_MASTER_A2NOC_SNOC, 1, 16, SM8350_SLAVE_SNOC_GEM_NOC_SF);
|
||||
DEFINE_QNODE(qnm_snoc_cfg, SM8350_MASTER_SNOC_CFG, 1, 4, SM8350_SLAVE_SERVICE_SNOC);
|
||||
DEFINE_QNODE(qxm_pimem, SM8350_MASTER_PIMEM, 1, 8, SM8350_SLAVE_SNOC_GEM_NOC_GC);
|
||||
DEFINE_QNODE(xm_gic, SM8350_MASTER_GIC, 1, 8, SM8350_SLAVE_SNOC_GEM_NOC_GC);
|
||||
DEFINE_QNODE(qnm_mnoc_hf_disp, SM8350_MASTER_MNOC_HF_MEM_NOC_DISP, 2, 32, SM8350_SLAVE_LLCC_DISP);
|
||||
DEFINE_QNODE(qnm_mnoc_sf_disp, SM8350_MASTER_MNOC_SF_MEM_NOC_DISP, 2, 32, SM8350_SLAVE_LLCC_DISP);
|
||||
DEFINE_QNODE(llcc_mc_disp, SM8350_MASTER_LLCC_DISP, 4, 4, SM8350_SLAVE_EBI1_DISP);
|
||||
DEFINE_QNODE(qxm_mdp0_disp, SM8350_MASTER_MDP0_DISP, 1, 32, SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP);
|
||||
DEFINE_QNODE(qxm_mdp1_disp, SM8350_MASTER_MDP1_DISP, 1, 32, SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP);
|
||||
DEFINE_QNODE(qxm_rot_disp, SM8350_MASTER_ROTATOR_DISP, 1, 32, SM8350_SLAVE_MNOC_SF_MEM_NOC_DISP);
|
||||
DEFINE_QNODE(qns_a1noc_snoc, SM8350_SLAVE_A1NOC_SNOC, 1, 16, SM8350_MASTER_A1NOC_SNOC);
|
||||
DEFINE_QNODE(srvc_aggre1_noc, SM8350_SLAVE_SERVICE_A1NOC, 1, 4);
|
||||
DEFINE_QNODE(qns_a2noc_snoc, SM8350_SLAVE_A2NOC_SNOC, 1, 16, SM8350_MASTER_A2NOC_SNOC);
|
||||
DEFINE_QNODE(qns_pcie_mem_noc, SM8350_SLAVE_ANOC_PCIE_GEM_NOC, 1, 16, SM8350_MASTER_ANOC_PCIE_GEM_NOC);
|
||||
DEFINE_QNODE(srvc_aggre2_noc, SM8350_SLAVE_SERVICE_A2NOC, 1, 4);
|
||||
DEFINE_QNODE(qhs_ahb2phy0, SM8350_SLAVE_AHB2PHY_SOUTH, 1, 4);
|
||||
DEFINE_QNODE(qhs_ahb2phy1, SM8350_SLAVE_AHB2PHY_NORTH, 1, 4);
|
||||
DEFINE_QNODE(qhs_aoss, SM8350_SLAVE_AOSS, 1, 4);
|
||||
DEFINE_QNODE(qhs_apss, SM8350_SLAVE_APPSS, 1, 8);
|
||||
DEFINE_QNODE(qhs_camera_cfg, SM8350_SLAVE_CAMERA_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_clk_ctl, SM8350_SLAVE_CLK_CTL, 1, 4);
|
||||
DEFINE_QNODE(qhs_compute_cfg, SM8350_SLAVE_CDSP_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_cpr_cx, SM8350_SLAVE_RBCPR_CX_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_cpr_mmcx, SM8350_SLAVE_RBCPR_MMCX_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_cpr_mx, SM8350_SLAVE_RBCPR_MX_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_crypto0_cfg, SM8350_SLAVE_CRYPTO_0_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_cx_rdpm, SM8350_SLAVE_CX_RDPM, 1, 4);
|
||||
DEFINE_QNODE(qhs_dcc_cfg, SM8350_SLAVE_DCC_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_display_cfg, SM8350_SLAVE_DISPLAY_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_gpuss_cfg, SM8350_SLAVE_GFX3D_CFG, 1, 8);
|
||||
DEFINE_QNODE(qhs_hwkm, SM8350_SLAVE_HWKM, 1, 4);
|
||||
DEFINE_QNODE(qhs_imem_cfg, SM8350_SLAVE_IMEM_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_ipa, SM8350_SLAVE_IPA_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_ipc_router, SM8350_SLAVE_IPC_ROUTER_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_lpass_cfg, SM8350_SLAVE_LPASS, 1, 4, SM8350_MASTER_CNOC_LPASS_AG_NOC);
|
||||
DEFINE_QNODE(qhs_mss_cfg, SM8350_SLAVE_CNOC_MSS, 1, 4);
|
||||
DEFINE_QNODE(qhs_mx_rdpm, SM8350_SLAVE_MX_RDPM, 1, 4);
|
||||
DEFINE_QNODE(qhs_pcie0_cfg, SM8350_SLAVE_PCIE_0_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_pcie1_cfg, SM8350_SLAVE_PCIE_1_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_pdm, SM8350_SLAVE_PDM, 1, 4);
|
||||
DEFINE_QNODE(qhs_pimem_cfg, SM8350_SLAVE_PIMEM_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_pka_wrapper_cfg, SM8350_SLAVE_PKA_WRAPPER_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_pmu_wrapper_cfg, SM8350_SLAVE_PMU_WRAPPER_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_qdss_cfg, SM8350_SLAVE_QDSS_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_qspi, SM8350_SLAVE_QSPI_0, 1, 4);
|
||||
DEFINE_QNODE(qhs_qup0, SM8350_SLAVE_QUP_0, 1, 4);
|
||||
DEFINE_QNODE(qhs_qup1, SM8350_SLAVE_QUP_1, 1, 4);
|
||||
DEFINE_QNODE(qhs_qup2, SM8350_SLAVE_QUP_2, 1, 4);
|
||||
DEFINE_QNODE(qhs_sdc2, SM8350_SLAVE_SDCC_2, 1, 4);
|
||||
DEFINE_QNODE(qhs_sdc4, SM8350_SLAVE_SDCC_4, 1, 4);
|
||||
DEFINE_QNODE(qhs_security, SM8350_SLAVE_SECURITY, 1, 4);
|
||||
DEFINE_QNODE(qhs_spss_cfg, SM8350_SLAVE_SPSS_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_tcsr, SM8350_SLAVE_TCSR, 1, 4);
|
||||
DEFINE_QNODE(qhs_tlmm, SM8350_SLAVE_TLMM, 1, 4);
|
||||
DEFINE_QNODE(qhs_ufs_card_cfg, SM8350_SLAVE_UFS_CARD_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_ufs_mem_cfg, SM8350_SLAVE_UFS_MEM_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_usb3_0, SM8350_SLAVE_USB3_0, 1, 4);
|
||||
DEFINE_QNODE(qhs_usb3_1, SM8350_SLAVE_USB3_1, 1, 4);
|
||||
DEFINE_QNODE(qhs_venus_cfg, SM8350_SLAVE_VENUS_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_vsense_ctrl_cfg, SM8350_SLAVE_VSENSE_CTRL_CFG, 1, 4);
|
||||
DEFINE_QNODE(qns_a1_noc_cfg, SM8350_SLAVE_A1NOC_CFG, 1, 4);
|
||||
DEFINE_QNODE(qns_a2_noc_cfg, SM8350_SLAVE_A2NOC_CFG, 1, 4);
|
||||
DEFINE_QNODE(qns_ddrss_cfg, SM8350_SLAVE_DDRSS_CFG, 1, 4);
|
||||
DEFINE_QNODE(qns_mnoc_cfg, SM8350_SLAVE_CNOC_MNOC_CFG, 1, 4);
|
||||
DEFINE_QNODE(qns_snoc_cfg, SM8350_SLAVE_SNOC_CFG, 1, 4);
|
||||
DEFINE_QNODE(qxs_boot_imem, SM8350_SLAVE_BOOT_IMEM, 1, 8);
|
||||
DEFINE_QNODE(qxs_imem, SM8350_SLAVE_IMEM, 1, 8);
|
||||
DEFINE_QNODE(qxs_pimem, SM8350_SLAVE_PIMEM, 1, 8);
|
||||
DEFINE_QNODE(srvc_cnoc, SM8350_SLAVE_SERVICE_CNOC, 1, 4);
|
||||
DEFINE_QNODE(xs_pcie_0, SM8350_SLAVE_PCIE_0, 1, 8);
|
||||
DEFINE_QNODE(xs_pcie_1, SM8350_SLAVE_PCIE_1, 1, 8);
|
||||
DEFINE_QNODE(xs_qdss_stm, SM8350_SLAVE_QDSS_STM, 1, 4);
|
||||
DEFINE_QNODE(xs_sys_tcu_cfg, SM8350_SLAVE_TCU, 1, 8);
|
||||
DEFINE_QNODE(qhs_llcc, SM8350_SLAVE_LLCC_CFG, 1, 4);
|
||||
DEFINE_QNODE(qns_gemnoc, SM8350_SLAVE_GEM_NOC_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SM8350_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_modem_ms_mpu_cfg, SM8350_SLAVE_MCDMA_MS_MPU_CFG, 1, 4);
|
||||
DEFINE_QNODE(qns_gem_noc_cnoc, SM8350_SLAVE_GEM_NOC_CNOC, 1, 16, SM8350_MASTER_GEM_NOC_CNOC);
|
||||
DEFINE_QNODE(qns_llcc, SM8350_SLAVE_LLCC, 4, 16, SM8350_MASTER_LLCC);
|
||||
DEFINE_QNODE(qns_pcie, SM8350_SLAVE_MEM_NOC_PCIE_SNOC, 1, 8);
|
||||
DEFINE_QNODE(srvc_even_gemnoc, SM8350_SLAVE_SERVICE_GEM_NOC_1, 1, 4);
|
||||
DEFINE_QNODE(srvc_odd_gemnoc, SM8350_SLAVE_SERVICE_GEM_NOC_2, 1, 4);
|
||||
DEFINE_QNODE(srvc_sys_gemnoc, SM8350_SLAVE_SERVICE_GEM_NOC, 1, 4);
|
||||
DEFINE_QNODE(qhs_lpass_core, SM8350_SLAVE_LPASS_CORE_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_lpass_lpi, SM8350_SLAVE_LPASS_LPI_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_lpass_mpu, SM8350_SLAVE_LPASS_MPU_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_lpass_top, SM8350_SLAVE_LPASS_TOP_CFG, 1, 4);
|
||||
DEFINE_QNODE(srvc_niu_aml_noc, SM8350_SLAVE_SERVICES_LPASS_AML_NOC, 1, 4);
|
||||
DEFINE_QNODE(srvc_niu_lpass_agnoc, SM8350_SLAVE_SERVICE_LPASS_AG_NOC, 1, 4);
|
||||
DEFINE_QNODE(ebi, SM8350_SLAVE_EBI1, 4, 4);
|
||||
DEFINE_QNODE(qns_mem_noc_hf, SM8350_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SM8350_MASTER_MNOC_HF_MEM_NOC);
|
||||
DEFINE_QNODE(qns_mem_noc_sf, SM8350_SLAVE_MNOC_SF_MEM_NOC, 2, 32, SM8350_MASTER_MNOC_SF_MEM_NOC);
|
||||
DEFINE_QNODE(srvc_mnoc, SM8350_SLAVE_SERVICE_MNOC, 1, 4);
|
||||
DEFINE_QNODE(qns_nsp_gemnoc, SM8350_SLAVE_CDSP_MEM_NOC, 2, 32, SM8350_MASTER_COMPUTE_NOC);
|
||||
DEFINE_QNODE(service_nsp_noc, SM8350_SLAVE_SERVICE_NSP_NOC, 1, 4);
|
||||
DEFINE_QNODE(qns_gemnoc_gc, SM8350_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SM8350_MASTER_SNOC_GC_MEM_NOC);
|
||||
DEFINE_QNODE(qns_gemnoc_sf, SM8350_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SM8350_MASTER_SNOC_SF_MEM_NOC);
|
||||
DEFINE_QNODE(srvc_snoc, SM8350_SLAVE_SERVICE_SNOC, 1, 4);
|
||||
DEFINE_QNODE(qns_llcc_disp, SM8350_SLAVE_LLCC_DISP, 4, 16, SM8350_MASTER_LLCC_DISP);
|
||||
DEFINE_QNODE(ebi_disp, SM8350_SLAVE_EBI1_DISP, 4, 4);
|
||||
DEFINE_QNODE(qns_mem_noc_hf_disp, SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP, 2, 32, SM8350_MASTER_MNOC_HF_MEM_NOC_DISP);
|
||||
DEFINE_QNODE(qns_mem_noc_sf_disp, SM8350_SLAVE_MNOC_SF_MEM_NOC_DISP, 2, 32, SM8350_MASTER_MNOC_SF_MEM_NOC_DISP);
|
||||
|
||||
DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
|
||||
DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
|
||||
DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie);
|
||||
DEFINE_QBCM(bcm_cn1, "CN1", false, &xm_qdss_dap, &qhs_ahb2phy0, &qhs_ahb2phy1, &qhs_aoss, &qhs_apss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_cfg, &qhs_cpr_cx, &qhs_cpr_mmcx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_cx_rdpm, &qhs_dcc_cfg, &qhs_display_cfg, &qhs_gpuss_cfg, &qhs_hwkm, &qhs_imem_cfg, &qhs_ipa, &qhs_ipc_router, &qhs_mss_cfg, &qhs_mx_rdpm, &qhs_pcie0_cfg, &qhs_pcie1_cfg, &qhs_pimem_cfg, &qhs_pka_wrapper_cfg, &qhs_pmu_wrapper_cfg, &qhs_qdss_cfg, &qhs_qup0, &qhs_qup1, &qhs_qup2, &qhs_security, &qhs_spss_cfg, &qhs_tcsr, &qhs_tlmm, &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_a1_noc_cfg, &qns_a2_noc_cfg, &qns_ddrss_cfg, &qns_mnoc_cfg, &qns_snoc_cfg, &srvc_cnoc);
|
||||
DEFINE_QBCM(bcm_cn2, "CN2", false, &qhs_lpass_cfg, &qhs_pdm, &qhs_qspi, &qhs_sdc2, &qhs_sdc4);
|
||||
DEFINE_QBCM(bcm_co0, "CO0", false, &qns_nsp_gemnoc);
|
||||
DEFINE_QBCM(bcm_co3, "CO3", false, &qxm_nsp);
|
||||
DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
|
||||
DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf);
|
||||
DEFINE_QBCM(bcm_mm1, "MM1", false, &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1);
|
||||
DEFINE_QBCM(bcm_mm4, "MM4", false, &qns_mem_noc_sf);
|
||||
DEFINE_QBCM(bcm_mm5, "MM5", false, &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_video0, &qnm_video1, &qnm_video_cvp, &qxm_rot);
|
||||
DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
|
||||
DEFINE_QBCM(bcm_sh2, "SH2", false, &alm_gpu_tcu, &alm_sys_tcu);
|
||||
DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc);
|
||||
DEFINE_QBCM(bcm_sh4, "SH4", false, &chm_apps);
|
||||
DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf);
|
||||
DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc);
|
||||
DEFINE_QBCM(bcm_sn3, "SN3", false, &qxs_pimem);
|
||||
DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_qdss_stm);
|
||||
DEFINE_QBCM(bcm_sn5, "SN5", false, &xm_pcie3_0);
|
||||
DEFINE_QBCM(bcm_sn6, "SN6", false, &xm_pcie3_1);
|
||||
DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre1_noc);
|
||||
DEFINE_QBCM(bcm_sn8, "SN8", false, &qnm_aggre2_noc);
|
||||
DEFINE_QBCM(bcm_sn14, "SN14", false, &qns_pcie_mem_noc);
|
||||
DEFINE_QBCM(bcm_acv_disp, "ACV", false, &ebi_disp);
|
||||
DEFINE_QBCM(bcm_mc0_disp, "MC0", false, &ebi_disp);
|
||||
DEFINE_QBCM(bcm_mm0_disp, "MM0", false, &qns_mem_noc_hf_disp);
|
||||
DEFINE_QBCM(bcm_mm1_disp, "MM1", false, &qxm_mdp0_disp, &qxm_mdp1_disp);
|
||||
DEFINE_QBCM(bcm_mm4_disp, "MM4", false, &qns_mem_noc_sf_disp);
|
||||
DEFINE_QBCM(bcm_mm5_disp, "MM5", false, &qxm_rot_disp);
|
||||
DEFINE_QBCM(bcm_sh0_disp, "SH0", false, &qns_llcc_disp);
|
||||
|
||||
static struct qcom_icc_bcm *aggre1_noc_bcms[] = {
|
||||
};
|
||||
|
||||
static struct qcom_icc_node *aggre1_noc_nodes[] = {
|
||||
[MASTER_QSPI_0] = &qhm_qspi,
|
||||
[MASTER_QUP_1] = &qhm_qup1,
|
||||
[MASTER_A1NOC_CFG] = &qnm_a1noc_cfg,
|
||||
[MASTER_SDCC_4] = &xm_sdc4,
|
||||
[MASTER_UFS_MEM] = &xm_ufs_mem,
|
||||
[MASTER_USB3_0] = &xm_usb3_0,
|
||||
[MASTER_USB3_1] = &xm_usb3_1,
|
||||
[SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
|
||||
[SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
|
||||
};
|
||||
|
||||
static struct qcom_icc_desc sm8350_aggre1_noc = {
|
||||
.nodes = aggre1_noc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
|
||||
.bcms = aggre1_noc_bcms,
|
||||
.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm *aggre2_noc_bcms[] = {
|
||||
&bcm_ce0,
|
||||
&bcm_sn5,
|
||||
&bcm_sn6,
|
||||
&bcm_sn14,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node *aggre2_noc_nodes[] = {
|
||||
[MASTER_QDSS_BAM] = &qhm_qdss_bam,
|
||||
[MASTER_QUP_0] = &qhm_qup0,
|
||||
[MASTER_QUP_2] = &qhm_qup2,
|
||||
[MASTER_A2NOC_CFG] = &qnm_a2noc_cfg,
|
||||
[MASTER_CRYPTO] = &qxm_crypto,
|
||||
[MASTER_IPA] = &qxm_ipa,
|
||||
[MASTER_PCIE_0] = &xm_pcie3_0,
|
||||
[MASTER_PCIE_1] = &xm_pcie3_1,
|
||||
[MASTER_QDSS_ETR] = &xm_qdss_etr,
|
||||
[MASTER_SDCC_2] = &xm_sdc2,
|
||||
[MASTER_UFS_CARD] = &xm_ufs_card,
|
||||
[SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
|
||||
[SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
|
||||
[SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
|
||||
};
|
||||
|
||||
static struct qcom_icc_desc sm8350_aggre2_noc = {
|
||||
.nodes = aggre2_noc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
|
||||
.bcms = aggre2_noc_bcms,
|
||||
.num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm *config_noc_bcms[] = {
|
||||
&bcm_cn0,
|
||||
&bcm_cn1,
|
||||
&bcm_cn2,
|
||||
&bcm_sn3,
|
||||
&bcm_sn4,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node *config_noc_nodes[] = {
|
||||
[MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
|
||||
[MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
|
||||
[MASTER_QDSS_DAP] = &xm_qdss_dap,
|
||||
[SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
|
||||
[SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1,
|
||||
[SLAVE_AOSS] = &qhs_aoss,
|
||||
[SLAVE_APPSS] = &qhs_apss,
|
||||
[SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
|
||||
[SLAVE_CLK_CTL] = &qhs_clk_ctl,
|
||||
[SLAVE_CDSP_CFG] = &qhs_compute_cfg,
|
||||
[SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
|
||||
[SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx,
|
||||
[SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
|
||||
[SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
|
||||
[SLAVE_CX_RDPM] = &qhs_cx_rdpm,
|
||||
[SLAVE_DCC_CFG] = &qhs_dcc_cfg,
|
||||
[SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
|
||||
[SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
|
||||
[SLAVE_HWKM] = &qhs_hwkm,
|
||||
[SLAVE_IMEM_CFG] = &qhs_imem_cfg,
|
||||
[SLAVE_IPA_CFG] = &qhs_ipa,
|
||||
[SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
|
||||
[SLAVE_LPASS] = &qhs_lpass_cfg,
|
||||
[SLAVE_CNOC_MSS] = &qhs_mss_cfg,
|
||||
[SLAVE_MX_RDPM] = &qhs_mx_rdpm,
|
||||
[SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
|
||||
[SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
|
||||
[SLAVE_PDM] = &qhs_pdm,
|
||||
[SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
|
||||
[SLAVE_PKA_WRAPPER_CFG] = &qhs_pka_wrapper_cfg,
|
||||
[SLAVE_PMU_WRAPPER_CFG] = &qhs_pmu_wrapper_cfg,
|
||||
[SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
|
||||
[SLAVE_QSPI_0] = &qhs_qspi,
|
||||
[SLAVE_QUP_0] = &qhs_qup0,
|
||||
[SLAVE_QUP_1] = &qhs_qup1,
|
||||
[SLAVE_QUP_2] = &qhs_qup2,
|
||||
[SLAVE_SDCC_2] = &qhs_sdc2,
|
||||
[SLAVE_SDCC_4] = &qhs_sdc4,
|
||||
[SLAVE_SECURITY] = &qhs_security,
|
||||
[SLAVE_SPSS_CFG] = &qhs_spss_cfg,
|
||||
[SLAVE_TCSR] = &qhs_tcsr,
|
||||
[SLAVE_TLMM] = &qhs_tlmm,
|
||||
[SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg,
|
||||
[SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
|
||||
[SLAVE_USB3_0] = &qhs_usb3_0,
|
||||
[SLAVE_USB3_1] = &qhs_usb3_1,
|
||||
[SLAVE_VENUS_CFG] = &qhs_venus_cfg,
|
||||
[SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
|
||||
[SLAVE_A1NOC_CFG] = &qns_a1_noc_cfg,
|
||||
[SLAVE_A2NOC_CFG] = &qns_a2_noc_cfg,
|
||||
[SLAVE_DDRSS_CFG] = &qns_ddrss_cfg,
|
||||
[SLAVE_CNOC_MNOC_CFG] = &qns_mnoc_cfg,
|
||||
[SLAVE_SNOC_CFG] = &qns_snoc_cfg,
|
||||
[SLAVE_BOOT_IMEM] = &qxs_boot_imem,
|
||||
[SLAVE_IMEM] = &qxs_imem,
|
||||
[SLAVE_PIMEM] = &qxs_pimem,
|
||||
[SLAVE_SERVICE_CNOC] = &srvc_cnoc,
|
||||
[SLAVE_PCIE_0] = &xs_pcie_0,
|
||||
[SLAVE_PCIE_1] = &xs_pcie_1,
|
||||
[SLAVE_QDSS_STM] = &xs_qdss_stm,
|
||||
[SLAVE_TCU] = &xs_sys_tcu_cfg,
|
||||
};
|
||||
|
||||
static struct qcom_icc_desc sm8350_config_noc = {
|
||||
.nodes = config_noc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(config_noc_nodes),
|
||||
.bcms = config_noc_bcms,
|
||||
.num_bcms = ARRAY_SIZE(config_noc_bcms),
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm *dc_noc_bcms[] = {
|
||||
};
|
||||
|
||||
static struct qcom_icc_node *dc_noc_nodes[] = {
|
||||
[MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc,
|
||||
[SLAVE_LLCC_CFG] = &qhs_llcc,
|
||||
[SLAVE_GEM_NOC_CFG] = &qns_gemnoc,
|
||||
};
|
||||
|
||||
static struct qcom_icc_desc sm8350_dc_noc = {
|
||||
.nodes = dc_noc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
|
||||
.bcms = dc_noc_bcms,
|
||||
.num_bcms = ARRAY_SIZE(dc_noc_bcms),
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm *gem_noc_bcms[] = {
|
||||
&bcm_sh0,
|
||||
&bcm_sh2,
|
||||
&bcm_sh3,
|
||||
&bcm_sh4,
|
||||
&bcm_sh0_disp,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node *gem_noc_nodes[] = {
|
||||
[MASTER_GPU_TCU] = &alm_gpu_tcu,
|
||||
[MASTER_SYS_TCU] = &alm_sys_tcu,
|
||||
[MASTER_APPSS_PROC] = &chm_apps,
|
||||
[MASTER_COMPUTE_NOC] = &qnm_cmpnoc,
|
||||
[MASTER_GEM_NOC_CFG] = &qnm_gemnoc_cfg,
|
||||
[MASTER_GFX3D] = &qnm_gpu,
|
||||
[MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
|
||||
[MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
|
||||
[MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
|
||||
[MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
|
||||
[MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
|
||||
[SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg,
|
||||
[SLAVE_MCDMA_MS_MPU_CFG] = &qhs_modem_ms_mpu_cfg,
|
||||
[SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
|
||||
[SLAVE_LLCC] = &qns_llcc,
|
||||
[SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
|
||||
[SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc,
|
||||
[SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc,
|
||||
[SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc,
|
||||
[MASTER_MNOC_HF_MEM_NOC_DISP] = &qnm_mnoc_hf_disp,
|
||||
[MASTER_MNOC_SF_MEM_NOC_DISP] = &qnm_mnoc_sf_disp,
|
||||
[SLAVE_LLCC_DISP] = &qns_llcc_disp,
|
||||
};
|
||||
|
||||
static struct qcom_icc_desc sm8350_gem_noc = {
|
||||
.nodes = gem_noc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
|
||||
.bcms = gem_noc_bcms,
|
||||
.num_bcms = ARRAY_SIZE(gem_noc_bcms),
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm *lpass_ag_noc_bcms[] = {
|
||||
};
|
||||
|
||||
static struct qcom_icc_node *lpass_ag_noc_nodes[] = {
|
||||
[MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc,
|
||||
[SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core,
|
||||
[SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi,
|
||||
[SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu,
|
||||
[SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top,
|
||||
[SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc,
|
||||
[SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc,
|
||||
};
|
||||
|
||||
static struct qcom_icc_desc sm8350_lpass_ag_noc = {
|
||||
.nodes = lpass_ag_noc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
|
||||
.bcms = lpass_ag_noc_bcms,
|
||||
.num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms),
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm *mc_virt_bcms[] = {
|
||||
&bcm_acv,
|
||||
&bcm_mc0,
|
||||
&bcm_acv_disp,
|
||||
&bcm_mc0_disp,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node *mc_virt_nodes[] = {
|
||||
[MASTER_LLCC] = &llcc_mc,
|
||||
[SLAVE_EBI1] = &ebi,
|
||||
[MASTER_LLCC_DISP] = &llcc_mc_disp,
|
||||
[SLAVE_EBI1_DISP] = &ebi_disp,
|
||||
};
|
||||
|
||||
static struct qcom_icc_desc sm8350_mc_virt = {
|
||||
.nodes = mc_virt_nodes,
|
||||
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
|
||||
.bcms = mc_virt_bcms,
|
||||
.num_bcms = ARRAY_SIZE(mc_virt_bcms),
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm *mmss_noc_bcms[] = {
|
||||
&bcm_mm0,
|
||||
&bcm_mm1,
|
||||
&bcm_mm4,
|
||||
&bcm_mm5,
|
||||
&bcm_mm0_disp,
|
||||
&bcm_mm1_disp,
|
||||
&bcm_mm4_disp,
|
||||
&bcm_mm5_disp,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node *mmss_noc_nodes[] = {
|
||||
[MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
|
||||
[MASTER_CAMNOC_ICP] = &qnm_camnoc_icp,
|
||||
[MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
|
||||
[MASTER_CNOC_MNOC_CFG] = &qnm_mnoc_cfg,
|
||||
[MASTER_VIDEO_P0] = &qnm_video0,
|
||||
[MASTER_VIDEO_P1] = &qnm_video1,
|
||||
[MASTER_VIDEO_PROC] = &qnm_video_cvp,
|
||||
[MASTER_MDP0] = &qxm_mdp0,
|
||||
[MASTER_MDP1] = &qxm_mdp1,
|
||||
[MASTER_ROTATOR] = &qxm_rot,
|
||||
[SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
|
||||
[SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
|
||||
[SLAVE_SERVICE_MNOC] = &srvc_mnoc,
|
||||
[MASTER_MDP0_DISP] = &qxm_mdp0_disp,
|
||||
[MASTER_MDP1_DISP] = &qxm_mdp1_disp,
|
||||
[MASTER_ROTATOR_DISP] = &qxm_rot_disp,
|
||||
[SLAVE_MNOC_HF_MEM_NOC_DISP] = &qns_mem_noc_hf_disp,
|
||||
[SLAVE_MNOC_SF_MEM_NOC_DISP] = &qns_mem_noc_sf_disp,
|
||||
};
|
||||
|
||||
static struct qcom_icc_desc sm8350_mmss_noc = {
|
||||
.nodes = mmss_noc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
|
||||
.bcms = mmss_noc_bcms,
|
||||
.num_bcms = ARRAY_SIZE(mmss_noc_bcms),
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm *nsp_noc_bcms[] = {
|
||||
&bcm_co0,
|
||||
&bcm_co3,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node *nsp_noc_nodes[] = {
|
||||
[MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config,
|
||||
[MASTER_CDSP_PROC] = &qxm_nsp,
|
||||
[SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,
|
||||
[SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc,
|
||||
};
|
||||
|
||||
static struct qcom_icc_desc sm8350_compute_noc = {
|
||||
.nodes = nsp_noc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
|
||||
.bcms = nsp_noc_bcms,
|
||||
.num_bcms = ARRAY_SIZE(nsp_noc_bcms),
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm *system_noc_bcms[] = {
|
||||
&bcm_sn0,
|
||||
&bcm_sn2,
|
||||
&bcm_sn7,
|
||||
&bcm_sn8,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node *system_noc_nodes[] = {
|
||||
[MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
|
||||
[MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
|
||||
[MASTER_SNOC_CFG] = &qnm_snoc_cfg,
|
||||
[MASTER_PIMEM] = &qxm_pimem,
|
||||
[MASTER_GIC] = &xm_gic,
|
||||
[SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
|
||||
[SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
|
||||
[SLAVE_SERVICE_SNOC] = &srvc_snoc,
|
||||
};
|
||||
|
||||
static struct qcom_icc_desc sm8350_system_noc = {
|
||||
.nodes = system_noc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(system_noc_nodes),
|
||||
.bcms = system_noc_bcms,
|
||||
.num_bcms = ARRAY_SIZE(system_noc_bcms),
|
||||
};
|
||||
|
||||
static int qnoc_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct qcom_icc_desc *desc;
|
||||
struct icc_onecell_data *data;
|
||||
struct icc_provider *provider;
|
||||
struct qcom_icc_node **qnodes;
|
||||
struct qcom_icc_provider *qp;
|
||||
struct icc_node *node;
|
||||
size_t num_nodes, i;
|
||||
int ret;
|
||||
|
||||
desc = of_device_get_match_data(&pdev->dev);
|
||||
if (!desc)
|
||||
return -EINVAL;
|
||||
|
||||
qnodes = desc->nodes;
|
||||
num_nodes = desc->num_nodes;
|
||||
|
||||
qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL);
|
||||
if (!qp)
|
||||
return -ENOMEM;
|
||||
|
||||
data = devm_kcalloc(&pdev->dev, num_nodes, sizeof(*node), GFP_KERNEL);
|
||||
if (!data)
|
||||
return -ENOMEM;
|
||||
|
||||
provider = &qp->provider;
|
||||
provider->dev = &pdev->dev;
|
||||
provider->set = qcom_icc_set;
|
||||
provider->pre_aggregate = qcom_icc_pre_aggregate;
|
||||
provider->aggregate = qcom_icc_aggregate;
|
||||
provider->xlate = of_icc_xlate_onecell;
|
||||
INIT_LIST_HEAD(&provider->nodes);
|
||||
provider->data = data;
|
||||
|
||||
qp->dev = &pdev->dev;
|
||||
qp->bcms = desc->bcms;
|
||||
qp->num_bcms = desc->num_bcms;
|
||||
|
||||
qp->voter = of_bcm_voter_get(qp->dev, NULL);
|
||||
if (IS_ERR(qp->voter))
|
||||
return PTR_ERR(qp->voter);
|
||||
|
||||
ret = icc_provider_add(provider);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "error adding interconnect provider\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
for (i = 0; i < qp->num_bcms; i++)
|
||||
qcom_icc_bcm_init(qp->bcms[i], &pdev->dev);
|
||||
|
||||
for (i = 0; i < num_nodes; i++) {
|
||||
size_t j;
|
||||
|
||||
if (!qnodes[i])
|
||||
continue;
|
||||
|
||||
node = icc_node_create(qnodes[i]->id);
|
||||
if (IS_ERR(node)) {
|
||||
ret = PTR_ERR(node);
|
||||
goto err;
|
||||
}
|
||||
|
||||
node->name = qnodes[i]->name;
|
||||
node->data = qnodes[i];
|
||||
icc_node_add(node, provider);
|
||||
|
||||
for (j = 0; j < qnodes[i]->num_links; j++)
|
||||
icc_link_create(node, qnodes[i]->links[j]);
|
||||
|
||||
data->nodes[i] = node;
|
||||
}
|
||||
data->num_nodes = num_nodes;
|
||||
|
||||
platform_set_drvdata(pdev, qp);
|
||||
|
||||
return ret;
|
||||
|
||||
err:
|
||||
icc_nodes_remove(provider);
|
||||
icc_provider_del(provider);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int qnoc_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct qcom_icc_provider *qp = platform_get_drvdata(pdev);
|
||||
|
||||
icc_nodes_remove(&qp->provider);
|
||||
return icc_provider_del(&qp->provider);
|
||||
}
|
||||
|
||||
static const struct of_device_id qnoc_of_match[] = {
|
||||
{ .compatible = "qcom,sm8350-aggre1-noc", .data = &sm8350_aggre1_noc},
|
||||
{ .compatible = "qcom,sm8350-aggre2-noc", .data = &sm8350_aggre2_noc},
|
||||
{ .compatible = "qcom,sm8350-config-noc", .data = &sm8350_config_noc},
|
||||
{ .compatible = "qcom,sm8350-dc-noc", .data = &sm8350_dc_noc},
|
||||
{ .compatible = "qcom,sm8350-gem-noc", .data = &sm8350_gem_noc},
|
||||
{ .compatible = "qcom,sm8350-lpass-ag-noc", .data = &sm8350_lpass_ag_noc},
|
||||
{ .compatible = "qcom,sm8350-mc-virt", .data = &sm8350_mc_virt},
|
||||
{ .compatible = "qcom,sm8350-mmss-noc", .data = &sm8350_mmss_noc},
|
||||
{ .compatible = "qcom,sm8350-compute-noc", .data = &sm8350_compute_noc},
|
||||
{ .compatible = "qcom,sm8350-system-noc", .data = &sm8350_system_noc},
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, qnoc_of_match);
|
||||
|
||||
static struct platform_driver qnoc_driver = {
|
||||
.probe = qnoc_probe,
|
||||
.remove = qnoc_remove,
|
||||
.driver = {
|
||||
.name = "qnoc-sm8350",
|
||||
.of_match_table = qnoc_of_match,
|
||||
.sync_state = icc_sync_state,
|
||||
},
|
||||
};
|
||||
module_platform_driver(qnoc_driver);
|
||||
|
||||
MODULE_DESCRIPTION("SM8350 NoC driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
168
drivers/interconnect/qcom/sm8350.h
Normal file
168
drivers/interconnect/qcom/sm8350.h
Normal file
@ -0,0 +1,168 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Qualcomm SM8350 interconnect IDs
|
||||
*
|
||||
* Copyright (c) 2021, Linaro Limited
|
||||
*/
|
||||
|
||||
#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8350_H
|
||||
#define __DRIVERS_INTERCONNECT_QCOM_SM8350_H
|
||||
|
||||
#define SM8350_MASTER_GPU_TCU 0
|
||||
#define SM8350_MASTER_SYS_TCU 1
|
||||
#define SM8350_MASTER_APPSS_PROC 2
|
||||
#define SM8350_MASTER_LLCC 3
|
||||
#define SM8350_MASTER_CNOC_LPASS_AG_NOC 4
|
||||
#define SM8350_MASTER_CDSP_NOC_CFG 5
|
||||
#define SM8350_MASTER_QDSS_BAM 6
|
||||
#define SM8350_MASTER_QSPI_0 7
|
||||
#define SM8350_MASTER_QUP_0 8
|
||||
#define SM8350_MASTER_QUP_1 9
|
||||
#define SM8350_MASTER_QUP_2 10
|
||||
#define SM8350_MASTER_A1NOC_CFG 11
|
||||
#define SM8350_MASTER_A2NOC_CFG 12
|
||||
#define SM8350_MASTER_A1NOC_SNOC 13
|
||||
#define SM8350_MASTER_A2NOC_SNOC 14
|
||||
#define SM8350_MASTER_CAMNOC_HF 15
|
||||
#define SM8350_MASTER_CAMNOC_ICP 16
|
||||
#define SM8350_MASTER_CAMNOC_SF 17
|
||||
#define SM8350_MASTER_COMPUTE_NOC 18
|
||||
#define SM8350_MASTER_CNOC_DC_NOC 19
|
||||
#define SM8350_MASTER_GEM_NOC_CFG 20
|
||||
#define SM8350_MASTER_GEM_NOC_CNOC 21
|
||||
#define SM8350_MASTER_GEM_NOC_PCIE_SNOC 22
|
||||
#define SM8350_MASTER_GFX3D 23
|
||||
#define SM8350_MASTER_CNOC_MNOC_CFG 24
|
||||
#define SM8350_MASTER_MNOC_HF_MEM_NOC 25
|
||||
#define SM8350_MASTER_MNOC_SF_MEM_NOC 26
|
||||
#define SM8350_MASTER_ANOC_PCIE_GEM_NOC 27
|
||||
#define SM8350_MASTER_SNOC_CFG 28
|
||||
#define SM8350_MASTER_SNOC_GC_MEM_NOC 29
|
||||
#define SM8350_MASTER_SNOC_SF_MEM_NOC 30
|
||||
#define SM8350_MASTER_VIDEO_P0 31
|
||||
#define SM8350_MASTER_VIDEO_P1 32
|
||||
#define SM8350_MASTER_VIDEO_PROC 33
|
||||
#define SM8350_MASTER_QUP_CORE_0 34
|
||||
#define SM8350_MASTER_QUP_CORE_1 35
|
||||
#define SM8350_MASTER_QUP_CORE_2 36
|
||||
#define SM8350_MASTER_CRYPTO 37
|
||||
#define SM8350_MASTER_IPA 38
|
||||
#define SM8350_MASTER_MDP0 39
|
||||
#define SM8350_MASTER_MDP1 40
|
||||
#define SM8350_MASTER_CDSP_PROC 41
|
||||
#define SM8350_MASTER_PIMEM 42
|
||||
#define SM8350_MASTER_ROTATOR 43
|
||||
#define SM8350_MASTER_GIC 44
|
||||
#define SM8350_MASTER_PCIE_0 45
|
||||
#define SM8350_MASTER_PCIE_1 46
|
||||
#define SM8350_MASTER_QDSS_DAP 47
|
||||
#define SM8350_MASTER_QDSS_ETR 48
|
||||
#define SM8350_MASTER_SDCC_2 49
|
||||
#define SM8350_MASTER_SDCC_4 50
|
||||
#define SM8350_MASTER_UFS_CARD 51
|
||||
#define SM8350_MASTER_UFS_MEM 52
|
||||
#define SM8350_MASTER_USB3_0 53
|
||||
#define SM8350_MASTER_USB3_1 54
|
||||
#define SM8350_SLAVE_EBI1 55
|
||||
#define SM8350_SLAVE_AHB2PHY_SOUTH 56
|
||||
#define SM8350_SLAVE_AHB2PHY_NORTH 57
|
||||
#define SM8350_SLAVE_AOSS 58
|
||||
#define SM8350_SLAVE_APPSS 59
|
||||
#define SM8350_SLAVE_CAMERA_CFG 60
|
||||
#define SM8350_SLAVE_CLK_CTL 61
|
||||
#define SM8350_SLAVE_CDSP_CFG 62
|
||||
#define SM8350_SLAVE_RBCPR_CX_CFG 63
|
||||
#define SM8350_SLAVE_RBCPR_MMCX_CFG 64
|
||||
#define SM8350_SLAVE_RBCPR_MX_CFG 65
|
||||
#define SM8350_SLAVE_CRYPTO_0_CFG 66
|
||||
#define SM8350_SLAVE_CX_RDPM 67
|
||||
#define SM8350_SLAVE_DCC_CFG 68
|
||||
#define SM8350_SLAVE_DISPLAY_CFG 69
|
||||
#define SM8350_SLAVE_GFX3D_CFG 70
|
||||
#define SM8350_SLAVE_HWKM 71
|
||||
#define SM8350_SLAVE_IMEM_CFG 72
|
||||
#define SM8350_SLAVE_IPA_CFG 73
|
||||
#define SM8350_SLAVE_IPC_ROUTER_CFG 74
|
||||
#define SM8350_SLAVE_LLCC_CFG 75
|
||||
#define SM8350_SLAVE_LPASS 76
|
||||
#define SM8350_SLAVE_LPASS_CORE_CFG 77
|
||||
#define SM8350_SLAVE_LPASS_LPI_CFG 78
|
||||
#define SM8350_SLAVE_LPASS_MPU_CFG 79
|
||||
#define SM8350_SLAVE_LPASS_TOP_CFG 80
|
||||
#define SM8350_SLAVE_MSS_PROC_MS_MPU_CFG 81
|
||||
#define SM8350_SLAVE_MCDMA_MS_MPU_CFG 82
|
||||
#define SM8350_SLAVE_CNOC_MSS 83
|
||||
#define SM8350_SLAVE_MX_RDPM 84
|
||||
#define SM8350_SLAVE_PCIE_0_CFG 85
|
||||
#define SM8350_SLAVE_PCIE_1_CFG 86
|
||||
#define SM8350_SLAVE_PDM 87
|
||||
#define SM8350_SLAVE_PIMEM_CFG 88
|
||||
#define SM8350_SLAVE_PKA_WRAPPER_CFG 89
|
||||
#define SM8350_SLAVE_PMU_WRAPPER_CFG 90
|
||||
#define SM8350_SLAVE_QDSS_CFG 91
|
||||
#define SM8350_SLAVE_QSPI_0 92
|
||||
#define SM8350_SLAVE_QUP_0 93
|
||||
#define SM8350_SLAVE_QUP_1 94
|
||||
#define SM8350_SLAVE_QUP_2 95
|
||||
#define SM8350_SLAVE_SDCC_2 96
|
||||
#define SM8350_SLAVE_SDCC_4 97
|
||||
#define SM8350_SLAVE_SECURITY 98
|
||||
#define SM8350_SLAVE_SPSS_CFG 99
|
||||
#define SM8350_SLAVE_TCSR 100
|
||||
#define SM8350_SLAVE_TLMM 101
|
||||
#define SM8350_SLAVE_UFS_CARD_CFG 102
|
||||
#define SM8350_SLAVE_UFS_MEM_CFG 103
|
||||
#define SM8350_SLAVE_USB3_0 104
|
||||
#define SM8350_SLAVE_USB3_1 105
|
||||
#define SM8350_SLAVE_VENUS_CFG 106
|
||||
#define SM8350_SLAVE_VSENSE_CTRL_CFG 107
|
||||
#define SM8350_SLAVE_A1NOC_CFG 108
|
||||
#define SM8350_SLAVE_A1NOC_SNOC 109
|
||||
#define SM8350_SLAVE_A2NOC_CFG 110
|
||||
#define SM8350_SLAVE_A2NOC_SNOC 111
|
||||
#define SM8350_SLAVE_DDRSS_CFG 112
|
||||
#define SM8350_SLAVE_GEM_NOC_CNOC 113
|
||||
#define SM8350_SLAVE_GEM_NOC_CFG 114
|
||||
#define SM8350_SLAVE_SNOC_GEM_NOC_GC 115
|
||||
#define SM8350_SLAVE_SNOC_GEM_NOC_SF 116
|
||||
#define SM8350_SLAVE_LLCC 117
|
||||
#define SM8350_SLAVE_MNOC_HF_MEM_NOC 118
|
||||
#define SM8350_SLAVE_MNOC_SF_MEM_NOC 119
|
||||
#define SM8350_SLAVE_CNOC_MNOC_CFG 120
|
||||
#define SM8350_SLAVE_CDSP_MEM_NOC 121
|
||||
#define SM8350_SLAVE_MEM_NOC_PCIE_SNOC 122
|
||||
#define SM8350_SLAVE_ANOC_PCIE_GEM_NOC 123
|
||||
#define SM8350_SLAVE_SNOC_CFG 124
|
||||
#define SM8350_SLAVE_QUP_CORE_0 125
|
||||
#define SM8350_SLAVE_QUP_CORE_1 126
|
||||
#define SM8350_SLAVE_QUP_CORE_2 127
|
||||
#define SM8350_SLAVE_BOOT_IMEM 128
|
||||
#define SM8350_SLAVE_IMEM 129
|
||||
#define SM8350_SLAVE_PIMEM 130
|
||||
#define SM8350_SLAVE_SERVICE_NSP_NOC 131
|
||||
#define SM8350_SLAVE_SERVICE_A1NOC 132
|
||||
#define SM8350_SLAVE_SERVICE_A2NOC 133
|
||||
#define SM8350_SLAVE_SERVICE_CNOC 134
|
||||
#define SM8350_SLAVE_SERVICE_GEM_NOC_1 135
|
||||
#define SM8350_SLAVE_SERVICE_MNOC 136
|
||||
#define SM8350_SLAVE_SERVICES_LPASS_AML_NOC 137
|
||||
#define SM8350_SLAVE_SERVICE_LPASS_AG_NOC 138
|
||||
#define SM8350_SLAVE_SERVICE_GEM_NOC_2 139
|
||||
#define SM8350_SLAVE_SERVICE_SNOC 140
|
||||
#define SM8350_SLAVE_SERVICE_GEM_NOC 141
|
||||
#define SM8350_SLAVE_PCIE_0 142
|
||||
#define SM8350_SLAVE_PCIE_1 143
|
||||
#define SM8350_SLAVE_QDSS_STM 144
|
||||
#define SM8350_SLAVE_TCU 145
|
||||
#define SM8350_MASTER_LLCC_DISP 146
|
||||
#define SM8350_MASTER_MNOC_HF_MEM_NOC_DISP 147
|
||||
#define SM8350_MASTER_MNOC_SF_MEM_NOC_DISP 148
|
||||
#define SM8350_MASTER_MDP0_DISP 149
|
||||
#define SM8350_MASTER_MDP1_DISP 150
|
||||
#define SM8350_MASTER_ROTATOR_DISP 151
|
||||
#define SM8350_SLAVE_EBI1_DISP 152
|
||||
#define SM8350_SLAVE_LLCC_DISP 153
|
||||
#define SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP 154
|
||||
#define SM8350_SLAVE_MNOC_SF_MEM_NOC_DISP 155
|
||||
|
||||
#endif
|
||||
116
include/dt-bindings/interconnect/qcom,sdm660.h
Normal file
116
include/dt-bindings/interconnect/qcom,sdm660.h
Normal file
@ -0,0 +1,116 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/* SDM660 interconnect IDs */
|
||||
|
||||
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SDM660_H
|
||||
#define __DT_BINDINGS_INTERCONNECT_QCOM_SDM660_H
|
||||
|
||||
/* A2NOC */
|
||||
#define MASTER_IPA 0
|
||||
#define MASTER_CNOC_A2NOC 1
|
||||
#define MASTER_SDCC_1 2
|
||||
#define MASTER_SDCC_2 3
|
||||
#define MASTER_BLSP_1 4
|
||||
#define MASTER_BLSP_2 5
|
||||
#define MASTER_UFS 6
|
||||
#define MASTER_USB_HS 7
|
||||
#define MASTER_USB3 8
|
||||
#define MASTER_CRYPTO_C0 9
|
||||
#define SLAVE_A2NOC_SNOC 10
|
||||
|
||||
/* BIMC */
|
||||
#define MASTER_GNOC_BIMC 0
|
||||
#define MASTER_OXILI 1
|
||||
#define MASTER_MNOC_BIMC 2
|
||||
#define MASTER_SNOC_BIMC 3
|
||||
#define MASTER_PIMEM 4
|
||||
#define SLAVE_EBI 5
|
||||
#define SLAVE_HMSS_L3 6
|
||||
#define SLAVE_BIMC_SNOC 7
|
||||
|
||||
/* CNOC */
|
||||
#define MASTER_SNOC_CNOC 0
|
||||
#define MASTER_QDSS_DAP 1
|
||||
#define SLAVE_CNOC_A2NOC 2
|
||||
#define SLAVE_MPM 3
|
||||
#define SLAVE_PMIC_ARB 4
|
||||
#define SLAVE_TLMM_NORTH 5
|
||||
#define SLAVE_TCSR 6
|
||||
#define SLAVE_PIMEM_CFG 7
|
||||
#define SLAVE_IMEM_CFG 8
|
||||
#define SLAVE_MESSAGE_RAM 9
|
||||
#define SLAVE_GLM 10
|
||||
#define SLAVE_BIMC_CFG 11
|
||||
#define SLAVE_PRNG 12
|
||||
#define SLAVE_SPDM 13
|
||||
#define SLAVE_QDSS_CFG 14
|
||||
#define SLAVE_CNOC_MNOC_CFG 15
|
||||
#define SLAVE_SNOC_CFG 16
|
||||
#define SLAVE_QM_CFG 17
|
||||
#define SLAVE_CLK_CTL 18
|
||||
#define SLAVE_MSS_CFG 19
|
||||
#define SLAVE_TLMM_SOUTH 20
|
||||
#define SLAVE_UFS_CFG 21
|
||||
#define SLAVE_A2NOC_CFG 22
|
||||
#define SLAVE_A2NOC_SMMU_CFG 23
|
||||
#define SLAVE_GPUSS_CFG 24
|
||||
#define SLAVE_AHB2PHY 25
|
||||
#define SLAVE_BLSP_1 26
|
||||
#define SLAVE_SDCC_1 27
|
||||
#define SLAVE_SDCC_2 28
|
||||
#define SLAVE_TLMM_CENTER 29
|
||||
#define SLAVE_BLSP_2 30
|
||||
#define SLAVE_PDM 31
|
||||
#define SLAVE_CNOC_MNOC_MMSS_CFG 32
|
||||
#define SLAVE_USB_HS 33
|
||||
#define SLAVE_USB3_0 34
|
||||
#define SLAVE_SRVC_CNOC 35
|
||||
|
||||
/* GNOC */
|
||||
#define MASTER_APSS_PROC 0
|
||||
#define SLAVE_GNOC_BIMC 1
|
||||
#define SLAVE_GNOC_SNOC 2
|
||||
|
||||
/* MNOC */
|
||||
#define MASTER_CPP 0
|
||||
#define MASTER_JPEG 1
|
||||
#define MASTER_MDP_P0 2
|
||||
#define MASTER_MDP_P1 3
|
||||
#define MASTER_VENUS 4
|
||||
#define MASTER_VFE 5
|
||||
#define SLAVE_MNOC_BIMC 6
|
||||
#define MASTER_CNOC_MNOC_MMSS_CFG 7
|
||||
#define MASTER_CNOC_MNOC_CFG 8
|
||||
#define SLAVE_CAMERA_CFG 9
|
||||
#define SLAVE_CAMERA_THROTTLE_CFG 10
|
||||
#define SLAVE_MISC_CFG 11
|
||||
#define SLAVE_VENUS_THROTTLE_CFG 12
|
||||
#define SLAVE_VENUS_CFG 13
|
||||
#define SLAVE_MMSS_CLK_XPU_CFG 14
|
||||
#define SLAVE_MMSS_CLK_CFG 15
|
||||
#define SLAVE_MNOC_MPU_CFG 16
|
||||
#define SLAVE_DISPLAY_CFG 17
|
||||
#define SLAVE_CSI_PHY_CFG 18
|
||||
#define SLAVE_DISPLAY_THROTTLE_CFG 19
|
||||
#define SLAVE_SMMU_CFG 20
|
||||
#define SLAVE_SRVC_MNOC 21
|
||||
|
||||
/* SNOC */
|
||||
#define MASTER_QDSS_ETR 0
|
||||
#define MASTER_QDSS_BAM 1
|
||||
#define MASTER_SNOC_CFG 2
|
||||
#define MASTER_BIMC_SNOC 3
|
||||
#define MASTER_A2NOC_SNOC 4
|
||||
#define MASTER_GNOC_SNOC 5
|
||||
#define SLAVE_HMSS 6
|
||||
#define SLAVE_LPASS 7
|
||||
#define SLAVE_WLAN 8
|
||||
#define SLAVE_CDSP 9
|
||||
#define SLAVE_IPA 10
|
||||
#define SLAVE_SNOC_BIMC 11
|
||||
#define SLAVE_SNOC_CNOC 12
|
||||
#define SLAVE_IMEM 13
|
||||
#define SLAVE_PIMEM 14
|
||||
#define SLAVE_QDSS_STM 15
|
||||
#define SLAVE_SRVC_SNOC 16
|
||||
|
||||
#endif
|
||||
172
include/dt-bindings/interconnect/qcom,sm8350.h
Normal file
172
include/dt-bindings/interconnect/qcom,sm8350.h
Normal file
@ -0,0 +1,172 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Qualcomm SM8350 interconnect IDs
|
||||
*
|
||||
* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2021, Linaro Limited
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM8350_H
|
||||
#define __DT_BINDINGS_INTERCONNECT_QCOM_SM8350_H
|
||||
|
||||
#define MASTER_QSPI_0 0
|
||||
#define MASTER_QUP_1 1
|
||||
#define MASTER_A1NOC_CFG 2
|
||||
#define MASTER_SDCC_4 3
|
||||
#define MASTER_UFS_MEM 4
|
||||
#define MASTER_USB3_0 5
|
||||
#define MASTER_USB3_1 6
|
||||
#define SLAVE_A1NOC_SNOC 7
|
||||
#define SLAVE_SERVICE_A1NOC 8
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#define MASTER_QDSS_BAM 0
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#define MASTER_QUP_0 1
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#define MASTER_QUP_2 2
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#define MASTER_A2NOC_CFG 3
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#define MASTER_CRYPTO 4
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#define MASTER_IPA 5
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#define MASTER_PCIE_0 6
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#define MASTER_PCIE_1 7
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#define MASTER_QDSS_ETR 8
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#define MASTER_SDCC_2 9
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#define MASTER_UFS_CARD 10
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||||
#define SLAVE_A2NOC_SNOC 11
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||||
#define SLAVE_ANOC_PCIE_GEM_NOC 12
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||||
#define SLAVE_SERVICE_A2NOC 13
|
||||
|
||||
#define MASTER_GEM_NOC_CNOC 0
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#define MASTER_GEM_NOC_PCIE_SNOC 1
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||||
#define MASTER_QDSS_DAP 2
|
||||
#define SLAVE_AHB2PHY_SOUTH 3
|
||||
#define SLAVE_AHB2PHY_NORTH 4
|
||||
#define SLAVE_AOSS 5
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||||
#define SLAVE_APPSS 6
|
||||
#define SLAVE_CAMERA_CFG 7
|
||||
#define SLAVE_CLK_CTL 8
|
||||
#define SLAVE_CDSP_CFG 9
|
||||
#define SLAVE_RBCPR_CX_CFG 10
|
||||
#define SLAVE_RBCPR_MMCX_CFG 11
|
||||
#define SLAVE_RBCPR_MX_CFG 12
|
||||
#define SLAVE_CRYPTO_0_CFG 13
|
||||
#define SLAVE_CX_RDPM 14
|
||||
#define SLAVE_DCC_CFG 15
|
||||
#define SLAVE_DISPLAY_CFG 16
|
||||
#define SLAVE_GFX3D_CFG 17
|
||||
#define SLAVE_HWKM 18
|
||||
#define SLAVE_IMEM_CFG 19
|
||||
#define SLAVE_IPA_CFG 20
|
||||
#define SLAVE_IPC_ROUTER_CFG 21
|
||||
#define SLAVE_LPASS 22
|
||||
#define SLAVE_CNOC_MSS 23
|
||||
#define SLAVE_MX_RDPM 24
|
||||
#define SLAVE_PCIE_0_CFG 25
|
||||
#define SLAVE_PCIE_1_CFG 26
|
||||
#define SLAVE_PDM 27
|
||||
#define SLAVE_PIMEM_CFG 28
|
||||
#define SLAVE_PKA_WRAPPER_CFG 29
|
||||
#define SLAVE_PMU_WRAPPER_CFG 30
|
||||
#define SLAVE_QDSS_CFG 31
|
||||
#define SLAVE_QSPI_0 32
|
||||
#define SLAVE_QUP_0 33
|
||||
#define SLAVE_QUP_1 34
|
||||
#define SLAVE_QUP_2 35
|
||||
#define SLAVE_SDCC_2 36
|
||||
#define SLAVE_SDCC_4 37
|
||||
#define SLAVE_SECURITY 38
|
||||
#define SLAVE_SPSS_CFG 39
|
||||
#define SLAVE_TCSR 40
|
||||
#define SLAVE_TLMM 41
|
||||
#define SLAVE_UFS_CARD_CFG 42
|
||||
#define SLAVE_UFS_MEM_CFG 43
|
||||
#define SLAVE_USB3_0 44
|
||||
#define SLAVE_USB3_1 45
|
||||
#define SLAVE_VENUS_CFG 46
|
||||
#define SLAVE_VSENSE_CTRL_CFG 47
|
||||
#define SLAVE_A1NOC_CFG 48
|
||||
#define SLAVE_A2NOC_CFG 49
|
||||
#define SLAVE_DDRSS_CFG 50
|
||||
#define SLAVE_CNOC_MNOC_CFG 51
|
||||
#define SLAVE_SNOC_CFG 52
|
||||
#define SLAVE_BOOT_IMEM 53
|
||||
#define SLAVE_IMEM 54
|
||||
#define SLAVE_PIMEM 55
|
||||
#define SLAVE_SERVICE_CNOC 56
|
||||
#define SLAVE_PCIE_0 57
|
||||
#define SLAVE_PCIE_1 58
|
||||
#define SLAVE_QDSS_STM 59
|
||||
#define SLAVE_TCU 60
|
||||
|
||||
#define MASTER_CNOC_DC_NOC 0
|
||||
#define SLAVE_LLCC_CFG 1
|
||||
#define SLAVE_GEM_NOC_CFG 2
|
||||
|
||||
#define MASTER_GPU_TCU 0
|
||||
#define MASTER_SYS_TCU 1
|
||||
#define MASTER_APPSS_PROC 2
|
||||
#define MASTER_COMPUTE_NOC 3
|
||||
#define MASTER_GEM_NOC_CFG 4
|
||||
#define MASTER_GFX3D 5
|
||||
#define MASTER_MNOC_HF_MEM_NOC 6
|
||||
#define MASTER_MNOC_SF_MEM_NOC 7
|
||||
#define MASTER_ANOC_PCIE_GEM_NOC 8
|
||||
#define MASTER_SNOC_GC_MEM_NOC 9
|
||||
#define MASTER_SNOC_SF_MEM_NOC 10
|
||||
#define SLAVE_MSS_PROC_MS_MPU_CFG 11
|
||||
#define SLAVE_MCDMA_MS_MPU_CFG 12
|
||||
#define SLAVE_GEM_NOC_CNOC 13
|
||||
#define SLAVE_LLCC 14
|
||||
#define SLAVE_MEM_NOC_PCIE_SNOC 15
|
||||
#define SLAVE_SERVICE_GEM_NOC_1 16
|
||||
#define SLAVE_SERVICE_GEM_NOC_2 17
|
||||
#define SLAVE_SERVICE_GEM_NOC 18
|
||||
#define MASTER_MNOC_HF_MEM_NOC_DISP 19
|
||||
#define MASTER_MNOC_SF_MEM_NOC_DISP 20
|
||||
#define SLAVE_LLCC_DISP 21
|
||||
|
||||
#define MASTER_CNOC_LPASS_AG_NOC 0
|
||||
#define SLAVE_LPASS_CORE_CFG 1
|
||||
#define SLAVE_LPASS_LPI_CFG 2
|
||||
#define SLAVE_LPASS_MPU_CFG 3
|
||||
#define SLAVE_LPASS_TOP_CFG 4
|
||||
#define SLAVE_SERVICES_LPASS_AML_NOC 5
|
||||
#define SLAVE_SERVICE_LPASS_AG_NOC 6
|
||||
|
||||
#define MASTER_LLCC 0
|
||||
#define SLAVE_EBI1 1
|
||||
#define MASTER_LLCC_DISP 2
|
||||
#define SLAVE_EBI1_DISP 3
|
||||
|
||||
#define MASTER_CAMNOC_HF 0
|
||||
#define MASTER_CAMNOC_ICP 1
|
||||
#define MASTER_CAMNOC_SF 2
|
||||
#define MASTER_CNOC_MNOC_CFG 3
|
||||
#define MASTER_VIDEO_P0 4
|
||||
#define MASTER_VIDEO_P1 5
|
||||
#define MASTER_VIDEO_PROC 6
|
||||
#define MASTER_MDP0 7
|
||||
#define MASTER_MDP1 8
|
||||
#define MASTER_ROTATOR 9
|
||||
#define SLAVE_MNOC_HF_MEM_NOC 10
|
||||
#define SLAVE_MNOC_SF_MEM_NOC 11
|
||||
#define SLAVE_SERVICE_MNOC 12
|
||||
#define MASTER_MDP0_DISP 13
|
||||
#define MASTER_MDP1_DISP 14
|
||||
#define MASTER_ROTATOR_DISP 15
|
||||
#define SLAVE_MNOC_HF_MEM_NOC_DISP 16
|
||||
#define SLAVE_MNOC_SF_MEM_NOC_DISP 17
|
||||
|
||||
#define MASTER_CDSP_NOC_CFG 0
|
||||
#define MASTER_CDSP_PROC 1
|
||||
#define SLAVE_CDSP_MEM_NOC 2
|
||||
#define SLAVE_SERVICE_NSP_NOC 3
|
||||
|
||||
#define MASTER_A1NOC_SNOC 0
|
||||
#define MASTER_A2NOC_SNOC 1
|
||||
#define MASTER_SNOC_CFG 2
|
||||
#define MASTER_PIMEM 3
|
||||
#define MASTER_GIC 4
|
||||
#define SLAVE_SNOC_GEM_NOC_GC 5
|
||||
#define SLAVE_SNOC_GEM_NOC_SF 6
|
||||
#define SLAVE_SERVICE_SNOC 7
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user