powerpc/dma: use the dma_direct mapping routines
Switch the streaming DMA mapping and ownership transfer methods to the functionally identical dma_direct_ versions. Factor the cache maintainance helpers into the form expected by the common code for that. Signed-off-by: Christoph Hellwig <hch@lst.de> Tested-by: Christian Zigotzky <chzigotzky@xenosoft.de> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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@ -25,36 +25,6 @@ extern void *__dma_nommu_alloc_coherent(struct device *dev, size_t size,
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extern void __dma_nommu_free_coherent(struct device *dev, size_t size,
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void *vaddr, dma_addr_t dma_handle,
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unsigned long attrs);
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int dma_nommu_map_sg(struct device *dev, struct scatterlist *sgl,
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int nents, enum dma_data_direction direction,
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unsigned long attrs);
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dma_addr_t dma_nommu_map_page(struct device *dev, struct page *page,
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unsigned long offset, size_t size,
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enum dma_data_direction dir, unsigned long attrs);
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#ifdef CONFIG_NOT_COHERENT_CACHE
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/*
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* DMA-consistent mapping functions for PowerPCs that don't support
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* cache snooping. These allocate/free a region of uncached mapped
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* memory space for use with DMA devices. Alternatively, you could
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* allocate the space "normally" and use the cache management functions
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* to ensure it is consistent.
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*/
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struct device;
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extern void __dma_sync(void *vaddr, size_t size, int direction);
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extern void __dma_sync_page(struct page *page, unsigned long offset,
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size_t size, int direction);
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extern unsigned long __dma_get_coherent_pfn(unsigned long cpu_addr);
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#else /* ! CONFIG_NOT_COHERENT_CACHE */
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/*
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* Cache coherent cores.
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*/
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#define __dma_sync(addr, size, rw) ((void)0)
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#define __dma_sync_page(pg, off, sz, rw) ((void)0)
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#endif /* ! CONFIG_NOT_COHERENT_CACHE */
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static inline unsigned long device_to_mask(struct device *dev)
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{
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@ -68,7 +68,7 @@ static dma_addr_t dma_iommu_map_page(struct device *dev, struct page *page,
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unsigned long attrs)
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{
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if (dma_iommu_map_bypass(dev, attrs))
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return dma_nommu_map_page(dev, page, offset, size, direction,
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return dma_direct_map_page(dev, page, offset, size, direction,
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attrs);
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return iommu_map_page(dev, get_iommu_table_base(dev), page, offset,
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size, device_to_mask(dev), direction, attrs);
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@ -90,7 +90,7 @@ static int dma_iommu_map_sg(struct device *dev, struct scatterlist *sglist,
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unsigned long attrs)
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{
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if (dma_iommu_map_bypass(dev, attrs))
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return dma_nommu_map_sg(dev, sglist, nelems, direction, attrs);
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return dma_direct_map_sg(dev, sglist, nelems, direction, attrs);
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return ppc_iommu_map_sg(dev, get_iommu_table_base(dev), sglist, nelems,
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device_to_mask(dev), direction, attrs);
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}
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@ -27,77 +27,6 @@
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* default the offset is PCI_DRAM_OFFSET.
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*/
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int dma_nommu_map_sg(struct device *dev, struct scatterlist *sgl,
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int nents, enum dma_data_direction direction,
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unsigned long attrs)
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{
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struct scatterlist *sg;
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int i;
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for_each_sg(sgl, sg, nents, i) {
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sg->dma_address = phys_to_dma(dev, sg_phys(sg));
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sg->dma_length = sg->length;
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if (attrs & DMA_ATTR_SKIP_CPU_SYNC)
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continue;
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__dma_sync_page(sg_page(sg), sg->offset, sg->length, direction);
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}
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return nents;
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}
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static void dma_nommu_unmap_sg(struct device *dev, struct scatterlist *sgl,
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int nents, enum dma_data_direction direction,
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unsigned long attrs)
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{
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struct scatterlist *sg;
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int i;
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for_each_sg(sgl, sg, nents, i)
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__dma_sync_page(sg_page(sg), sg->offset, sg->length, direction);
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}
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dma_addr_t dma_nommu_map_page(struct device *dev, struct page *page,
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unsigned long offset, size_t size,
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enum dma_data_direction dir, unsigned long attrs)
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{
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if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
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__dma_sync_page(page, offset, size, dir);
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return phys_to_dma(dev, page_to_phys(page)) + offset;
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}
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static inline void dma_nommu_unmap_page(struct device *dev,
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dma_addr_t dma_address,
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size_t size,
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enum dma_data_direction direction,
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unsigned long attrs)
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{
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if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
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__dma_sync(bus_to_virt(dma_address), size, direction);
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}
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#ifdef CONFIG_NOT_COHERENT_CACHE
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static inline void dma_nommu_sync_sg(struct device *dev,
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struct scatterlist *sgl, int nents,
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enum dma_data_direction direction)
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{
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struct scatterlist *sg;
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int i;
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for_each_sg(sgl, sg, nents, i)
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__dma_sync_page(sg_page(sg), sg->offset, sg->length, direction);
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}
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static inline void dma_nommu_sync_single(struct device *dev,
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dma_addr_t dma_handle, size_t size,
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enum dma_data_direction direction)
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{
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__dma_sync(bus_to_virt(dma_handle), size, direction);
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}
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#endif
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const struct dma_map_ops dma_nommu_ops = {
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#ifdef CONFIG_NOT_COHERENT_CACHE
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.alloc = __dma_nommu_alloc_coherent,
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@ -106,17 +35,17 @@ const struct dma_map_ops dma_nommu_ops = {
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.alloc = dma_direct_alloc,
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.free = dma_direct_free,
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#endif
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.map_sg = dma_nommu_map_sg,
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.unmap_sg = dma_nommu_unmap_sg,
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.map_sg = dma_direct_map_sg,
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.dma_supported = dma_direct_supported,
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.map_page = dma_nommu_map_page,
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.unmap_page = dma_nommu_unmap_page,
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.map_page = dma_direct_map_page,
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.get_required_mask = dma_direct_get_required_mask,
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#ifdef CONFIG_NOT_COHERENT_CACHE
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.sync_single_for_cpu = dma_nommu_sync_single,
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.sync_single_for_device = dma_nommu_sync_single,
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.sync_sg_for_cpu = dma_nommu_sync_sg,
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.sync_sg_for_device = dma_nommu_sync_sg,
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.unmap_sg = dma_direct_unmap_sg,
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.unmap_page = dma_direct_unmap_page,
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.sync_single_for_cpu = dma_direct_sync_single_for_cpu,
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.sync_single_for_device = dma_direct_sync_single_for_device,
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.sync_sg_for_cpu = dma_direct_sync_sg_for_cpu,
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.sync_sg_for_device = dma_direct_sync_sg_for_device,
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#endif
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};
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EXPORT_SYMBOL(dma_nommu_ops);
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@ -314,7 +314,7 @@ void __dma_nommu_free_coherent(struct device *dev, size_t size, void *vaddr,
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/*
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* make an area consistent.
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*/
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void __dma_sync(void *vaddr, size_t size, int direction)
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static void __dma_sync(void *vaddr, size_t size, int direction)
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{
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unsigned long start = (unsigned long)vaddr;
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unsigned long end = start + size;
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@ -340,7 +340,6 @@ void __dma_sync(void *vaddr, size_t size, int direction)
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break;
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}
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}
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EXPORT_SYMBOL(__dma_sync);
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#ifdef CONFIG_HIGHMEM
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/*
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@ -387,21 +386,33 @@ static inline void __dma_sync_page_highmem(struct page *page,
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* __dma_sync_page makes memory consistent. identical to __dma_sync, but
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* takes a struct page instead of a virtual address
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*/
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void __dma_sync_page(struct page *page, unsigned long offset,
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size_t size, int direction)
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static void __dma_sync_page(phys_addr_t paddr, size_t size, int dir)
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{
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struct page *page = pfn_to_page(paddr >> PAGE_SHIFT);
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unsigned offset = paddr & ~PAGE_MASK;
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#ifdef CONFIG_HIGHMEM
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__dma_sync_page_highmem(page, offset, size, direction);
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__dma_sync_page_highmem(page, offset, size, dir);
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#else
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unsigned long start = (unsigned long)page_address(page) + offset;
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__dma_sync((void *)start, size, direction);
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__dma_sync((void *)start, size, dir);
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#endif
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}
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EXPORT_SYMBOL(__dma_sync_page);
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void arch_sync_dma_for_device(struct device *dev, phys_addr_t paddr,
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size_t size, enum dma_data_direction dir)
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{
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__dma_sync_page(paddr, size, dir);
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}
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void arch_sync_dma_for_cpu(struct device *dev, phys_addr_t paddr,
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size_t size, enum dma_data_direction dir)
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{
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__dma_sync_page(paddr, size, dir);
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}
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/*
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* Return the PFN for a given cpu virtual address returned by
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* __dma_nommu_alloc_coherent.
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* Return the PFN for a given cpu virtual address returned by arch_dma_alloc.
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*/
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long arch_dma_coherent_to_pfn(struct device *dev, void *vaddr,
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dma_addr_t dma_addr)
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@ -403,6 +403,8 @@ config NOT_COHERENT_CACHE
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depends on 4xx || PPC_8xx || E200 || PPC_MPC512x || \
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GAMECUBE_COMMON || AMIGAONE
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select ARCH_HAS_DMA_COHERENT_TO_PFN
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select ARCH_HAS_SYNC_DMA_FOR_DEVICE
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select ARCH_HAS_SYNC_DMA_FOR_CPU
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default n if PPC_47x
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default y
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