iommu/vt-d: Support cpumask for IOMMU perfmon
The perf subsystem assumes that all counters are by default per-CPU. So the user space tool reads a counter from each CPU. However, the IOMMU counters are system-wide and can be read from any CPU. Here we use a CPU mask to restrict counting to one CPU to handle the issue. (with CPU hotplug notifier to choose a different CPU if the chosen one is taken off-line). The CPU is exposed to /sys/bus/event_source/devices/dmar*/cpumask for the user space perf tool. Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Link: https://lore.kernel.org/r/20230128200428.1459118-6-kan.liang@linux.intel.com Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
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@ -27,3 +27,11 @@ Description: Read-only. Attribute group to describe the magic bits
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filter_pasid = "config2:0-21" - PASID filter
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filter_ats = "config2:24-28" - Address Type filter
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filter_page_table = "config2:32-36" - Page Table Level filter
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What: /sys/bus/event_source/devices/dmar*/cpumask
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Date: Jan 2023
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KernelVersion: 6.3
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Contact: Kan Liang <kan.liang@linux.intel.com>
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Description: Read-only. This file always returns the CPU to which the
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IOMMU pmu is bound for access to all IOMMU pmu performance
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monitoring events.
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@ -34,9 +34,28 @@ static struct attribute_group iommu_pmu_events_attr_group = {
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.attrs = attrs_empty,
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};
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static cpumask_t iommu_pmu_cpu_mask;
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static ssize_t
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cpumask_show(struct device *dev, struct device_attribute *attr, char *buf)
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{
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return cpumap_print_to_pagebuf(true, buf, &iommu_pmu_cpu_mask);
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}
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static DEVICE_ATTR_RO(cpumask);
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static struct attribute *iommu_pmu_cpumask_attrs[] = {
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&dev_attr_cpumask.attr,
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NULL
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};
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static struct attribute_group iommu_pmu_cpumask_attr_group = {
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.attrs = iommu_pmu_cpumask_attrs,
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};
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static const struct attribute_group *iommu_pmu_attr_groups[] = {
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&iommu_pmu_format_attr_group,
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&iommu_pmu_events_attr_group,
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&iommu_pmu_cpumask_attr_group,
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NULL
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};
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@ -679,20 +698,98 @@ void free_iommu_pmu(struct intel_iommu *iommu)
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iommu->pmu = NULL;
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}
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void iommu_pmu_register(struct intel_iommu *iommu)
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static int iommu_pmu_cpu_online(unsigned int cpu)
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{
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if (!iommu->pmu)
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if (cpumask_empty(&iommu_pmu_cpu_mask))
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cpumask_set_cpu(cpu, &iommu_pmu_cpu_mask);
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return 0;
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}
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static int iommu_pmu_cpu_offline(unsigned int cpu)
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{
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struct dmar_drhd_unit *drhd;
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struct intel_iommu *iommu;
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int target;
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if (!cpumask_test_and_clear_cpu(cpu, &iommu_pmu_cpu_mask))
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return 0;
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target = cpumask_any_but(cpu_online_mask, cpu);
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if (target < nr_cpu_ids)
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cpumask_set_cpu(target, &iommu_pmu_cpu_mask);
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else
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target = -1;
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rcu_read_lock();
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for_each_iommu(iommu, drhd) {
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if (!iommu->pmu)
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continue;
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perf_pmu_migrate_context(&iommu->pmu->pmu, cpu, target);
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}
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rcu_read_unlock();
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return 0;
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}
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static int nr_iommu_pmu;
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static int iommu_pmu_cpuhp_setup(struct iommu_pmu *iommu_pmu)
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{
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int ret;
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if (nr_iommu_pmu++)
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return 0;
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ret = cpuhp_setup_state(CPUHP_AP_PERF_X86_IOMMU_PERF_ONLINE,
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"driver/iommu/intel/perfmon:online",
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iommu_pmu_cpu_online,
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iommu_pmu_cpu_offline);
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if (ret)
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nr_iommu_pmu = 0;
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return ret;
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}
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static void iommu_pmu_cpuhp_free(struct iommu_pmu *iommu_pmu)
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{
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if (--nr_iommu_pmu)
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return;
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if (__iommu_pmu_register(iommu)) {
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pr_err("Failed to register PMU for iommu (seq_id = %d)\n",
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iommu->seq_id);
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free_iommu_pmu(iommu);
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}
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cpuhp_remove_state(CPUHP_AP_PERF_X86_IOMMU_PERF_ONLINE);
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}
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void iommu_pmu_register(struct intel_iommu *iommu)
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{
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struct iommu_pmu *iommu_pmu = iommu->pmu;
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if (!iommu_pmu)
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return;
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if (__iommu_pmu_register(iommu))
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goto err;
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if (iommu_pmu_cpuhp_setup(iommu_pmu))
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goto unregister;
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return;
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unregister:
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perf_pmu_unregister(&iommu_pmu->pmu);
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err:
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pr_err("Failed to register PMU for iommu (seq_id = %d)\n", iommu->seq_id);
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free_iommu_pmu(iommu);
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}
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void iommu_pmu_unregister(struct intel_iommu *iommu)
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{
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if (iommu->pmu)
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perf_pmu_unregister(&iommu->pmu->pmu);
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struct iommu_pmu *iommu_pmu = iommu->pmu;
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if (!iommu_pmu)
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return;
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iommu_pmu_cpuhp_free(iommu_pmu);
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perf_pmu_unregister(&iommu_pmu->pmu);
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}
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@ -221,6 +221,7 @@ enum cpuhp_state {
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CPUHP_AP_PERF_X86_CQM_ONLINE,
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CPUHP_AP_PERF_X86_CSTATE_ONLINE,
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CPUHP_AP_PERF_X86_IDXD_ONLINE,
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CPUHP_AP_PERF_X86_IOMMU_PERF_ONLINE,
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CPUHP_AP_PERF_S390_CF_ONLINE,
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CPUHP_AP_PERF_S390_SF_ONLINE,
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CPUHP_AP_PERF_ARM_CCI_ONLINE,
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