ARM: OMAP2+: onenand: refactor for clarity
Refactor set_async_mode & set_sync_mode functions to separate out timing calculation & actual configuration (GPMC & OneNAND side). Thanks to Jon for his suggestions. Signed-off-by: Afzal Mohammed <afzal@ti.com> Reviewed-by: Jon Hunter <jon-hunter@ti.com>
This commit is contained in:
Afzal Mohammed
parent
2e618261c9
commit
46376884ce
@ -16,6 +16,7 @@
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#include <linux/mtd/onenand_regs.h>
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#include <linux/io.h>
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#include <linux/platform_data/mtd-onenand-omap2.h>
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#include <linux/err.h>
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#include <asm/mach/flash.h>
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@ -25,6 +26,15 @@
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#define ONENAND_IO_SIZE SZ_128K
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#define ONENAND_FLAG_SYNCREAD (1 << 0)
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#define ONENAND_FLAG_SYNCWRITE (1 << 1)
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#define ONENAND_FLAG_HF (1 << 2)
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#define ONENAND_FLAG_VHF (1 << 3)
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static unsigned onenand_flags;
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static unsigned latency;
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static int fclk_offset;
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static struct omap_onenand_platform_data *gpmc_onenand_data;
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static struct resource gpmc_onenand_resource = {
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@ -38,11 +48,9 @@ static struct platform_device gpmc_onenand_device = {
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.resource = &gpmc_onenand_resource,
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};
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static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
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static struct gpmc_timings omap2_onenand_calc_async_timings(void)
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{
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struct gpmc_timings t;
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u32 reg;
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int err;
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const int t_cer = 15;
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const int t_avdp = 12;
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@ -55,11 +63,6 @@ static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
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const int t_wpl = 40;
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const int t_wph = 30;
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/* Ensure sync read and sync write are disabled */
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reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
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reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE;
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writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
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memset(&t, 0, sizeof(t));
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t.sync_clk = 0;
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t.cs_on = 0;
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@ -86,25 +89,30 @@ static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
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t.cs_wr_off = t.we_off + gpmc_round_ns_to_ticks(t_wph);
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t.wr_cycle = t.cs_wr_off + gpmc_round_ns_to_ticks(t_cez);
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return t;
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}
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static int gpmc_set_async_mode(int cs, struct gpmc_timings *t)
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{
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/* Configure GPMC for asynchronous read */
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gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1,
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GPMC_CONFIG1_DEVICESIZE_16 |
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GPMC_CONFIG1_MUXADDDATA);
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err = gpmc_cs_set_timings(cs, &t);
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if (err)
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return err;
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return gpmc_cs_set_timings(cs, t);
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}
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static void omap2_onenand_set_async_mode(void __iomem *onenand_base)
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{
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u32 reg;
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/* Ensure sync read and sync write are disabled */
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reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
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reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE;
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writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
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return 0;
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}
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static void set_onenand_cfg(void __iomem *onenand_base, int latency,
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int sync_read, int sync_write, int hf, int vhf)
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static void set_onenand_cfg(void __iomem *onenand_base)
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{
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u32 reg;
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@ -112,19 +120,19 @@ static void set_onenand_cfg(void __iomem *onenand_base, int latency,
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reg &= ~((0x7 << ONENAND_SYS_CFG1_BRL_SHIFT) | (0x7 << 9));
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reg |= (latency << ONENAND_SYS_CFG1_BRL_SHIFT) |
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ONENAND_SYS_CFG1_BL_16;
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if (sync_read)
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if (onenand_flags & ONENAND_FLAG_SYNCREAD)
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reg |= ONENAND_SYS_CFG1_SYNC_READ;
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else
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reg &= ~ONENAND_SYS_CFG1_SYNC_READ;
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if (sync_write)
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if (onenand_flags & ONENAND_FLAG_SYNCWRITE)
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reg |= ONENAND_SYS_CFG1_SYNC_WRITE;
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else
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reg &= ~ONENAND_SYS_CFG1_SYNC_WRITE;
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if (hf)
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if (onenand_flags & ONENAND_FLAG_HF)
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reg |= ONENAND_SYS_CFG1_HF;
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else
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reg &= ~ONENAND_SYS_CFG1_HF;
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if (vhf)
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if (onenand_flags & ONENAND_FLAG_VHF)
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reg |= ONENAND_SYS_CFG1_VHF;
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else
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reg &= ~ONENAND_SYS_CFG1_VHF;
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@ -172,9 +180,9 @@ static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg,
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return freq;
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}
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static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
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void __iomem *onenand_base,
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int *freq_ptr)
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static struct gpmc_timings
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omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg,
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int freq, bool clk_dep)
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{
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struct gpmc_timings t;
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const int t_cer = 15;
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@ -184,29 +192,15 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
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const int t_wpl = 40;
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const int t_wph = 30;
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int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
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int div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency;
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int first_time = 0, hf = 0, vhf = 0, sync_read = 0, sync_write = 0;
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int err, ticks_cez;
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int cs = cfg->cs, freq = *freq_ptr;
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u32 reg;
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bool clk_dep = false;
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int div, fclk_offset_ns, gpmc_clk_ns;
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int ticks_cez;
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int cs = cfg->cs;
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if (cfg->flags & ONENAND_SYNC_READ) {
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sync_read = 1;
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} else if (cfg->flags & ONENAND_SYNC_READWRITE) {
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sync_read = 1;
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sync_write = 1;
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} else
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return omap2_onenand_set_async_mode(cs, onenand_base);
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if (!freq) {
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/* Very first call freq is not known */
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err = omap2_onenand_set_async_mode(cs, onenand_base);
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if (err)
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return err;
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freq = omap2_onenand_get_freq(cfg, onenand_base, &clk_dep);
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first_time = 1;
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}
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if (cfg->flags & ONENAND_SYNC_READ)
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onenand_flags = ONENAND_FLAG_SYNCREAD;
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else if (cfg->flags & ONENAND_SYNC_READWRITE)
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onenand_flags = ONENAND_FLAG_SYNCREAD | ONENAND_FLAG_SYNCWRITE;
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switch (freq) {
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case 104:
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@ -244,19 +238,23 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
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t_ach = 9;
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t_aavdh = 7;
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t_rdyo = 15;
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sync_write = 0;
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onenand_flags &= ~ONENAND_FLAG_SYNCWRITE;
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break;
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}
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div = gpmc_cs_calc_divider(cs, min_gpmc_clk_period);
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gpmc_clk_ns = gpmc_ticks_to_ns(div);
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if (gpmc_clk_ns < 15) /* >66Mhz */
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hf = 1;
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onenand_flags |= ONENAND_FLAG_HF;
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else
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onenand_flags &= ~ONENAND_FLAG_HF;
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if (gpmc_clk_ns < 12) /* >83Mhz */
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vhf = 1;
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if (vhf)
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onenand_flags |= ONENAND_FLAG_VHF;
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else
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onenand_flags &= ~ONENAND_FLAG_VHF;
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if (onenand_flags & ONENAND_FLAG_VHF)
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latency = 8;
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else if (hf)
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else if (onenand_flags & ONENAND_FLAG_HF)
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latency = 6;
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else if (gpmc_clk_ns >= 25) /* 40 MHz*/
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latency = 3;
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@ -279,9 +277,8 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
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}
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}
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if (first_time)
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set_onenand_cfg(onenand_base, latency,
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sync_read, sync_write, hf, vhf);
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/* Set synchronous read timings */
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memset(&t, 0, sizeof(t));
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if (div == 1) {
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reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2);
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@ -307,8 +304,6 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
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gpmc_cs_write_reg(cs, GPMC_CS_CONFIG4, reg);
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}
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/* Set synchronous read timings */
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memset(&t, 0, sizeof(t));
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t.sync_clk = min_gpmc_clk_period;
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t.cs_on = 0;
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t.adv_on = 0;
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@ -330,7 +325,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
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ticks_cez);
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/* Write */
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if (sync_write) {
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if (onenand_flags & ONENAND_FLAG_SYNCWRITE) {
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t.adv_wr_off = t.adv_rd_off;
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t.we_on = 0;
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t.we_off = t.cs_rd_off;
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@ -355,6 +350,14 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
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}
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}
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return t;
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}
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static int gpmc_set_sync_mode(int cs, struct gpmc_timings *t)
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{
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unsigned sync_read = onenand_flags & ONENAND_FLAG_SYNCREAD;
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unsigned sync_write = onenand_flags & ONENAND_FLAG_SYNCWRITE;
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/* Configure GPMC for synchronous read */
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gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1,
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GPMC_CONFIG1_WRAPBURST_SUPP |
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@ -371,11 +374,47 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
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GPMC_CONFIG1_DEVICETYPE_NOR |
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GPMC_CONFIG1_MUXADDDATA);
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err = gpmc_cs_set_timings(cs, &t);
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if (err)
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return err;
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return gpmc_cs_set_timings(cs, t);
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}
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set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf, vhf);
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static int omap2_onenand_setup_async(void __iomem *onenand_base)
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{
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struct gpmc_timings t;
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int ret;
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omap2_onenand_set_async_mode(onenand_base);
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t = omap2_onenand_calc_async_timings();
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ret = gpmc_set_async_mode(gpmc_onenand_data->cs, &t);
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if (IS_ERR_VALUE(ret))
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return ret;
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omap2_onenand_set_async_mode(onenand_base);
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return 0;
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}
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static int omap2_onenand_setup_sync(void __iomem *onenand_base, int *freq_ptr)
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{
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int ret, freq = *freq_ptr;
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struct gpmc_timings t;
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bool clk_dep = false;
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if (!freq) {
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/* Very first call freq is not known */
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freq = omap2_onenand_get_freq(gpmc_onenand_data,
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onenand_base, &clk_dep);
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set_onenand_cfg(onenand_base);
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}
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t = omap2_onenand_calc_sync_timings(gpmc_onenand_data, freq, clk_dep);
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ret = gpmc_set_sync_mode(gpmc_onenand_data->cs, &t);
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if (IS_ERR_VALUE(ret))
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return ret;
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set_onenand_cfg(onenand_base);
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*freq_ptr = freq;
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@ -385,15 +424,22 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
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static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
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{
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struct device *dev = &gpmc_onenand_device.dev;
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unsigned l = ONENAND_SYNC_READ | ONENAND_SYNC_READWRITE;
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int ret;
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/* Set sync timings in GPMC */
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if (omap2_onenand_set_sync_mode(gpmc_onenand_data, onenand_base,
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freq_ptr) < 0) {
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dev_err(dev, "Unable to set synchronous mode\n");
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return -EINVAL;
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ret = omap2_onenand_setup_async(onenand_base);
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if (ret) {
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dev_err(dev, "unable to set to async mode\n");
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return ret;
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}
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return 0;
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if (!(gpmc_onenand_data->flags & l))
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return 0;
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ret = omap2_onenand_setup_sync(onenand_base, freq_ptr);
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if (ret)
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dev_err(dev, "unable to set to sync mode\n");
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return ret;
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}
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void __init gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
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