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media: hantro: HEVC: unconditionnaly set pps_{cb/cr}_qp_offset values

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Always set pps_cb_qp_offset and pps_cr_qp_offset values in Hantro/G2
register whatever is V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT
flag value.
The vendor code does the same to set these values.
This fixes conformance test CAINIT_G_SHARP_3.

Fluster HEVC score is increase by one with this patch.

Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
This commit is contained in:
Benjamin Gaignard 2022-05-03 17:19:20 +02:00 committed by Mauro Carvalho Chehab
parent 387d117695
commit 46c8365691
1 changed files with 2 additions and 7 deletions
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9
drivers/staging/media/hantro/hantro_g2_hevc_dec.c
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@ -194,13 +194,8 @@ static void set_params(struct hantro_ctx *ctx)
hantro_reg_write(vpu, &g2_max_cu_qpd_depth, 0);
}
if (pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT) {
hantro_reg_write(vpu, &g2_cb_qp_offset, pps->pps_cb_qp_offset);
hantro_reg_write(vpu, &g2_cr_qp_offset, pps->pps_cr_qp_offset);
} else {
hantro_reg_write(vpu, &g2_cb_qp_offset, 0);
hantro_reg_write(vpu, &g2_cr_qp_offset, 0);
}
hantro_reg_write(vpu, &g2_cb_qp_offset, pps->pps_cb_qp_offset);
hantro_reg_write(vpu, &g2_cr_qp_offset, pps->pps_cr_qp_offset);
hantro_reg_write(vpu, &g2_filt_offset_beta, pps->pps_beta_offset_div2);
hantro_reg_write(vpu, &g2_filt_offset_tc, pps->pps_tc_offset_div2);