Merge branch 'pci/aer'
- Mask reporting of Mask Replay Timer Timeout Correctable Errors in the bridge above Genesys GL975x SD host controllers; the errors are caused by a GL975x hardware defect and they may lead to AER interrupts that prevent system suspend (Kai-Heng Feng) - Update URL of aer-inject tool (Kuppuswamy Sathyanarayanan) * pci/aer: PCI/AER: Update aer-inject tool source URL PCI: Mask Replay Timer Timeout errors for Genesys GL975x SD host controller
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@ -241,7 +241,7 @@ After reboot with new kernel or insert the module, a device file named
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Then, you need a user space tool named aer-inject, which can be gotten
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from:
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https://git.kernel.org/cgit/linux/kernel/git/gong.chen/aer-inject.git/
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https://github.com/intel/aer-inject.git
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More information about aer-inject can be found in the document in
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its source code.
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@ -47,7 +47,7 @@ config PCIEAER_INJECT
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error injection can fake almost all kinds of errors with the
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help of a user space helper tool aer-inject, which can be
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gotten from:
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https://git.kernel.org/cgit/linux/kernel/git/gong.chen/aer-inject.git/
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https://github.com/intel/aer-inject.git
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config PCIEAER_CXL
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bool "PCI Express CXL RAS support"
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@ -6,7 +6,7 @@
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* trigger various real hardware errors. Software based error
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* injection can fake almost all kinds of errors with the help of a
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* user space helper tool aer-inject, which can be gotten from:
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* https://git.kernel.org/cgit/linux/kernel/git/gong.chen/aer-inject.git/
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* https://github.com/intel/aer-inject.git
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*
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* Copyright 2009 Intel Corporation.
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* Huang Ying <ying.huang@intel.com>
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@ -6261,3 +6261,23 @@ static void pci_fixup_d3cold_delay_1sec(struct pci_dev *pdev)
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pdev->d3cold_delay = 1000;
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}
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DECLARE_PCI_FIXUP_FINAL(0x5555, 0x0004, pci_fixup_d3cold_delay_1sec);
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#ifdef CONFIG_PCIEAER
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static void pci_mask_replay_timer_timeout(struct pci_dev *pdev)
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{
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struct pci_dev *parent = pci_upstream_bridge(pdev);
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u32 val;
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if (!parent || !parent->aer_cap)
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return;
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pci_info(parent, "mask Replay Timer Timeout Correctable Errors due to %s hardware defect",
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pci_name(pdev));
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pci_read_config_dword(parent, parent->aer_cap + PCI_ERR_COR_MASK, &val);
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val |= PCI_ERR_COR_REP_TIMER;
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pci_write_config_dword(parent, parent->aer_cap + PCI_ERR_COR_MASK, val);
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}
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9750, pci_mask_replay_timer_timeout);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9755, pci_mask_replay_timer_timeout);
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#endif
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