dt-bindings: Fix typos
Fix typos in Documentation/devicetree/bindings. The changes are in descriptions or comments where they shouldn't affect functionality. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://lore.kernel.org/r/20230814212822.193684-3-helgaas@kernel.org Signed-off-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Bjorn Helgaas
Rob Herring
parent
de259b7bd6
commit
47aab53331
@ -1222,9 +1222,9 @@ properties:
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- description:
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Freescale Vybrid Platform Device Tree Bindings
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For the Vybrid SoC familiy all variants with DDR controller are supported,
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For the Vybrid SoC family all variants with DDR controller are supported,
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which is the VF5xx and VF6xx series. Out of historical reasons, in most
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places the kernel uses vf610 to refer to the whole familiy.
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places the kernel uses vf610 to refer to the whole family.
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The compatible string "fsl,vf610m4" is used for the secondary Cortex-M4
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core support.
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items:
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@ -21,13 +21,13 @@ The Device Tree node representing this System Controller 0 provides a
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number of clocks:
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- a set of core clocks
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- a set of gatable clocks
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- a set of gateable clocks
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Those clocks can be referenced by other Device Tree nodes using two
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cells:
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- The first cell must be 0 or 1. 0 for the core clocks and 1 for the
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gatable clocks.
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- The second cell identifies the particular core clock or gatable
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gateable clocks.
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- The second cell identifies the particular core clock or gateable
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clocks.
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The following clocks are available:
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@ -38,7 +38,7 @@ The following clocks are available:
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- 0 3 Core
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- 0 4 NAND core
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- 0 5 SDIO core
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- Gatable clocks
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- Gateable clocks
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- 1 0 Audio
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- 1 1 Comm Unit
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- 1 2 NAND
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@ -16,7 +16,7 @@ The available clocks are defined in dt-bindings/clock/mt*-clk.h.
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The mipi0a controller also uses the common power domain from
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Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
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The available power doamins are defined in dt-bindings/power/mt*-power.h.
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The available power domains are defined in dt-bindings/power/mt*-power.h.
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Example:
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@ -15,7 +15,7 @@ The available clocks are defined in dt-bindings/clock/mt*-clk.h.
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The vcodecsys controller also uses the common power domain from
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Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
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The available power doamins are defined in dt-bindings/power/mt*-power.h.
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The available power domains are defined in dt-bindings/power/mt*-power.h.
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Example:
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@ -541,13 +541,13 @@ properties:
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- const: msi,primo81
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- const: allwinner,sun6i-a31s
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- description: Emlid Neutis N5 Developper Board
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- description: Emlid Neutis N5 Developer Board
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items:
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- const: emlid,neutis-n5-devboard
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- const: emlid,neutis-n5
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- const: allwinner,sun50i-h5
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- description: Emlid Neutis N5H3 Developper Board
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- description: Emlid Neutis N5H3 Developer Board
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items:
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- const: emlid,neutis-n5h3-devboard
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- const: emlid,neutis-n5h3
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@ -12,7 +12,7 @@ maintainers:
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description: |
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This document defines device tree properties common to most Parallel
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ATA (PATA, also known as IDE) AT attachment storage devices.
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It doesn't constitue a device tree binding specification by itself but is
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It doesn't constitute a device tree binding specification by itself but is
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meant to be referenced by device tree bindings.
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The PATA (IDE) controller-specific device tree bindings are responsible for
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@ -43,7 +43,7 @@ properties:
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brcm,gisb-arb-master-names:
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$ref: /schemas/types.yaml#/definitions/string-array
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description: >
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String list of the litteral name of the GISB masters. Should match the
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String list of the literal name of the GISB masters. Should match the
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number of bits set in brcm,gisb-master-mask and the order in which they
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appear from MSB to LSB.
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@ -7,10 +7,10 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NVIDIA Tegra ACONNECT Bus
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description: |
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The Tegra ACONNECT bus is an AXI switch which is used to connnect various
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The Tegra ACONNECT bus is an AXI switch which is used to connect various
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components inside the Audio Processing Engine (APE). All CPU accesses to
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the APE subsystem go through the ACONNECT via an APB to AXI wrapper. All
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devices accessed via the ACONNNECT are described by child-nodes.
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devices accessed via the ACONNECT are described by child-nodes.
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maintainers:
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- Jon Hunter <jonathanh@nvidia.com>
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@ -4,7 +4,7 @@
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$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-osc-clk.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Allwinner A10 Gatable Oscillator Clock
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title: Allwinner A10 Gateable Oscillator Clock
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maintainers:
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- Chen-Yu Tsai <wens@csie.org>
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@ -1,7 +1,7 @@
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Alphascale Clock Controller
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The ACC (Alphascale Clock Controller) is responsible of choising proper
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clock source, setting deviders and clock gates.
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The ACC (Alphascale Clock Controller) is responsible for choosing proper
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clock source, setting dividers and clock gates.
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Required properties for the ACC node:
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- compatible: must be "alphascale,asm9260-clock-controller"
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@ -14,7 +14,7 @@ Required properties:
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- #clock-cells : from common clock binding; shall be set to 0.
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- compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"
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- clocks : parent clock phandle
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- reg - pll control0 and pll multipler registers
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- reg - pll control0 and pll multiplier registers
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- reg-names : control, multiplier and post-divider. The multiplier and
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post-divider registers are applicable only for main pll clock
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- fixed-postdiv : fixed post divider value. If absent, use clkod register bits
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@ -68,7 +68,7 @@ soc {
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"base_ssp0_clk", "base_sdio_clk";
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};
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/* A user of CCU brach clocks */
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/* A user of CCU branch clocks */
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uart1: serial@40082000 {
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...
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clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>;
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@ -5,8 +5,8 @@ control registers for two low speed clocks. One of the clocks is a
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32 kHz oscillator driver with power up/down and clock gating. Next
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is a fixed divider that creates a 1 kHz clock from the 32 kHz osc.
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These clocks are used by the RTC and the Event Router peripherials.
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The 32 kHz can also be routed to other peripherials to enable low
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These clocks are used by the RTC and the Event Router peripherals.
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The 32 kHz can also be routed to other peripherals to enable low
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power modes.
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This binding uses the common clock binding:
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@ -12,7 +12,7 @@ requests.
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Required properties:
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- compatible: "maxim,max9485"
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- clocks: Input clock, must provice 27.000 MHz
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- clocks: Input clock, must provide 27.000 MHz
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- clock-names: Must be set to "xclk"
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- #clock-cells: From common clock binding; shall be set to 1
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@ -25,7 +25,7 @@ properties:
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- description: Sleep clock source
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- description: PCIE 0 Pipe clock source (Optional clock)
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- description: PCIE 1 Pipe clock source (Optional clock)
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- description: PCIE 1 Phy Auxillary clock source (Optional clock)
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- description: PCIE 1 Phy Auxiliary clock source (Optional clock)
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- description: UFS Phy Rx symbol 0 clock source (Optional clock)
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- description: UFS Phy Rx symbol 1 clock source (Optional clock)
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- description: UFS Phy Tx symbol 0 clock source (Optional clock)
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@ -14,7 +14,7 @@ description:
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There is one ACC register region per CPU within the KPSS remapped region as
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well as an alias register region that remaps accesses to the ACC associated
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with the CPU accessing the region. ACC v1 is currently used as a
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clock-controller for enabling the cpu and hanling the aux clocks.
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clock-controller for enabling the cpu and handling the aux clocks.
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properties:
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compatible:
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@ -66,7 +66,7 @@ then:
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else:
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description: |
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Other SC9863a clock nodes should be the child of a syscon node in
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which compatible string shoule be:
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which compatible string should be:
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"sprd,sc9863a-glbregs", "syscon", "simple-mfd"
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The 'reg' property for the clock node is also required if there is a sub
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@ -8,7 +8,7 @@ parents, one of which can be selected as output. This clock does not
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gate or adjust the parent rate via a divider or multiplier.
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By default the "clocks" property lists the parents in the same order
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as they are programmed into the regster. E.g:
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as they are programmed into the register. E.g:
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clocks = <&foo_clock>, <&bar_clock>, <&baz_clock>;
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@ -9,7 +9,7 @@ Optional properties:
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- clocks: list of clock identifiers which are external input clocks to the
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given clock controller. Please refer the next section to find
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the input clocks for a given controller.
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- clock-names: list of names of clocks which are exteral input clocks to the
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- clock-names: list of names of clocks which are external input clocks to the
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given clock controller.
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Input clocks for top clock controller:
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@ -227,7 +227,7 @@ properties:
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state as defined in 7.4.2 Sink Electrical Parameters of USB Power Delivery Specification
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Revision 3.0, Version 1.2. When the property is set, the port requests pSnkStby(2.5W -
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5V@500mA) upon entering SNK_DISCOVERY(instead of 3A or the 1.5A, Rp current advertised, during
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SNK_DISCOVERY) and the actual currrent limit after reception of PS_Ready for PD link or during
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SNK_DISCOVERY) and the actual current limit after reception of PS_Ready for PD link or during
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SNK_READY for non-pd link.
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type: boolean
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@ -18,7 +18,7 @@ description: |
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each IP (DMC, CPU, RIGHTBUS, LEFTBUS, CAM interface, LCD, G3D, MFC). The
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Exynos PPMU driver uses the devfreq-event class to provide event data to
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various devfreq devices. The devfreq devices would use the event data when
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derterming the current state of each IP.
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determining the current state of each IP.
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properties:
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compatible:
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@ -12,7 +12,7 @@ Required properties:
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Required children nodes:
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Children nodes are encoding available output ports and their connections
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to external devices using the OF graph reprensentation (see ../graph.txt).
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to external devices using the OF graph representation (see ../graph.txt).
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At least one port node is required.
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Optional properties in grandchild nodes:
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@ -11,7 +11,7 @@ maintainers:
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description: |
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This document defines device tree properties for the Synopsys DesignWare MIPI
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DSI host controller. It doesn't constitue a device tree binding specification
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DSI host controller. It doesn't constitute a device tree binding specification
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by itself but is meant to be referenced by platform-specific device tree
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bindings.
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@ -1,4 +1,4 @@
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* Currus Logic CLPS711X Framebuffer
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* Cirrus Logic CLPS711X Framebuffer
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Required properties:
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- compatible: Shall contain "cirrus,ep7209-fb".
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@ -11,7 +11,7 @@ maintainers:
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- Rob Clark <robdclark@gmail.com>
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description:
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This is the bindings documentation for the Mobile Display Subsytem(MDSS) that
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This is the bindings documentation for the Mobile Display Subsystem(MDSS) that
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encapsulates sub-blocks like MDP5, DSI, HDMI, eDP, etc.
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properties:
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@ -20,7 +20,7 @@ description: |
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The panel itself contains:
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- AT24C16C EEPROM holding panel identification and timing requirements
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- AR1021 resistive touch screen controller (optional)
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- FT5x6 capacitive touch screnn controller (optional)
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- FT5x6 capacitive touch screen controller (optional)
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- GT911/GT928 capacitive touch screen controller (optional)
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The above chips share same I2C bus. The EEPROM is factory preprogrammed with
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@ -12,7 +12,7 @@ maintainers:
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description: |
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This document defines device tree properties common to several classes of
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display panels. It doesn't constitue a device tree binding specification by
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display panels. It doesn't constitute a device tree binding specification by
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itself but is meant to be referenced by device tree bindings.
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When referenced from panel device tree bindings the properties defined in this
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@ -97,7 +97,7 @@ properties:
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# optional when driving an eDP output
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nvidia,dpaux:
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description: phandle to a DispayPort AUX interface
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description: phandle to a DisplayPort AUX interface
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$ref: /schemas/types.yaml#/definitions/phandle
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allOf:
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@ -68,7 +68,7 @@ properties:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: >
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Bitmask of channels to reserve for devices that need a specific
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channel. These channels will only be assigned when explicitely
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channel. These channels will only be assigned when explicitly
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requested by a client. The primary use for this is channels 0 and
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1, which can be configured to have special behaviour for NAND/BCH
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when using programmable firmware.
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@ -2,7 +2,7 @@
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Required properties:
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- compatible: Should be "nvidia,<chip>-apbdma"
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- reg: Should contain DMA registers location and length. This shuld include
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- reg: Should contain DMA registers location and length. This should include
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all of the per-channel registers.
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- interrupts: Should contain all of the per-channel DMA interrupts.
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- clocks: Must contain one entry, for the module clock.
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@ -48,7 +48,7 @@ properties:
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qcom,controlled-remotely:
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type: boolean
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description:
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Indicates that the bam is controlled by remote proccessor i.e. execution
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Indicates that the bam is controlled by remote processor i.e. execution
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environment.
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qcom,ee:
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@ -148,7 +148,7 @@ properties:
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memcpy-channels:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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description: Array of u32 elements indicating which channels on the DMA
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engine are elegible for memcpy transfers
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engine are eligible for memcpy transfers
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required:
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- "#dma-cells"
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@ -63,7 +63,7 @@ FPGA Bridge
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will be disabled.
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* During Partial Reconfiguration of a specific region, that region's bridge
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will be used to gate the busses. Traffic to other regions is not affected.
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* In some implementations, the FPGA Manager transparantly handles gating the
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* In some implementations, the FPGA Manager transparently handles gating the
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buses, eliminating the need to show the hardware FPGA bridges in the
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device tree.
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* An FPGA image may create a set of reprogrammable regions, each having its
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@ -466,7 +466,7 @@ It is beyond the scope of this document to fully describe all the FPGA design
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constraints required to make partial reconfiguration work[1] [2] [3], but a few
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deserve quick mention.
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A persona must have boundary connections that line up with those of the partion
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A persona must have boundary connections that line up with those of the partition
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or region it is designed to go into.
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During programming, transactions through those connections must be stopped and
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@ -27,7 +27,7 @@ Required properties:
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- gpio-controller: Marks the device node as a GPIO controller.
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- interrupts: The EXT_INT_0 parent interrupt resource must be listed first.
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- interrupt-cells: Should be two.
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- first cell is 0-N coresponding for EXT_INT_0 to EXT_INT_N.
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- first cell is 0-N corresponding for EXT_INT_0 to EXT_INT_N.
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- second cell is used to specify flags.
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- interrupt-controller: Marks the device node as an interrupt controller.
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- apm,nr-gpios: Optional, specify number of gpios pin.
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@ -9,7 +9,7 @@ title: Synopsys DesignWare APB GPIO controller
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description: |
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Synopsys DesignWare GPIO controllers have a configurable number of ports,
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each of which are intended to be represented as child nodes with the generic
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GPIO-controller properties as desribed in this bindings file.
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GPIO-controller properties as described in this bindings file.
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maintainers:
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- Hoan Tran <hoan@os.amperecomputing.com>
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@ -58,14 +58,14 @@ properties:
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deprecated: true
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description:
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Name of the hwmod associated with the GPIO. Needed on some legacy OMAP
|
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SoCs which have not been converted to the ti,sysc interconnect hierarachy.
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SoCs which have not been converted to the ti,sysc interconnect hierarchy.
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ti,no-reset-on-init:
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$ref: /schemas/types.yaml#/definitions/flag
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deprecated: true
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description:
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Do not reset on init. Used with ti,hwmods on some legacy OMAP SoCs which
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have not been converted to the ti,sysc interconnect hierarachy.
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have not been converted to the ti,sysc interconnect hierarchy.
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patternProperties:
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"^(.+-hog(-[0-9]+)?)$":
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@ -27,7 +27,7 @@ properties:
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shunt-resistor-micro-ohms:
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description:
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The value of curent sense resistor in microohms. If not provided,
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The value of current sense resistor in microohms. If not provided,
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the current reading and overcurrent alert is disabled.
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adi,shutdown-threshold-microamp:
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@ -11,7 +11,7 @@ maintainers:
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- Nuno Sá <nuno.sa@analog.com>
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description: |+
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Bindings for the Analog Devices AXI FAN Control driver. Spefications of the
|
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Bindings for the Analog Devices AXI FAN Control driver. Specifications of the
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core can be found in:
|
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||||
https://wiki.analog.com/resources/fpga/docs/axi_fan_control
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@ -46,7 +46,7 @@ patternProperties:
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shunt-resistor-micro-ohms:
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description:
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The value of curent sense resistor in microohms.
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The value of current sense resistor in microohms.
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required:
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- compatible
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@ -45,7 +45,7 @@ Required properties for each child node:
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- aspeed,fan-tach-ch : should specify the Fan tach input channel.
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integer value in the range 0 through 15, with 0 indicating
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Fan tach channel 0 and 15 indicating Fan tach channel 15.
|
||||
Atleast one Fan tach input channel is required.
|
||||
At least one Fan tach input channel is required.
|
||||
|
||||
Examples:
|
||||
|
||||
|
||||
@ -18,7 +18,7 @@ optional properties:
|
||||
in7. Otherwise the pin is set as FAN2 input.
|
||||
|
||||
- vcc-supply: a Phandle for the regulator supplying power, can be
|
||||
cofigured to measure 5.0V power supply. Default is 3.3V.
|
||||
configured to measure 5.0V power supply. Default is 3.3V.
|
||||
|
||||
Example:
|
||||
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
Lantiq cpu temperatur sensor
|
||||
Lantiq cpu temperature sensor
|
||||
|
||||
Requires node properties:
|
||||
- compatible value :
|
||||
|
||||
@ -42,7 +42,7 @@ properties:
|
||||
reg:
|
||||
items:
|
||||
- description: PVT common registers
|
||||
- description: PVT temprature sensor registers
|
||||
- description: PVT temperature sensor registers
|
||||
- description: PVT process detector registers
|
||||
- description: PVT voltage monitor registers
|
||||
|
||||
|
||||
@ -23,7 +23,7 @@ Required properties for pwm-fan node
|
||||
fan subnode format:
|
||||
===================
|
||||
Under fan subnode can be upto 8 child nodes, each child node representing a fan.
|
||||
Each fan subnode must have one PWM channel and atleast one Fan tach channel.
|
||||
Each fan subnode must have one PWM channel and at least one Fan tach channel.
|
||||
|
||||
For PWM channel can be configured cooling-levels to create cooling device.
|
||||
Cooling device could be bound to a thermal zone for the thermal control.
|
||||
|
||||
@ -13,7 +13,7 @@ description: |
|
||||
The SHTC1, SHTW1 and SHTC3 are digital humidity and temperature sensors
|
||||
designed especially for battery-driven high-volume consumer electronics
|
||||
applications.
|
||||
For further information refere to Documentation/hwmon/shtc1.rst
|
||||
For further information refer to Documentation/hwmon/shtc1.rst
|
||||
|
||||
This binding document describes the binding for the hardware monitor
|
||||
portion of the driver.
|
||||
|
||||
@ -33,7 +33,7 @@ properties:
|
||||
|
||||
shunt-resistor-micro-ohms:
|
||||
description: |
|
||||
If 0, the calibration process will be skiped and the current and power
|
||||
If 0, the calibration process will be skipped and the current and power
|
||||
measurement engine will not work. Temperature and voltage measurement
|
||||
will continue to work. The shunt value also need to respect:
|
||||
rshunt <= pga-gain * 40 * 1000 * 1000.
|
||||
|
||||
@ -26,7 +26,7 @@ properties:
|
||||
maxItems: 1
|
||||
|
||||
shunt-resistor-micro-ohms:
|
||||
description: The value of curent sense resistor in microohms.
|
||||
description: The value of current sense resistor in microohms.
|
||||
default: 255000
|
||||
minimum: 250000
|
||||
maximum: 255000
|
||||
|
||||
@ -10,7 +10,7 @@ Required properties:
|
||||
"source" for I2C source (parent) clock,
|
||||
"enable" for I2C module enable clock.
|
||||
- clocks: Should contain a clock specifier for each entry in clock-names.
|
||||
- clock-frequency: Constains desired I2C bus clock frequency in Hz.
|
||||
- clock-frequency: Contains desired I2C bus clock frequency in Hz.
|
||||
- #address-cells: Should be 1 to describe address cells for I2C device address.
|
||||
- #size-cells: Should be 0 means no size cell for I2C device address.
|
||||
|
||||
|
||||
@ -57,7 +57,7 @@ description: |
|
||||
|27 |FPD Internal voltage measurement, VCC_PSINTFP (supply5). |Voltage
|
||||
|28 |PS Auxiliary voltage measurement (supply6). |Voltage
|
||||
|29 |PL VCCADC voltage measurement (vccams). |Voltage
|
||||
|30 |Differential analog input signal voltage measurment. |Voltage
|
||||
|30 |Differential analog input signal voltage measurement. |Voltage
|
||||
|31 |VUser0 voltage measurement (supply7). |Voltage
|
||||
|32 |VUser1 voltage measurement (supply8). |Voltage
|
||||
|33 |VUser2 voltage measurement (supply9). |Voltage
|
||||
|
||||
@ -4,7 +4,7 @@
|
||||
$id: http://devicetree.org/schemas/iio/cdc/adi,ad7150.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Analog device AD7150 and similar capacitance to digital convertors.
|
||||
title: Analog device AD7150 and similar capacitance to digital converters.
|
||||
|
||||
maintainers:
|
||||
- Jonathan Cameron <jic23@kernel.org>
|
||||
|
||||
@ -12,7 +12,7 @@ maintainers:
|
||||
|
||||
description: |
|
||||
This document defines device tree properties common to several iio
|
||||
sensors. It doesn't constitue a device tree binding specification by itself but
|
||||
sensors. It doesn't constitute a device tree binding specification by itself but
|
||||
is meant to be referenced by device tree bindings.
|
||||
|
||||
When referenced from sensor tree bindings the properties defined in this
|
||||
|
||||
@ -33,7 +33,7 @@ properties:
|
||||
items:
|
||||
- const: lo_in
|
||||
description:
|
||||
External clock that provides the Local Oscilator input.
|
||||
External clock that provides the Local Oscillator input.
|
||||
|
||||
vcm-supply:
|
||||
description:
|
||||
|
||||
@ -10,7 +10,7 @@ maintainers:
|
||||
- Eugene Zaikonnikov <ez@norophonic.com>
|
||||
|
||||
description: |
|
||||
Relative humidity and tempereature sensors on I2C bus
|
||||
Relative humidity and temperature sensors on I2C bus
|
||||
|
||||
Datasheets are available at:
|
||||
http://www.ti.com/product/HDC2010/datasheet
|
||||
|
||||
@ -47,7 +47,7 @@ properties:
|
||||
reset-gpios:
|
||||
description:
|
||||
Optional GPIO for resetting the device.
|
||||
If not present the device is not resetted during the probe.
|
||||
If not present the device is not reset during the probe.
|
||||
maxItems: 1
|
||||
|
||||
honeywell,pmin-pascal:
|
||||
|
||||
@ -10,7 +10,7 @@ maintainers:
|
||||
- Matt Ranostay <matt.ranostay@konsulko.com>
|
||||
|
||||
description:
|
||||
This lightening distance sensor uses an I2C or SPI interface. The
|
||||
This lightning distance sensor uses an I2C or SPI interface. The
|
||||
binding currently only covers the SPI option.
|
||||
|
||||
properties:
|
||||
|
||||
@ -97,7 +97,7 @@ properties:
|
||||
|
||||
interrupts:
|
||||
description: interrupt line(s) connected to the DRDY line(s) and/or the
|
||||
Intertial interrupt lines INT1 and INT2 if these exist. This means up to
|
||||
Inertial interrupt lines INT1 and INT2 if these exist. This means up to
|
||||
three interrupts, and the DRDY must be the first one if it exists on
|
||||
the package. The trigger edge of the interrupts is sometimes software
|
||||
configurable in the hardware so the operating system should parse this
|
||||
|
||||
@ -34,8 +34,8 @@ Optional Properties:
|
||||
mode.
|
||||
- syna,sensor-type: Set the sensor type. 1 for touchscreen 2 for touchpad.
|
||||
- syna,disable-report-mask: Mask for disabling posiiton reporting. Used to
|
||||
disable reporing absolute position data.
|
||||
- syna,rezero-wait-ms: Time in miliseconds to wait after issuing a rezero
|
||||
disable reporting absolute position data.
|
||||
- syna,rezero-wait-ms: Time in milliseconds to wait after issuing a rezero
|
||||
command.
|
||||
|
||||
|
||||
|
||||
@ -6,7 +6,7 @@ Required properties:
|
||||
- ti,x-plate-ohms: X-plate resistance in ohms.
|
||||
|
||||
Optional properties:
|
||||
- gpios: the interrupt gpio the chip is connected to (trough the penirq pin).
|
||||
- gpios: the interrupt gpio the chip is connected to (through the penirq pin).
|
||||
The penirq pin goes to low when the panel is touched.
|
||||
(see GPIO binding[1] for more details).
|
||||
- interrupts: (gpio) interrupt to which the chip is connected
|
||||
|
||||
@ -49,7 +49,7 @@ properties:
|
||||
|
||||
The 2nd cell contains the interrupt number for the interrupt type.
|
||||
SPI interrupts are in the range [0-987]. PPI interrupts are in the
|
||||
range [0-15]. Extented SPI interrupts are in the range [0-1023].
|
||||
range [0-15]. Extended SPI interrupts are in the range [0-1023].
|
||||
Extended PPI interrupts are in the range [0-127].
|
||||
|
||||
The 3rd cell is the flags, encoded as follows:
|
||||
|
||||
@ -70,7 +70,7 @@ Bank 1:
|
||||
25: DMA9
|
||||
26: DMA10
|
||||
27: DMA11-14 - shared interrupt for DMA 11 to 14
|
||||
28: DMAALL - triggers on all dma interrupts (including chanel 15)
|
||||
28: DMAALL - triggers on all dma interrupts (including channel 15)
|
||||
29: AUX
|
||||
30: ARM
|
||||
31: VPUDMA
|
||||
|
||||
@ -59,7 +59,7 @@ description: >
|
||||
..
|
||||
31 ........................ X
|
||||
|
||||
The BCM3380 Level 1 / Level 2 interrrupt controller shows up in various forms
|
||||
The BCM3380 Level 1 / Level 2 interrupt controller shows up in various forms
|
||||
on many BCM338x/BCM63xx chipsets. It has the following properties:
|
||||
|
||||
- outputs a single interrupt signal to its interrupt controller parent
|
||||
|
||||
@ -66,7 +66,7 @@ properties:
|
||||
|
||||
mediatek,bled-ocp-shutdown:
|
||||
description: |
|
||||
Enable the backlight shutdown when OCP level triggerred.
|
||||
Enable the backlight shutdown when OCP level triggered.
|
||||
type: boolean
|
||||
|
||||
mediatek,bled-ocp-microamp:
|
||||
|
||||
@ -106,7 +106,7 @@ patternProperties:
|
||||
|
||||
max-cur:
|
||||
$ref: /schemas/types.yaml#/definitions/uint8
|
||||
description: Maximun current at each LED channel.
|
||||
description: Maximum current at each LED channel.
|
||||
|
||||
reg:
|
||||
maximum: 8
|
||||
@ -129,7 +129,7 @@ patternProperties:
|
||||
|
||||
max-cur:
|
||||
$ref: /schemas/types.yaml#/definitions/uint8
|
||||
description: Maximun current at each LED channel.
|
||||
description: Maximum current at each LED channel.
|
||||
|
||||
reg:
|
||||
description: |
|
||||
|
||||
@ -56,7 +56,7 @@ properties:
|
||||
description: >
|
||||
A list of integer pairs, where each pair represent the dtest line the
|
||||
particular channel should be connected to and the flags denoting how the
|
||||
value should be outputed, as defined in the datasheet. The number of
|
||||
value should be outputted, as defined in the datasheet. The number of
|
||||
pairs should be the same as the number of channels.
|
||||
items:
|
||||
items:
|
||||
|
||||
@ -29,7 +29,7 @@ Required properties:
|
||||
where N is the value specified by 2nd cell above. If FlexRM
|
||||
does not get required number of completion messages in time
|
||||
specified by this cell then it will inject one MSI interrupt
|
||||
to CPU provided atleast one completion message is available.
|
||||
to CPU provided at least one completion message is available.
|
||||
|
||||
Optional properties:
|
||||
--------------------
|
||||
|
||||
@ -159,7 +159,7 @@ properties:
|
||||
a corresponding sysc interconnect node.
|
||||
|
||||
This property is only needed on some legacy OMAP SoCs which have not
|
||||
yet been converted to the ti,sysc interconnect hierarachy, but is
|
||||
yet been converted to the ti,sysc interconnect hierarchy, but is
|
||||
otherwise considered obsolete.
|
||||
|
||||
patternProperties:
|
||||
|
||||
@ -12,7 +12,7 @@ maintainers:
|
||||
description: |-
|
||||
The Toshiba TC358746 converts a parallel video stream into a MIPI CSI-2
|
||||
stream. The direction can be either parallel-in -> csi-out or csi-in ->
|
||||
parallel-out The chip is programmable trough I2C and SPI but the SPI
|
||||
parallel-out The chip is programmable through I2C and SPI but the SPI
|
||||
interface is only supported in parallel-in -> csi-out mode.
|
||||
|
||||
Note that the current device tree bindings only support the
|
||||
|
||||
@ -53,7 +53,7 @@ Optional Connector Properties:
|
||||
==============================
|
||||
|
||||
- sdtv-standards: Set the possible signals to which the hardware tries to lock
|
||||
instead of using the autodetection mechnism. Please look at
|
||||
instead of using the autodetection mechanism. Please look at
|
||||
[1] for more information.
|
||||
|
||||
[1] Documentation/devicetree/bindings/display/connector/analog-tv-connector.yaml.
|
||||
|
||||
@ -36,7 +36,7 @@ description: |
|
||||
controls the information of each hardware independent which include clk/power/irq.
|
||||
|
||||
There are two workqueues in parent device: lat workqueue and core workqueue. They are used
|
||||
to lat and core hardware deocder. Lat workqueue need to get input bitstream and lat buffer,
|
||||
to lat and core hardware decoder. Lat workqueue need to get input bitstream and lat buffer,
|
||||
then enable lat to decode, writing the result to lat buffer, dislabe hardware when lat decode
|
||||
done. Core workqueue need to get lat buffer and output buffer, then enable core to decode,
|
||||
writing the result to output buffer, disable hardware when core decode done. These two
|
||||
|
||||
@ -67,7 +67,7 @@ properties:
|
||||
minimum: 0
|
||||
maximum: 31
|
||||
description: the hardware id of this larb. It's only required when this
|
||||
hardward id is not consecutive from its M4U point of view.
|
||||
hardware id is not consecutive from its M4U point of view.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
@ -152,7 +152,7 @@ properties:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
When the DRAM type is DDR3, this parameter defines the phy side CA line
|
||||
(incluing command line, address line and clock line) drive strength.
|
||||
(including command line, address line and clock line) drive strength.
|
||||
default: 40
|
||||
|
||||
rockchip,phy_ddr3_dq_drv:
|
||||
@ -305,7 +305,7 @@ properties:
|
||||
description:
|
||||
Defines the self-refresh power down idle period in which memories are
|
||||
placed into self-refresh power down mode if bus is idle for
|
||||
srpd_lite_idle nanoseonds. This parameter is for LPDDR4 only.
|
||||
srpd_lite_idle nanoseconds. This parameter is for LPDDR4 only.
|
||||
|
||||
rockchip,standby-idle-ns:
|
||||
description:
|
||||
|
||||
@ -12,7 +12,7 @@ maintainers:
|
||||
|
||||
description:
|
||||
The Zynq DDR ECC controller has an optional ECC support in half-bus width
|
||||
(16-bit) configuration. It is cappable of correcting single bit ECC errors
|
||||
(16-bit) configuration. It is capable of correcting single bit ECC errors
|
||||
and detecting double bit ECC errors.
|
||||
|
||||
properties:
|
||||
|
||||
@ -27,7 +27,7 @@ description:
|
||||
as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
|
||||
management and bus snoop configuration.
|
||||
|
||||
* A set of SuperIO[3] scratch registers enableing implementation of e.g. custom
|
||||
* A set of SuperIO[3] scratch registers enabling implementation of e.g. custom
|
||||
hardware management protocols for handover between the host and baseboard
|
||||
management controller.
|
||||
|
||||
|
||||
@ -34,7 +34,7 @@ properties:
|
||||
BD9576 and BD9573 VOUT1 regulator enable state can be individually
|
||||
controlled by a GPIO. This is dictated by state of vout1-en pin during
|
||||
the PMIC startup. If vout1-en is LOW during PMIC startup then the VOUT1
|
||||
enable sate is controlled via this pin. Set this property if vout1-en
|
||||
enable state is controlled via this pin. Set this property if vout1-en
|
||||
is wired to be down at PMIC start-up.
|
||||
type: boolean
|
||||
|
||||
@ -61,7 +61,7 @@ properties:
|
||||
rohm,hw-timeout-ms:
|
||||
maxItems: 2
|
||||
description:
|
||||
Watchog timeout in milliseconds. If single value is given it is
|
||||
Watchdog timeout in milliseconds. If single value is given it is
|
||||
the maximum timeout. Eg. if pinging watchdog is not done within this time
|
||||
limit the watchdog will be triggered. If two values are given watchdog
|
||||
is configured in "window mode". Then first value is limit for short-ping
|
||||
|
||||
@ -313,7 +313,7 @@ properties:
|
||||
- const: audioclk
|
||||
|
||||
stericsson,earpeice-cmv:
|
||||
description: Earpeice voltage
|
||||
description: Earpiece voltage
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [ 950, 1100, 1270, 1580 ]
|
||||
|
||||
@ -337,39 +337,39 @@ properties:
|
||||
with power.
|
||||
|
||||
ab8500_ldo_aux1:
|
||||
description: The voltage for the auxilary LDO regulator 1
|
||||
description: The voltage for the auxiliary LDO regulator 1
|
||||
type: object
|
||||
$ref: ../regulator/regulator.yaml#
|
||||
unevaluatedProperties: false
|
||||
|
||||
ab8500_ldo_aux2:
|
||||
description: The voltage for the auxilary LDO regulator 2
|
||||
description: The voltage for the auxiliary LDO regulator 2
|
||||
type: object
|
||||
$ref: ../regulator/regulator.yaml#
|
||||
unevaluatedProperties: false
|
||||
|
||||
ab8500_ldo_aux3:
|
||||
description: The voltage for the auxilary LDO regulator 3
|
||||
description: The voltage for the auxiliary LDO regulator 3
|
||||
type: object
|
||||
$ref: ../regulator/regulator.yaml#
|
||||
unevaluatedProperties: false
|
||||
|
||||
ab8500_ldo_aux4:
|
||||
description: The voltage for the auxilary LDO regulator 4
|
||||
description: The voltage for the auxiliary LDO regulator 4
|
||||
only present on AB8505
|
||||
type: object
|
||||
$ref: ../regulator/regulator.yaml#
|
||||
unevaluatedProperties: false
|
||||
|
||||
ab8500_ldo_aux5:
|
||||
description: The voltage for the auxilary LDO regulator 5
|
||||
description: The voltage for the auxiliary LDO regulator 5
|
||||
only present on AB8505
|
||||
type: object
|
||||
$ref: ../regulator/regulator.yaml#
|
||||
unevaluatedProperties: false
|
||||
|
||||
ab8500_ldo_aux6:
|
||||
description: The voltage for the auxilary LDO regulator 6
|
||||
description: The voltage for the auxiliary LDO regulator 6
|
||||
only present on AB8505
|
||||
type: object
|
||||
$ref: ../regulator/regulator.yaml#
|
||||
@ -378,7 +378,7 @@ properties:
|
||||
# There is never any AUX7 regulator which is confusing
|
||||
|
||||
ab8500_ldo_aux8:
|
||||
description: The voltage for the auxilary LDO regulator 8
|
||||
description: The voltage for the auxiliary LDO regulator 8
|
||||
only present on AB8505
|
||||
type: object
|
||||
$ref: ../regulator/regulator.yaml#
|
||||
|
||||
@ -107,7 +107,7 @@ properties:
|
||||
$ref: ../regulator/regulator.yaml#
|
||||
|
||||
db8500_vrf1:
|
||||
description: RF transciever voltage regulator.
|
||||
description: RF transceiver voltage regulator.
|
||||
type: object
|
||||
$ref: ../regulator/regulator.yaml#
|
||||
|
||||
|
||||
@ -9,7 +9,7 @@ Required properties:
|
||||
Optional properties:
|
||||
- marvell,detect-delay-ms: sets the detection delay timeout in ms.
|
||||
|
||||
In addition to the properties described in this docuent, the details
|
||||
In addition to the properties described in this document, the details
|
||||
described in mmc.txt are supported.
|
||||
|
||||
Examples:
|
||||
|
||||
@ -95,7 +95,7 @@ while in suspend.
|
||||
| card | -- CIRQ --> | hsmmc | -- IRQ --> | CPU |
|
||||
------ ------- -----
|
||||
|
||||
In suspend the fclk is off and the module is disfunctional. Even register reads
|
||||
In suspend the fclk is off and the module is dysfunctional. Even register reads
|
||||
will fail. A small logic in the host will request fclk restore, when an
|
||||
external event is detected. Once the clock is restored, the host detects the
|
||||
event normally. Since am33xx doesn't have this line it never wakes from
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
* Broadcom Starfighter 2 integrated swich
|
||||
* Broadcom Starfighter 2 integrated switch
|
||||
|
||||
See dsa/brcm,bcm7445-switch-v4.0.yaml for the documentation.
|
||||
|
||||
|
||||
@ -26,7 +26,7 @@ Optional properties:
|
||||
will be disabled.
|
||||
|
||||
- bosch,slew-rate : slew rate of the CLKOUT signal. If not specified,
|
||||
a resonable value will be calculated.
|
||||
a reasonable value will be calculated.
|
||||
|
||||
- bosch,disconnect-rx0-input : see data sheet.
|
||||
|
||||
|
||||
@ -4,7 +4,7 @@
|
||||
$id: http://devicetree.org/schemas/net/dsa/brcm,sf2.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom Starfighter 2 integrated swich
|
||||
title: Broadcom Starfighter 2 integrated switch
|
||||
|
||||
maintainers:
|
||||
- Florian Fainelli <f.fainelli@gmail.com>
|
||||
|
||||
@ -110,7 +110,7 @@ properties:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
If set, indicates that PHY will disable swap of the
|
||||
TX/RX lanes. This property allows the PHY to work correcly after
|
||||
TX/RX lanes. This property allows the PHY to work correctly after
|
||||
e.g. wrong bootstrap configuration caused by issues in PCB
|
||||
layout design.
|
||||
|
||||
|
||||
@ -129,7 +129,7 @@ properties:
|
||||
type: boolean
|
||||
description:
|
||||
If present, indicates that MAC supports WOL(Wake-On-LAN), and MAC WOL will be enabled.
|
||||
Otherwise, PHY WOL is perferred.
|
||||
Otherwise, PHY WOL is preferred.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
@ -33,7 +33,7 @@ properties:
|
||||
- usb424,9906 # SMSC9505A USB Ethernet Device (HAL)
|
||||
- usb424,9907 # SMSC9500 USB Ethernet Device (Alternate ID)
|
||||
- usb424,9908 # SMSC9500A USB Ethernet Device (Alternate ID)
|
||||
- usb424,9909 # SMSC9512/9514 USB Hub & Ethernet Devic. ID)
|
||||
- usb424,9909 # SMSC9512/9514 USB Hub & Ethernet Device ID)
|
||||
- usb424,9e00 # SMSC9500A USB Ethernet Device
|
||||
- usb424,9e01 # SMSC9505A USB Ethernet Device
|
||||
- usb424,9e08 # SMSC LAN89530 USB Ethernet Device
|
||||
|
||||
@ -37,13 +37,13 @@ properties:
|
||||
type: boolean
|
||||
description: |
|
||||
For I2C type of connection. Specifies that the chip read event shall be
|
||||
trigged on falling edge.
|
||||
triggered on falling edge.
|
||||
|
||||
i2c-int-rising:
|
||||
type: boolean
|
||||
description: |
|
||||
For I2C type of connection. Specifies that the chip read event shall be
|
||||
trigged on rising edge.
|
||||
triggered on rising edge.
|
||||
|
||||
break-control:
|
||||
type: boolean
|
||||
|
||||
@ -5,10 +5,10 @@ Required properties:
|
||||
- reg: Address and length of the register set for the device
|
||||
- interrupts: Should contain the SXGBE interrupts
|
||||
These interrupts are ordered by fixed and follows variable
|
||||
trasmit DMA interrupts, receive DMA interrupts and lpi interrupt.
|
||||
transmit DMA interrupts, receive DMA interrupts and lpi interrupt.
|
||||
index 0 - this is fixed common interrupt of SXGBE and it is always
|
||||
available.
|
||||
index 1 to 25 - 8 variable trasmit interrupts, variable 16 receive interrupts
|
||||
index 1 to 25 - 8 variable transmit interrupts, variable 16 receive interrupts
|
||||
and 1 optional lpi interrupt.
|
||||
- phy-mode: String, operation mode of the PHY interface.
|
||||
Supported values are: "sgmii", "xgmii".
|
||||
|
||||
@ -110,7 +110,7 @@ Optional properties:
|
||||
It depends on the SoC configuration.
|
||||
- snps,read-requests: Number of read requests that the AXI port can issue.
|
||||
It depends on the SoC configuration.
|
||||
- snps,burst-map: Bitmap of allowed AXI burst lengts, with the LSB
|
||||
- snps,burst-map: Bitmap of allowed AXI burst lengths, with the LSB
|
||||
representing 4, then 8 etc.
|
||||
- snps,txpbl: DMA Programmable burst length for the TX DMA
|
||||
- snps,rxpbl: DMA Programmable burst length for the RX DMA
|
||||
|
||||
@ -21,7 +21,7 @@ Optional properties:
|
||||
MAC can generate it.
|
||||
- st,tx-retime-src: This specifies which clk is wired up to the mac for
|
||||
retimeing tx lines. This is totally board dependent and can take one of the
|
||||
posssible values from "txclk", "clk_125" or "clkgen".
|
||||
possible values from "txclk", "clk_125" or "clkgen".
|
||||
If not passed, the internal clock will be used by default.
|
||||
- sti-ethclk: this is the phy clock.
|
||||
- sti-clkconf: this is an extra sysconfig register, available in new SoCs,
|
||||
|
||||
@ -7,7 +7,7 @@ Ethernet physical media devices (PHY) and the Gigabit Ethernet controller.
|
||||
This core can be used in all three modes of operation(10/100/1000 Mb/s).
|
||||
The Management Data Input/Output (MDIO) interface is used to configure the
|
||||
Speed of operation. This core can switch dynamically between the three
|
||||
Different speed modes by configuring the conveter register through mdio write.
|
||||
Different speed modes by configuring the converter register through mdio write.
|
||||
|
||||
This converter sits between the ethernet MAC and the external phy.
|
||||
MAC <==> GMII2RGMII <==> RGMII_PHY
|
||||
|
||||
@ -23,7 +23,7 @@ Required properties:
|
||||
- altr,tlb-num-ways: Specifies the number of set-associativity ways in the TLB.
|
||||
- altr,tlb-num-entries: Specifies the number of entries in the TLB.
|
||||
- altr,tlb-ptr-sz: Specifies size of TLB pointer.
|
||||
- altr,has-mul: Specifies CPU hardware multipy support, should be 1.
|
||||
- altr,has-mul: Specifies CPU hardware multiply support, should be 1.
|
||||
- altr,has-mmu: Specifies CPU support MMU support, should be 1.
|
||||
- altr,has-initda: Specifies CPU support initda instruction, should be 1.
|
||||
- altr,reset-addr: Specifies CPU reset address
|
||||
|
||||
@ -14,7 +14,7 @@ description:
|
||||
infrastructure shall provide a non-volatile memory with a table whose the
|
||||
content is well specified and gives many information about the manufacturer
|
||||
(name, country of manufacture, etc) as well as device caracteristics (serial
|
||||
number, hardware version, mac addresses, etc). The underlaying device type
|
||||
number, hardware version, mac addresses, etc). The underlying device type
|
||||
(flash, EEPROM,...) is not specified. The exact location of each value is also
|
||||
dynamic and should be discovered at run time because it depends on the
|
||||
parameters the manufacturer decided to embed.
|
||||
|
||||
@ -14,7 +14,7 @@ Required properties:
|
||||
- #size-cells: Must be 0.
|
||||
|
||||
The INNO USB2 PHY device should be a child node of peripheral controller that
|
||||
contains the PHY configuration register, and each device suppports up to 2 PHY
|
||||
contains the PHY configuration register, and each device supports up to 2 PHY
|
||||
ports which are represented as child nodes of INNO USB2 PHY device.
|
||||
|
||||
Required properties for PHY port node:
|
||||
|
||||
@ -8,7 +8,7 @@ Required properties:
|
||||
- clocks: Must contain an entry for each entry in clock-names.
|
||||
See ../clock/clock-bindings.txt for details.
|
||||
- clock-names: Must include "usb_phy".
|
||||
- img,cr-top: Must constain a phandle to the CR_TOP syscon node.
|
||||
- img,cr-top: Must contain a phandle to the CR_TOP syscon node.
|
||||
- img,refclk: Indicates the reference clock source for the USB PHY.
|
||||
See <dt-bindings/phy/phy-pistachio-usb.h> for a list of valid values.
|
||||
|
||||
|
||||
@ -4,7 +4,7 @@ Required properties:
|
||||
- compatible: "marvell,pxa1928-usb-phy" or "marvell,pxa1928-hsic-phy"
|
||||
- reg: base address and length of the registers
|
||||
- clocks - A single clock. From common clock binding.
|
||||
- #phys-cells: should be 0. From commmon phy binding.
|
||||
- #phys-cells: should be 0. From common phy binding.
|
||||
- resets: reference to the reset controller
|
||||
|
||||
Example:
|
||||
|
||||
@ -10,7 +10,7 @@ maintainers:
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
description: |
|
||||
The Rockchip SoC has a MIPI CSI D-PHY based on an Innosilicon IP wich
|
||||
The Rockchip SoC has a MIPI CSI D-PHY based on an Innosilicon IP which
|
||||
connects to the ISP1 (Image Signal Processing unit v1.0) for CSI cameras.
|
||||
|
||||
properties:
|
||||
|
||||
@ -59,7 +59,7 @@ properties:
|
||||
description:
|
||||
GPIO to signal Type-C cable orientation for lane swap.
|
||||
If GPIO is active, lane 0 and lane 1 of SERDES will be swapped to
|
||||
achieve the funtionality of an external type-C plug flip mux.
|
||||
achieve the functionality of an external type-C plug flip mux.
|
||||
|
||||
typec-dir-debounce-ms:
|
||||
minimum: 100
|
||||
|
||||
@ -62,7 +62,7 @@ Deprecated properties:
|
||||
- ctrl-module : phandle of the control module used by PHY driver to power on
|
||||
the PHY.
|
||||
|
||||
Recommended properies:
|
||||
Recommended properties:
|
||||
- syscon-phy-power : phandle/offset pair. Phandle to the system control
|
||||
module and the register offset to power on/off the PHY.
|
||||
|
||||
|
||||
@ -97,7 +97,7 @@ patternProperties:
|
||||
# It's pretty scary, but the basic idea is that:
|
||||
# - One node name can start with either s- or r- for PRCM nodes,
|
||||
# - Then, the name itself can be any repetition of <string>- (to
|
||||
# accomodate with nodes like uart4-rts-cts-pins), where each
|
||||
# accommodate with nodes like uart4-rts-cts-pins), where each
|
||||
# string can be either starting with 'p' but in a string longer
|
||||
# than 3, or something that doesn't start with 'p',
|
||||
# - Then, the bank name is optional and will be between pa and pg,
|
||||
|
||||
@ -11,7 +11,7 @@ maintainers:
|
||||
|
||||
description:
|
||||
The Canaan Kendryte K210 SoC Fully Programmable IO Array (FPIOA)
|
||||
controller allows assiging any of 256 possible functions to any of
|
||||
controller allows assigning any of 256 possible functions to any of
|
||||
48 IO pins of the SoC. Pin function configuration is performed on
|
||||
a per-pin basis.
|
||||
|
||||
|
||||
@ -159,7 +159,7 @@ patternProperties:
|
||||
|
||||
mediatek,pull-up-adv:
|
||||
description: |
|
||||
Pull up setings for 2 pull resistors, R0 and R1. User can
|
||||
Pull up settings for 2 pull resistors, R0 and R1. User can
|
||||
configure those special pins. Valid arguments are described as
|
||||
below:
|
||||
0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user