ARM: entry: Make asm coproc dispatch code NWFPE only
Now that we can dispatch all VFP and iWMMXT related undef exceptions using undef hooks implemented in C code, we no longer need the asm entry code that takes care of this unless we are using FPE, so we can move it into the FPE entry code. As this means it is ARM only, we can remove the Thumb2 specific decorations as well. It also means the non-standard, asm-only calling convention where returning via LR means failure and returning via R9 means success is now only used on legacy platforms that lack any kind of function return prediction, avoiding the associated performance impact. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
This commit is contained in:
Ard Biesheuvel
parent
303d6da167
commit
47ba5f39ea
@ -454,8 +454,10 @@ __und_usr:
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tst r5, #PSR_T_BIT @ Thumb mode?
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mov r1, #2 @ set insn size to 2 for Thumb
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bne 0f @ handle as Thumb undef exception
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#ifdef CONFIG_FPE_NWFPE
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adr r9, ret_from_exception
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bl call_fpe @ returns via R9 on success
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#endif
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mov r1, #4 @ set insn size to 4 for ARM
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0: mov r0, sp
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uaccess_disable ip
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@ -464,97 +466,6 @@ __und_usr:
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UNWIND(.fnend)
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ENDPROC(__und_usr)
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/*
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* The out of line fixup for the ldrt instruction below.
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*/
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.pushsection .text.fixup, "ax"
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.align 2
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4: str r4, [sp, #S_PC] @ retry current instruction
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ret r9
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.popsection
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/*
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* Check whether the instruction is a co-processor instruction.
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* If yes, we need to call the relevant co-processor handler.
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*
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* Note that we don't do a full check here for the co-processor
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* instructions; all instructions with bit 27 set are well
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* defined. The only instructions that should fault are the
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* co-processor instructions. However, we have to watch out
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* for the ARM6/ARM7 SWI bug.
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*
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* Emulators may wish to make use of the following registers:
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* r4 = PC value to resume execution after successful emulation
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* r9 = normal "successful" return address
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* r10 = this threads thread_info structure
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* lr = unrecognised instruction return address
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* IRQs enabled, FIQs enabled.
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*/
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call_fpe:
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mov r2, r4
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sub r4, r4, #4 @ ARM instruction at user PC - 4
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USERL( 4b, ldrt r0, [r4]) @ load opcode from user space
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ARM_BE8(rev r0, r0) @ little endian instruction
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uaccess_disable ip
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get_thread_info r10 @ get current thread
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tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
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reteq lr
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and r8, r0, #0x00000f00 @ mask out CP number
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#ifdef CONFIG_IWMMXT
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@ Test if we need to give access to iWMMXt coprocessors
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ldr r5, [r10, #TI_FLAGS]
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rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
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movscs r7, r5, lsr #(TIF_USING_IWMMXT + 1)
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movcs r0, sp @ pass struct pt_regs
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bcs iwmmxt_task_enable
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#endif
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ARM( add pc, pc, r8, lsr #6 )
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THUMB( lsr r8, r8, #6 )
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THUMB( add pc, r8 )
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nop
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ret.w lr @ CP#0
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W(b) do_fpe @ CP#1 (FPE)
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W(b) do_fpe @ CP#2 (FPE)
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ret.w lr @ CP#3
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ret.w lr @ CP#4
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ret.w lr @ CP#5
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ret.w lr @ CP#6
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ret.w lr @ CP#7
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ret.w lr @ CP#8
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ret.w lr @ CP#9
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ret.w lr @ CP#10 (VFP)
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ret.w lr @ CP#11 (VFP)
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ret.w lr @ CP#12
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ret.w lr @ CP#13
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ret.w lr @ CP#14 (Debug)
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ret.w lr @ CP#15 (Control)
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do_fpe:
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add r10, r10, #TI_FPSTATE @ r10 = workspace
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ldr_va pc, fp_enter, tmp=r4 @ Call FP module USR entry point
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/*
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* The FP module is called with these registers set:
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* r0 = instruction
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* r2 = PC+4
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* r9 = normal "successful" return address
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* r10 = FP workspace
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* lr = unrecognised FP instruction return address
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*/
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.pushsection .data
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.align 2
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ENTRY(fp_enter)
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.word no_fp
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.popsection
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ENTRY(no_fp)
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ret lr
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ENDPROC(no_fp)
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.align 5
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__pabt_usr:
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usr_entry
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@ -7,6 +7,7 @@
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Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/opcodes.h>
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@ -104,6 +105,7 @@ next:
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@ plain LDR instruction. Weird, but it seems harmless.
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.pushsection .text.fixup,"ax"
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.align 2
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.Lrep: str r4, [sp, #S_PC] @ retry current instruction
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.Lfix: ret r9 @ let the user eat segfaults
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.popsection
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@ -111,3 +113,78 @@ next:
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.align 3
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.long .Lx1, .Lfix
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.popsection
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@
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@ Check whether the instruction is a co-processor instruction.
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@ If yes, we need to call the relevant co-processor handler.
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@ Only FPE instructions are dispatched here, everything else
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@ is handled by undef hooks.
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@
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@ Emulators may wish to make use of the following registers:
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@ r4 = PC value to resume execution after successful emulation
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@ r9 = normal "successful" return address
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@ lr = unrecognised instruction return address
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@ IRQs enabled, FIQs enabled.
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@
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ENTRY(call_fpe)
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mov r2, r4
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sub r4, r4, #4 @ ARM instruction at user PC - 4
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USERL( .Lrep, ldrt r0, [r4]) @ load opcode from user space
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ARM_BE8(rev r0, r0) @ little endian instruction
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uaccess_disable ip
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get_thread_info r10 @ get current thread
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tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
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reteq lr
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and r8, r0, #0x00000f00 @ mask out CP number
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#ifdef CONFIG_IWMMXT
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@ Test if we need to give access to iWMMXt coprocessors
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ldr r5, [r10, #TI_FLAGS]
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rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
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movscs r7, r5, lsr #(TIF_USING_IWMMXT + 1)
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movcs r0, sp @ pass struct pt_regs
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bcs iwmmxt_task_enable
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#endif
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add pc, pc, r8, lsr #6
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nop
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ret lr @ CP#0
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b do_fpe @ CP#1 (FPE)
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b do_fpe @ CP#2 (FPE)
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ret lr @ CP#3
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ret lr @ CP#4
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ret lr @ CP#5
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ret lr @ CP#6
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ret lr @ CP#7
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ret lr @ CP#8
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ret lr @ CP#9
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ret lr @ CP#10 (VFP)
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ret lr @ CP#11 (VFP)
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ret lr @ CP#12
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ret lr @ CP#13
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ret lr @ CP#14 (Debug)
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ret lr @ CP#15 (Control)
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do_fpe:
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add r10, r10, #TI_FPSTATE @ r10 = workspace
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ldr_va pc, fp_enter, tmp=r4 @ Call FP module USR entry point
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@
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@ The FP module is called with these registers set:
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@ r0 = instruction
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@ r2 = PC+4
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@ r9 = normal "successful" return address
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@ r10 = FP workspace
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@ lr = unrecognised FP instruction return address
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@
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.pushsection .data
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.align 2
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ENTRY(fp_enter)
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.word no_fp
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.popsection
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no_fp:
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ret lr
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ENDPROC(no_fp)
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