soc: imx: gpcv2: add support for i.MX8MM power domains
This adds support for the power domains found on i.MX8MM. The 2D and 3D GPU domains are abstracted as a single domain in the driver, as they can't be powered up/down individually due to a shared reset. Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Lucas Stach
Shawn Guo
parent
30af8513bd
commit
47f87c6280
@ -19,6 +19,7 @@
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#include <linux/sizes.h>
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#include <dt-bindings/power/imx7-power.h>
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#include <dt-bindings/power/imx8mq-power.h>
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#include <dt-bindings/power/imx8mm-power.h>
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#define GPC_LPCR_A_CORE_BSC 0x000
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@ -44,6 +45,19 @@
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#define IMX8M_PCIE1_A53_DOMAIN BIT(3)
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#define IMX8M_MIPI_A53_DOMAIN BIT(2)
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#define IMX8MM_VPUH1_A53_DOMAIN BIT(15)
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#define IMX8MM_VPUG2_A53_DOMAIN BIT(14)
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#define IMX8MM_VPUG1_A53_DOMAIN BIT(13)
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#define IMX8MM_DISPMIX_A53_DOMAIN BIT(12)
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#define IMX8MM_VPUMIX_A53_DOMAIN BIT(10)
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#define IMX8MM_GPUMIX_A53_DOMAIN BIT(9)
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#define IMX8MM_GPU_A53_DOMAIN (BIT(8) | BIT(11))
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#define IMX8MM_DDR1_A53_DOMAIN BIT(7)
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#define IMX8MM_OTG2_A53_DOMAIN BIT(5)
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#define IMX8MM_OTG1_A53_DOMAIN BIT(4)
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#define IMX8MM_PCIE_A53_DOMAIN BIT(3)
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#define IMX8MM_MIPI_A53_DOMAIN BIT(2)
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#define GPC_PU_PGC_SW_PUP_REQ 0x0f8
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#define GPC_PU_PGC_SW_PDN_REQ 0x104
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@ -67,6 +81,19 @@
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#define IMX8M_PCIE1_SW_Pxx_REQ BIT(1)
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#define IMX8M_MIPI_SW_Pxx_REQ BIT(0)
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#define IMX8MM_VPUH1_SW_Pxx_REQ BIT(13)
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#define IMX8MM_VPUG2_SW_Pxx_REQ BIT(12)
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#define IMX8MM_VPUG1_SW_Pxx_REQ BIT(11)
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#define IMX8MM_DISPMIX_SW_Pxx_REQ BIT(10)
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#define IMX8MM_VPUMIX_SW_Pxx_REQ BIT(8)
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#define IMX8MM_GPUMIX_SW_Pxx_REQ BIT(7)
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#define IMX8MM_GPU_SW_Pxx_REQ (BIT(6) | BIT(9))
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#define IMX8MM_DDR1_SW_Pxx_REQ BIT(5)
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#define IMX8MM_OTG2_SW_Pxx_REQ BIT(3)
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#define IMX8MM_OTG1_SW_Pxx_REQ BIT(2)
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#define IMX8MM_PCIE_SW_Pxx_REQ BIT(1)
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#define IMX8MM_MIPI_SW_Pxx_REQ BIT(0)
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#define GPC_M4_PU_PDN_FLG 0x1bc
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#define GPC_PU_PWRHSK 0x1fc
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@ -78,6 +105,17 @@
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#define IMX8M_VPU_HSK_PWRDNREQN BIT(5)
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#define IMX8M_DISP_HSK_PWRDNREQN BIT(4)
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#define IMX8MM_GPUMIX_HSK_PWRDNACKN BIT(29)
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#define IMX8MM_GPU_HSK_PWRDNACKN (BIT(27) | BIT(28))
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#define IMX8MM_VPUMIX_HSK_PWRDNACKN BIT(26)
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#define IMX8MM_DISPMIX_HSK_PWRDNACKN BIT(25)
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#define IMX8MM_HSIO_HSK_PWRDNACKN (BIT(23) | BIT(24))
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#define IMX8MM_GPUMIX_HSK_PWRDNREQN BIT(11)
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#define IMX8MM_GPU_HSK_PWRDNREQN (BIT(9) | BIT(10))
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#define IMX8MM_VPUMIX_HSK_PWRDNREQN BIT(8)
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#define IMX8MM_DISPMIX_HSK_PWRDNREQN BIT(7)
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#define IMX8MM_HSIO_HSK_PWRDNREQN (BIT(5) | BIT(6))
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/*
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* The PGC offset values in Reference Manual
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* (Rev. 1, 01/2018 and the older ones) GPC chapter's
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@ -100,6 +138,20 @@
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#define IMX8M_PGC_MIPI_CSI2 28
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#define IMX8M_PGC_PCIE2 29
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#define IMX8MM_PGC_MIPI 16
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#define IMX8MM_PGC_PCIE 17
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#define IMX8MM_PGC_OTG1 18
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#define IMX8MM_PGC_OTG2 19
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#define IMX8MM_PGC_DDR1 21
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#define IMX8MM_PGC_GPU2D 22
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#define IMX8MM_PGC_GPUMIX 23
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#define IMX8MM_PGC_VPUMIX 24
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#define IMX8MM_PGC_GPU3D 25
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#define IMX8MM_PGC_DISPMIX 26
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#define IMX8MM_PGC_VPUG1 27
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#define IMX8MM_PGC_VPUG2 28
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#define IMX8MM_PGC_VPUH1 29
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#define GPC_PGC_CTRL(n) (0x800 + (n) * 0x40)
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#define GPC_PGC_SR(n) (GPC_PGC_CTRL(n) + 0xc)
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@ -527,6 +579,121 @@ static const struct imx_pgc_domain_data imx8m_pgc_domain_data = {
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.reg_access_table = &imx8m_access_table,
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};
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static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
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[IMX8MM_POWER_DOMAIN_HSIOMIX] = {
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.genpd = {
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.name = "hsiomix",
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},
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.bits = {
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.pxx = 0, /* no power sequence control */
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.map = 0, /* no power sequence control */
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.hskreq = IMX8MM_HSIO_HSK_PWRDNREQN,
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.hskack = IMX8MM_HSIO_HSK_PWRDNACKN,
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},
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},
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[IMX8MM_POWER_DOMAIN_PCIE] = {
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.genpd = {
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.name = "pcie",
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},
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.bits = {
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.pxx = IMX8MM_PCIE_SW_Pxx_REQ,
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.map = IMX8MM_PCIE_A53_DOMAIN,
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},
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.pgc = IMX8MM_PGC_PCIE,
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},
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[IMX8MM_POWER_DOMAIN_OTG1] = {
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.genpd = {
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.name = "usb-otg1",
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},
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.bits = {
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.pxx = IMX8MM_OTG1_SW_Pxx_REQ,
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.map = IMX8MM_OTG1_A53_DOMAIN,
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},
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.pgc = IMX8MM_PGC_OTG1,
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},
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[IMX8MM_POWER_DOMAIN_OTG2] = {
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.genpd = {
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.name = "usb-otg2",
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},
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.bits = {
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.pxx = IMX8MM_OTG2_SW_Pxx_REQ,
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.map = IMX8MM_OTG2_A53_DOMAIN,
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},
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.pgc = IMX8MM_PGC_OTG2,
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},
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[IMX8MM_POWER_DOMAIN_GPUMIX] = {
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.genpd = {
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.name = "gpumix",
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},
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.bits = {
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.pxx = IMX8MM_GPUMIX_SW_Pxx_REQ,
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.map = IMX8MM_GPUMIX_A53_DOMAIN,
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.hskreq = IMX8MM_GPUMIX_HSK_PWRDNREQN,
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.hskack = IMX8MM_GPUMIX_HSK_PWRDNACKN,
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},
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.pgc = IMX8MM_PGC_GPUMIX,
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},
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[IMX8MM_POWER_DOMAIN_GPU] = {
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.genpd = {
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.name = "gpu",
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},
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.bits = {
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.pxx = IMX8MM_GPU_SW_Pxx_REQ,
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.map = IMX8MM_GPU_A53_DOMAIN,
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.hskreq = IMX8MM_GPU_HSK_PWRDNREQN,
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.hskack = IMX8MM_GPU_HSK_PWRDNACKN,
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},
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.pgc = IMX8MM_PGC_GPU2D,
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},
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};
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static const struct regmap_range imx8mm_yes_ranges[] = {
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regmap_reg_range(GPC_LPCR_A_CORE_BSC,
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GPC_PU_PWRHSK),
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regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_MIPI),
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GPC_PGC_SR(IMX8MM_PGC_MIPI)),
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regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_PCIE),
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GPC_PGC_SR(IMX8MM_PGC_PCIE)),
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regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_OTG1),
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GPC_PGC_SR(IMX8MM_PGC_OTG1)),
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regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_OTG2),
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GPC_PGC_SR(IMX8MM_PGC_OTG2)),
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regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_DDR1),
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GPC_PGC_SR(IMX8MM_PGC_DDR1)),
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regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_GPU2D),
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GPC_PGC_SR(IMX8MM_PGC_GPU2D)),
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regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_GPUMIX),
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GPC_PGC_SR(IMX8MM_PGC_GPUMIX)),
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regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPUMIX),
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GPC_PGC_SR(IMX8MM_PGC_VPUMIX)),
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regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_GPU3D),
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GPC_PGC_SR(IMX8MM_PGC_GPU3D)),
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regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_DISPMIX),
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GPC_PGC_SR(IMX8MM_PGC_DISPMIX)),
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regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPUG1),
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GPC_PGC_SR(IMX8MM_PGC_VPUG1)),
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regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPUG2),
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GPC_PGC_SR(IMX8MM_PGC_VPUG2)),
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regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPUH1),
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GPC_PGC_SR(IMX8MM_PGC_VPUH1)),
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};
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static const struct regmap_access_table imx8mm_access_table = {
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.yes_ranges = imx8mm_yes_ranges,
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.n_yes_ranges = ARRAY_SIZE(imx8mm_yes_ranges),
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};
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static const struct imx_pgc_domain_data imx8mm_pgc_domain_data = {
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.domains = imx8mm_pgc_domains,
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.domains_num = ARRAY_SIZE(imx8mm_pgc_domains),
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.reg_access_table = &imx8mm_access_table,
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};
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static int imx_pgc_domain_probe(struct platform_device *pdev)
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{
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struct imx_pgc_domain *domain = pdev->dev.platform_data;
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@ -710,6 +877,7 @@ static int imx_gpcv2_probe(struct platform_device *pdev)
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static const struct of_device_id imx_gpcv2_dt_ids[] = {
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{ .compatible = "fsl,imx7d-gpc", .data = &imx7_pgc_domain_data, },
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{ .compatible = "fsl,imx8mm-gpc", .data = &imx8mm_pgc_domain_data, },
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{ .compatible = "fsl,imx8mq-gpc", .data = &imx8m_pgc_domain_data, },
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{ }
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};
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