Merge branch 'etnaviv/next' of https://git.pengutronix.de/git/lst/linux into drm-next
This time we've added support for reporting of GPU load via the common fdinfo format, as already supported by multiple other drivers. Improved diagnostic messages for MMU faults. And finally added experimental support for driving the VeriSilicon NPU cores, which are very close relatives to the GPU designs, so close in fact that they can run the same compute instruction set, but with a big NN-fabric/matrix/tensor execution array glued to the side. Signed-off-by: Dave Airlie <airlied@redhat.com> From: Lucas Stach <l.stach@pengutronix.de> Link: https://patchwork.freedesktop.org/patch/msgid/80ceb4eedf7d88e434deeb69607d5ce0a0759581.camel@pengutronix.de
This commit is contained in:
Dave Airlie
commit
48075a66fc
@ -22,6 +22,7 @@
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#include "etnaviv_gem.h"
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#include "etnaviv_mmu.h"
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#include "etnaviv_perfmon.h"
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#include "common.xml.h"
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/*
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* DRM operations:
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@ -56,6 +57,11 @@ static int etnaviv_open(struct drm_device *dev, struct drm_file *file)
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if (!ctx)
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return -ENOMEM;
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ret = xa_alloc_cyclic(&priv->active_contexts, &ctx->id, ctx,
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xa_limit_32b, &priv->next_context_id, GFP_KERNEL);
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if (ret < 0)
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goto out_free;
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ctx->mmu = etnaviv_iommu_context_init(priv->mmu_global,
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priv->cmdbuf_suballoc);
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if (!ctx->mmu) {
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@ -99,6 +105,8 @@ static void etnaviv_postclose(struct drm_device *dev, struct drm_file *file)
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etnaviv_iommu_context_put(ctx->mmu);
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xa_erase(&priv->active_contexts, ctx->id);
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kfree(ctx);
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}
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@ -468,7 +476,47 @@ static const struct drm_ioctl_desc etnaviv_ioctls[] = {
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ETNA_IOCTL(PM_QUERY_SIG, pm_query_sig, DRM_RENDER_ALLOW),
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};
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DEFINE_DRM_GEM_FOPS(fops);
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static void etnaviv_fop_show_fdinfo(struct seq_file *m, struct file *f)
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{
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struct drm_file *file = f->private_data;
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struct drm_device *dev = file->minor->dev;
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struct etnaviv_drm_private *priv = dev->dev_private;
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struct etnaviv_file_private *ctx = file->driver_priv;
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/*
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* For a description of the text output format used here, see
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* Documentation/gpu/drm-usage-stats.rst.
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*/
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seq_printf(m, "drm-driver:\t%s\n", dev->driver->name);
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seq_printf(m, "drm-client-id:\t%u\n", ctx->id);
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for (int i = 0; i < ETNA_MAX_PIPES; i++) {
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struct etnaviv_gpu *gpu = priv->gpu[i];
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char engine[10] = "UNK";
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int cur = 0;
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if (!gpu)
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continue;
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if (gpu->identity.features & chipFeatures_PIPE_2D)
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cur = snprintf(engine, sizeof(engine), "2D");
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if (gpu->identity.features & chipFeatures_PIPE_3D)
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cur = snprintf(engine + cur, sizeof(engine) - cur,
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"%s3D", cur ? "/" : "");
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if (gpu->identity.nn_core_count > 0)
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cur = snprintf(engine + cur, sizeof(engine) - cur,
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"%sNN", cur ? "/" : "");
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seq_printf(m, "drm-engine-%s:\t%llu ns\n", engine,
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ctx->sched_entity[i].elapsed_ns);
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}
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}
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static const struct file_operations fops = {
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.owner = THIS_MODULE,
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DRM_GEM_FOPS,
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.show_fdinfo = etnaviv_fop_show_fdinfo,
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};
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static const struct drm_driver etnaviv_drm_driver = {
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.driver_features = DRIVER_GEM | DRIVER_RENDER,
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@ -514,6 +562,8 @@ static int etnaviv_bind(struct device *dev)
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dma_set_max_seg_size(dev, SZ_2G);
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xa_init_flags(&priv->active_contexts, XA_FLAGS_ALLOC);
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mutex_init(&priv->gem_lock);
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INIT_LIST_HEAD(&priv->gem_list);
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priv->num_gpus = 0;
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@ -563,6 +613,8 @@ static void etnaviv_unbind(struct device *dev)
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etnaviv_cmdbuf_suballoc_destroy(priv->cmdbuf_suballoc);
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xa_destroy(&priv->active_contexts);
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drm->dev_private = NULL;
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kfree(priv);
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@ -12,6 +12,7 @@
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#include <linux/sizes.h>
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#include <linux/time64.h>
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#include <linux/types.h>
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#include <linux/xarray.h>
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#include <drm/drm_drv.h>
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#include <drm/drm_gem.h>
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@ -28,6 +29,7 @@ struct etnaviv_iommu_global;
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#define ETNAVIV_SOFTPIN_START_ADDRESS SZ_4M /* must be >= SUBALLOC_SIZE */
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struct etnaviv_file_private {
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int id;
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struct etnaviv_iommu_context *mmu;
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struct drm_sched_entity sched_entity[ETNA_MAX_PIPES];
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};
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@ -40,6 +42,9 @@ struct etnaviv_drm_private {
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struct etnaviv_cmdbuf_suballoc *cmdbuf_suballoc;
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struct etnaviv_iommu_global *mmu_global;
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struct xarray active_contexts;
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u32 next_context_id;
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/* list of GEM objects: */
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struct mutex gem_lock;
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struct list_head gem_list;
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@ -393,10 +393,11 @@ static void submit_cleanup(struct kref *kref)
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wake_up_all(&submit->gpu->fence_event);
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if (submit->out_fence) {
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/* first remove from IDR, so fence can not be found anymore */
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mutex_lock(&submit->gpu->fence_lock);
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idr_remove(&submit->gpu->fence_idr, submit->out_fence_id);
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mutex_unlock(&submit->gpu->fence_lock);
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/*
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* Remove from user fence array before dropping the reference,
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* so fence can not be found in lookup anymore.
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*/
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xa_erase(&submit->gpu->user_fences, submit->out_fence_id);
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dma_fence_put(submit->out_fence);
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}
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@ -773,6 +773,10 @@ int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
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goto fail;
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}
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if (gpu->identity.nn_core_count > 0)
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dev_warn(gpu->dev, "etnaviv has been instantiated on a NPU, "
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"for which the UAPI is still experimental\n");
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/* Exclude VG cores with FE2.0 */
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if (gpu->identity.features & chipFeatures_PIPE_VG &&
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gpu->identity.features & chipFeatures_FE20) {
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@ -957,6 +961,8 @@ int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m)
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gpu->identity.vertex_cache_size);
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seq_printf(m, "\t shader_core_count: %d\n",
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gpu->identity.shader_core_count);
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seq_printf(m, "\t nn_core_count: %d\n",
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gpu->identity.nn_core_count);
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seq_printf(m, "\t pixel_pipes: %d\n",
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gpu->identity.pixel_pipes);
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seq_printf(m, "\t vertex_output_buffer_size: %d\n",
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@ -1240,7 +1246,7 @@ int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
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* pretends we didn't find a fence in that case.
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*/
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rcu_read_lock();
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fence = idr_find(&gpu->fence_idr, id);
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fence = xa_load(&gpu->user_fences, id);
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if (fence)
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fence = dma_fence_get_rcu(fence);
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rcu_read_unlock();
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@ -1450,6 +1456,15 @@ static void sync_point_worker(struct work_struct *work)
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static void dump_mmu_fault(struct etnaviv_gpu *gpu)
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{
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static const char *fault_reasons[] = {
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"slave not present",
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"page not present",
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"write violation",
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"out of bounds",
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"read security violation",
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"write security violation",
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};
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u32 status_reg, status;
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int i;
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@ -1462,18 +1477,25 @@ static void dump_mmu_fault(struct etnaviv_gpu *gpu)
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dev_err_ratelimited(gpu->dev, "MMU fault status 0x%08x\n", status);
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for (i = 0; i < 4; i++) {
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const char *reason = "unknown";
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u32 address_reg;
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u32 mmu_status;
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if (!(status & (VIVS_MMUv2_STATUS_EXCEPTION0__MASK << (i * 4))))
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mmu_status = (status >> (i * 4)) & VIVS_MMUv2_STATUS_EXCEPTION0__MASK;
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if (!mmu_status)
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continue;
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if ((mmu_status - 1) < ARRAY_SIZE(fault_reasons))
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reason = fault_reasons[mmu_status - 1];
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if (gpu->sec_mode == ETNA_SEC_NONE)
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address_reg = VIVS_MMUv2_EXCEPTION_ADDR(i);
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else
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address_reg = VIVS_MMUv2_SEC_EXCEPTION_ADDR;
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dev_err_ratelimited(gpu->dev, "MMU %d fault addr 0x%08x\n", i,
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gpu_read(gpu, address_reg));
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dev_err_ratelimited(gpu->dev,
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"MMU %d fault (%s) addr 0x%08x\n",
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i, reason, gpu_read(gpu, address_reg));
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}
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}
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@ -1629,7 +1651,6 @@ static int etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu)
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return etnaviv_gpu_clk_disable(gpu);
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}
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#ifdef CONFIG_PM
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static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu)
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{
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int ret;
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@ -1645,7 +1666,6 @@ static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu)
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return 0;
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}
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#endif
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static int
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etnaviv_gpu_cooling_get_max_state(struct thermal_cooling_device *cdev,
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@ -1713,18 +1733,17 @@ static int etnaviv_gpu_bind(struct device *dev, struct device *master,
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if (ret)
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goto out_workqueue;
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#ifdef CONFIG_PM
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ret = pm_runtime_get_sync(gpu->dev);
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#else
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ret = etnaviv_gpu_clk_enable(gpu);
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#endif
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if (IS_ENABLED(CONFIG_PM))
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ret = pm_runtime_get_sync(gpu->dev);
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else
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ret = etnaviv_gpu_clk_enable(gpu);
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if (ret < 0)
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goto out_sched;
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gpu->drm = drm;
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gpu->fence_context = dma_fence_context_alloc(1);
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idr_init(&gpu->fence_idr);
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xa_init_flags(&gpu->user_fences, XA_FLAGS_ALLOC);
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spin_lock_init(&gpu->fence_spinlock);
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INIT_WORK(&gpu->sync_point_work, sync_point_worker);
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@ -1761,12 +1780,12 @@ static void etnaviv_gpu_unbind(struct device *dev, struct device *master,
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etnaviv_sched_fini(gpu);
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#ifdef CONFIG_PM
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pm_runtime_get_sync(gpu->dev);
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pm_runtime_put_sync_suspend(gpu->dev);
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#else
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etnaviv_gpu_hw_suspend(gpu);
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#endif
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if (IS_ENABLED(CONFIG_PM)) {
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pm_runtime_get_sync(gpu->dev);
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pm_runtime_put_sync_suspend(gpu->dev);
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} else {
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etnaviv_gpu_hw_suspend(gpu);
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}
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if (gpu->mmu_context)
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etnaviv_iommu_context_put(gpu->mmu_context);
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@ -1778,7 +1797,7 @@ static void etnaviv_gpu_unbind(struct device *dev, struct device *master,
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}
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gpu->drm = NULL;
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idr_destroy(&gpu->fence_idr);
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xa_destroy(&gpu->user_fences);
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if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
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thermal_cooling_device_unregister(gpu->cooling);
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@ -1810,7 +1829,7 @@ static int etnaviv_gpu_platform_probe(struct platform_device *pdev)
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gpu->dev = &pdev->dev;
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mutex_init(&gpu->lock);
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mutex_init(&gpu->fence_lock);
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mutex_init(&gpu->sched_lock);
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/* Map registers: */
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gpu->mmio = devm_platform_ioremap_resource(pdev, 0);
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@ -1880,7 +1899,6 @@ static int etnaviv_gpu_platform_remove(struct platform_device *pdev)
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return 0;
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}
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#ifdef CONFIG_PM
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static int etnaviv_gpu_rpm_suspend(struct device *dev)
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{
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struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
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@ -1923,18 +1941,16 @@ static int etnaviv_gpu_rpm_resume(struct device *dev)
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return 0;
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}
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#endif
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static const struct dev_pm_ops etnaviv_gpu_pm_ops = {
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SET_RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume,
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NULL)
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RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume, NULL)
|
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};
|
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|
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struct platform_driver etnaviv_gpu_driver = {
|
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.driver = {
|
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.name = "etnaviv-gpu",
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.owner = THIS_MODULE,
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.pm = &etnaviv_gpu_pm_ops,
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.pm = pm_ptr(&etnaviv_gpu_pm_ops),
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.of_match_table = etnaviv_gpu_match,
|
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},
|
||||
.probe = etnaviv_gpu_platform_probe,
|
||||
|
||||
@ -51,6 +51,9 @@ struct etnaviv_chip_identity {
|
||||
/* Number of shader cores. */
|
||||
u32 shader_core_count;
|
||||
|
||||
/* Number of Neural Network cores. */
|
||||
u32 nn_core_count;
|
||||
|
||||
/* Size of the vertex cache. */
|
||||
u32 vertex_cache_size;
|
||||
|
||||
@ -100,6 +103,7 @@ struct etnaviv_gpu {
|
||||
struct etnaviv_chip_identity identity;
|
||||
enum etnaviv_sec_mode sec_mode;
|
||||
struct workqueue_struct *wq;
|
||||
struct mutex sched_lock;
|
||||
struct drm_gpu_scheduler sched;
|
||||
bool initialized;
|
||||
bool fe_running;
|
||||
@ -117,8 +121,8 @@ struct etnaviv_gpu {
|
||||
u32 idle_mask;
|
||||
|
||||
/* Fencing support */
|
||||
struct mutex fence_lock;
|
||||
struct idr fence_idr;
|
||||
struct xarray user_fences;
|
||||
u32 next_user_fence;
|
||||
u32 next_fence;
|
||||
u32 completed_fence;
|
||||
wait_queue_head_t fence_event;
|
||||
|
||||
@ -16,6 +16,7 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
|
||||
.register_max = 64,
|
||||
.thread_count = 128,
|
||||
.shader_core_count = 1,
|
||||
.nn_core_count = 0,
|
||||
.vertex_cache_size = 8,
|
||||
.vertex_output_buffer_size = 1024,
|
||||
.pixel_pipes = 1,
|
||||
@ -47,6 +48,7 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
|
||||
.register_max = 64,
|
||||
.thread_count = 512,
|
||||
.shader_core_count = 2,
|
||||
.nn_core_count = 0,
|
||||
.vertex_cache_size = 16,
|
||||
.vertex_output_buffer_size = 1024,
|
||||
.pixel_pipes = 1,
|
||||
@ -78,6 +80,7 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
|
||||
.register_max = 64,
|
||||
.thread_count = 512,
|
||||
.shader_core_count = 2,
|
||||
.nn_core_count = 0,
|
||||
.vertex_cache_size = 16,
|
||||
.vertex_output_buffer_size = 1024,
|
||||
.pixel_pipes = 1,
|
||||
@ -140,6 +143,7 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
|
||||
.register_max = 64,
|
||||
.thread_count = 1024,
|
||||
.shader_core_count = 4,
|
||||
.nn_core_count = 0,
|
||||
.vertex_cache_size = 16,
|
||||
.vertex_output_buffer_size = 1024,
|
||||
.pixel_pipes = 2,
|
||||
@ -161,6 +165,38 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
|
||||
.minor_features10 = 0x90044250,
|
||||
.minor_features11 = 0x00000024,
|
||||
},
|
||||
{
|
||||
.model = 0x8000,
|
||||
.revision = 0x7120,
|
||||
.product_id = 0x45080009,
|
||||
.customer_id = 0x88,
|
||||
.eco_id = 0,
|
||||
.stream_count = 8,
|
||||
.register_max = 64,
|
||||
.thread_count = 256,
|
||||
.shader_core_count = 1,
|
||||
.nn_core_count = 8,
|
||||
.vertex_cache_size = 16,
|
||||
.vertex_output_buffer_size = 1024,
|
||||
.pixel_pipes = 1,
|
||||
.instruction_count = 512,
|
||||
.num_constants = 320,
|
||||
.buffer_size = 0,
|
||||
.varyings_count = 16,
|
||||
.features = 0xe0287cac,
|
||||
.minor_features0 = 0xc1799eff,
|
||||
.minor_features1 = 0xfefbfadb,
|
||||
.minor_features2 = 0xeb9d6fbf,
|
||||
.minor_features3 = 0xedfffced,
|
||||
.minor_features4 = 0xd30dafc7,
|
||||
.minor_features5 = 0x7b5ac333,
|
||||
.minor_features6 = 0xfc8ee200,
|
||||
.minor_features7 = 0x03fffa6f,
|
||||
.minor_features8 = 0x00fe0ef0,
|
||||
.minor_features9 = 0x0088003c,
|
||||
.minor_features10 = 0x108048c0,
|
||||
.minor_features11 = 0x00000010,
|
||||
},
|
||||
};
|
||||
|
||||
bool etnaviv_fill_identity_from_hwdb(struct etnaviv_gpu *gpu)
|
||||
|
||||
@ -97,24 +97,24 @@ static const struct drm_sched_backend_ops etnaviv_sched_ops = {
|
||||
|
||||
int etnaviv_sched_push_job(struct etnaviv_gem_submit *submit)
|
||||
{
|
||||
int ret = 0;
|
||||
struct etnaviv_gpu *gpu = submit->gpu;
|
||||
int ret;
|
||||
|
||||
/*
|
||||
* Hold the fence lock across the whole operation to avoid jobs being
|
||||
* Hold the sched lock across the whole operation to avoid jobs being
|
||||
* pushed out of order with regard to their sched fence seqnos as
|
||||
* allocated in drm_sched_job_arm.
|
||||
*/
|
||||
mutex_lock(&submit->gpu->fence_lock);
|
||||
mutex_lock(&gpu->sched_lock);
|
||||
|
||||
drm_sched_job_arm(&submit->sched_job);
|
||||
|
||||
submit->out_fence = dma_fence_get(&submit->sched_job.s_fence->finished);
|
||||
submit->out_fence_id = idr_alloc_cyclic(&submit->gpu->fence_idr,
|
||||
submit->out_fence, 0,
|
||||
INT_MAX, GFP_KERNEL);
|
||||
if (submit->out_fence_id < 0) {
|
||||
ret = xa_alloc_cyclic(&gpu->user_fences, &submit->out_fence_id,
|
||||
submit->out_fence, xa_limit_32b,
|
||||
&gpu->next_user_fence, GFP_KERNEL);
|
||||
if (ret < 0) {
|
||||
drm_sched_job_cleanup(&submit->sched_job);
|
||||
ret = -ENOMEM;
|
||||
goto out_unlock;
|
||||
}
|
||||
|
||||
@ -124,7 +124,7 @@ int etnaviv_sched_push_job(struct etnaviv_gem_submit *submit)
|
||||
drm_sched_entity_push_job(&submit->sched_job);
|
||||
|
||||
out_unlock:
|
||||
mutex_unlock(&submit->gpu->fence_lock);
|
||||
mutex_unlock(&gpu->sched_lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -8,17 +8,17 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng
|
||||
git clone git://0x04.net/rules-ng-ng
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- state.xml ( 26666 bytes, from 2019-12-20 21:20:35)
|
||||
- common.xml ( 35468 bytes, from 2018-02-10 13:09:26)
|
||||
- common_3d.xml ( 15058 bytes, from 2019-12-28 20:02:03)
|
||||
- state_hi.xml ( 30552 bytes, from 2019-12-28 20:02:48)
|
||||
- copyright.xml ( 1597 bytes, from 2018-02-10 13:09:26)
|
||||
- state_2d.xml ( 51552 bytes, from 2018-02-10 13:09:26)
|
||||
- state_3d.xml ( 83098 bytes, from 2019-12-28 20:02:03)
|
||||
- state_blt.xml ( 14252 bytes, from 2019-10-20 19:59:15)
|
||||
- state_vg.xml ( 5975 bytes, from 2018-02-10 13:09:26)
|
||||
- state.xml ( 27198 bytes, from 2022-04-22 10:35:24)
|
||||
- common.xml ( 35468 bytes, from 2020-10-28 12:56:03)
|
||||
- common_3d.xml ( 15058 bytes, from 2020-10-28 12:56:03)
|
||||
- state_hi.xml ( 34804 bytes, from 2022-12-02 09:06:28)
|
||||
- copyright.xml ( 1597 bytes, from 2020-10-28 12:56:03)
|
||||
- state_2d.xml ( 51552 bytes, from 2020-10-28 12:56:03)
|
||||
- state_3d.xml ( 84445 bytes, from 2022-11-15 15:59:38)
|
||||
- state_blt.xml ( 14424 bytes, from 2022-11-07 11:18:41)
|
||||
- state_vg.xml ( 5975 bytes, from 2020-10-28 12:56:03)
|
||||
|
||||
Copyright (C) 2012-2019 by the following authors:
|
||||
Copyright (C) 2012-2022 by the following authors:
|
||||
- Wladimir J. van der Laan <laanwj@gmail.com>
|
||||
- Christian Gmeiner <christian.gmeiner@gmail.com>
|
||||
- Lucas Stach <l.stach@pengutronix.de>
|
||||
@ -321,16 +321,16 @@ DEALINGS IN THE SOFTWARE.
|
||||
#define VIVS_MMUv2_CONFIGURATION_ADDRESS(x) (((x) << VIVS_MMUv2_CONFIGURATION_ADDRESS__SHIFT) & VIVS_MMUv2_CONFIGURATION_ADDRESS__MASK)
|
||||
|
||||
#define VIVS_MMUv2_STATUS 0x00000188
|
||||
#define VIVS_MMUv2_STATUS_EXCEPTION0__MASK 0x00000003
|
||||
#define VIVS_MMUv2_STATUS_EXCEPTION0__MASK 0x0000000f
|
||||
#define VIVS_MMUv2_STATUS_EXCEPTION0__SHIFT 0
|
||||
#define VIVS_MMUv2_STATUS_EXCEPTION0(x) (((x) << VIVS_MMUv2_STATUS_EXCEPTION0__SHIFT) & VIVS_MMUv2_STATUS_EXCEPTION0__MASK)
|
||||
#define VIVS_MMUv2_STATUS_EXCEPTION1__MASK 0x00000030
|
||||
#define VIVS_MMUv2_STATUS_EXCEPTION1__MASK 0x000000f0
|
||||
#define VIVS_MMUv2_STATUS_EXCEPTION1__SHIFT 4
|
||||
#define VIVS_MMUv2_STATUS_EXCEPTION1(x) (((x) << VIVS_MMUv2_STATUS_EXCEPTION1__SHIFT) & VIVS_MMUv2_STATUS_EXCEPTION1__MASK)
|
||||
#define VIVS_MMUv2_STATUS_EXCEPTION2__MASK 0x00000300
|
||||
#define VIVS_MMUv2_STATUS_EXCEPTION2__MASK 0x00000f00
|
||||
#define VIVS_MMUv2_STATUS_EXCEPTION2__SHIFT 8
|
||||
#define VIVS_MMUv2_STATUS_EXCEPTION2(x) (((x) << VIVS_MMUv2_STATUS_EXCEPTION2__SHIFT) & VIVS_MMUv2_STATUS_EXCEPTION2__MASK)
|
||||
#define VIVS_MMUv2_STATUS_EXCEPTION3__MASK 0x00003000
|
||||
#define VIVS_MMUv2_STATUS_EXCEPTION3__MASK 0x0000f000
|
||||
#define VIVS_MMUv2_STATUS_EXCEPTION3__SHIFT 12
|
||||
#define VIVS_MMUv2_STATUS_EXCEPTION3(x) (((x) << VIVS_MMUv2_STATUS_EXCEPTION3__SHIFT) & VIVS_MMUv2_STATUS_EXCEPTION3__MASK)
|
||||
|
||||
@ -465,7 +465,13 @@ DEALINGS IN THE SOFTWARE.
|
||||
#define VIVS_MC_PROFILE_CONFIG0 0x00000470
|
||||
#define VIVS_MC_PROFILE_CONFIG0_FE__MASK 0x000000ff
|
||||
#define VIVS_MC_PROFILE_CONFIG0_FE__SHIFT 0
|
||||
#define VIVS_MC_PROFILE_CONFIG0_FE_DRAW_COUNT 0x0000000a
|
||||
#define VIVS_MC_PROFILE_CONFIG0_FE_OUT_VERTEX_COUNT 0x0000000b
|
||||
#define VIVS_MC_PROFILE_CONFIG0_FE_CACHE_MISS_COUNT 0x0000000c
|
||||
#define VIVS_MC_PROFILE_CONFIG0_FE_RESET 0x0000000f
|
||||
#define VIVS_MC_PROFILE_CONFIG0_FE_CACHE_LK_COUNT 0x00000010
|
||||
#define VIVS_MC_PROFILE_CONFIG0_FE_STALL_COUNT 0x00000011
|
||||
#define VIVS_MC_PROFILE_CONFIG0_FE_PROCESS_COUNT 0x00000012
|
||||
#define VIVS_MC_PROFILE_CONFIG0_DE__MASK 0x0000ff00
|
||||
#define VIVS_MC_PROFILE_CONFIG0_DE__SHIFT 8
|
||||
#define VIVS_MC_PROFILE_CONFIG0_DE_RESET 0x00000f00
|
||||
@ -499,11 +505,14 @@ DEALINGS IN THE SOFTWARE.
|
||||
#define VIVS_MC_PROFILE_CONFIG1_PA_DEPTH_CLIPPED_COUNTER 0x00000006
|
||||
#define VIVS_MC_PROFILE_CONFIG1_PA_TRIVIAL_REJECTED_COUNTER 0x00000007
|
||||
#define VIVS_MC_PROFILE_CONFIG1_PA_CULLED_COUNTER 0x00000008
|
||||
#define VIVS_MC_PROFILE_CONFIG1_PA_DROPED_PRIM_COUNTER 0x00000009
|
||||
#define VIVS_MC_PROFILE_CONFIG1_PA_FRUSTUM_CLIPPED_PRIM_COUNTER 0x0000000a
|
||||
#define VIVS_MC_PROFILE_CONFIG1_PA_RESET 0x0000000f
|
||||
#define VIVS_MC_PROFILE_CONFIG1_SE__MASK 0x0000ff00
|
||||
#define VIVS_MC_PROFILE_CONFIG1_SE__SHIFT 8
|
||||
#define VIVS_MC_PROFILE_CONFIG1_SE_CULLED_TRIANGLE_COUNT 0x00000000
|
||||
#define VIVS_MC_PROFILE_CONFIG1_SE_CULLED_LINES_COUNT 0x00000100
|
||||
#define VIVS_MC_PROFILE_CONFIG1_SE_TRIVIAL_REJECTED_LINE_COUNT 0x00000400
|
||||
#define VIVS_MC_PROFILE_CONFIG1_SE_RESET 0x00000f00
|
||||
#define VIVS_MC_PROFILE_CONFIG1_RA__MASK 0x00ff0000
|
||||
#define VIVS_MC_PROFILE_CONFIG1_RA__SHIFT 16
|
||||
@ -515,6 +524,8 @@ DEALINGS IN THE SOFTWARE.
|
||||
#define VIVS_MC_PROFILE_CONFIG1_RA_PREFETCH_CACHE_MISS_COUNTER 0x000a0000
|
||||
#define VIVS_MC_PROFILE_CONFIG1_RA_CULLED_QUAD_COUNT 0x000b0000
|
||||
#define VIVS_MC_PROFILE_CONFIG1_RA_RESET 0x000f0000
|
||||
#define VIVS_MC_PROFILE_CONFIG1_RA_PIPE_HZ_CACHE_MISS_COUNTER 0x00110000
|
||||
#define VIVS_MC_PROFILE_CONFIG1_RA_PREFETCH_HZ_CACHE_MISS_COUNTER 0x00120000
|
||||
#define VIVS_MC_PROFILE_CONFIG1_TX__MASK 0xff000000
|
||||
#define VIVS_MC_PROFILE_CONFIG1_TX__SHIFT 24
|
||||
#define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_BILINEAR_REQUESTS 0x00000000
|
||||
@ -535,13 +546,48 @@ DEALINGS IN THE SOFTWARE.
|
||||
#define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_PIPELINE 0x00000001
|
||||
#define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_IP 0x00000002
|
||||
#define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_8B_FROM_PIPELINE 0x00000003
|
||||
#define VIVS_MC_PROFILE_CONFIG2_MC_RESET 0x0000000f
|
||||
#define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_SENTOUT_FROM_COLORPIPE 0x00000004
|
||||
#define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_FROM_COLORPIPE 0x00000005
|
||||
#define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_DEPTHPIPE 0x00000007
|
||||
#define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_SENTOUT_FROM_DEPTHPIPE 0x00000008
|
||||
#define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_8B_FROM_DEPTHPIPE 0x00000009
|
||||
#define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_SENTOUT_FROM_DEPTHPIPE 0x0000000a
|
||||
#define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_FROM_DEPTHPIPE 0x0000000b
|
||||
#define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_OTHERS 0x0000000c
|
||||
#define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_8B_FROM_OTHERS 0x0000000d
|
||||
#define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_FROM_OTHERS 0x0000000e
|
||||
#define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_FROM_OTHERS 0x0000000f
|
||||
#define VIVS_MC_PROFILE_CONFIG2_MC_FE_READ_BANDWIDTH 0x00000015
|
||||
#define VIVS_MC_PROFILE_CONFIG2_MC_MMU_READ_BANDWIDTH 0x00000016
|
||||
#define VIVS_MC_PROFILE_CONFIG2_MC_BLT_READ_BANDWIDTH 0x00000017
|
||||
#define VIVS_MC_PROFILE_CONFIG2_MC_SH0_READ_BANDWIDTH 0x00000018
|
||||
#define VIVS_MC_PROFILE_CONFIG2_MC_SH1_READ_BANDWIDTH 0x00000019
|
||||
#define VIVS_MC_PROFILE_CONFIG2_MC_PE_WRITE_BANDWIDTH 0x0000001a
|
||||
#define VIVS_MC_PROFILE_CONFIG2_MC_BLT_WRITE_BANDWIDTH 0x0000001b
|
||||
#define VIVS_MC_PROFILE_CONFIG2_MC_SH0_WRITE_BANDWIDTH 0x0000001c
|
||||
#define VIVS_MC_PROFILE_CONFIG2_MC_SH1_WRITE_BANDWIDTH 0x0000001d
|
||||
#define VIVS_MC_PROFILE_CONFIG2_HI__MASK 0x0000ff00
|
||||
#define VIVS_MC_PROFILE_CONFIG2_HI__SHIFT 8
|
||||
#define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_READ_REQUEST_STALLED 0x00000000
|
||||
#define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_WRITE_REQUEST_STALLED 0x00000100
|
||||
#define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_WRITE_DATA_STALLED 0x00000200
|
||||
#define VIVS_MC_PROFILE_CONFIG2_HI_RESET 0x00000f00
|
||||
#define VIVS_MC_PROFILE_CONFIG2_L2__MASK 0x00ff0000
|
||||
#define VIVS_MC_PROFILE_CONFIG2_L2__SHIFT 16
|
||||
#define VIVS_MC_PROFILE_CONFIG2_L2_TOTAL_AXI0_READ_REQUEST_COUNT 0x00000000
|
||||
#define VIVS_MC_PROFILE_CONFIG2_L2_TOTAL_AXI0_WRITE_REQUEST_COUNT 0x00040000
|
||||
#define VIVS_MC_PROFILE_CONFIG2_L2_TOTAL_AXI1_WRITE_REQUEST_COUNT 0x00050000
|
||||
#define VIVS_MC_PROFILE_CONFIG2_L2_TOTAL_READ_TRANSACTIONS_REQUEST_BY_AXI0 0x00080000
|
||||
#define VIVS_MC_PROFILE_CONFIG2_L2_TOTAL_READ_TRANSACTIONS_REQUEST_BY_AXI1 0x00090000
|
||||
#define VIVS_MC_PROFILE_CONFIG2_L2_TOTAL_WRITE_TRANSACTIONS_REQUEST_BY_AXI0 0x000c0000
|
||||
#define VIVS_MC_PROFILE_CONFIG2_L2_TOTAL_WRITE_TRANSACTIONS_REQUEST_BY_AXI1 0x000d0000
|
||||
#define VIVS_MC_PROFILE_CONFIG2_L2_RESET 0x000f0000
|
||||
#define VIVS_MC_PROFILE_CONFIG2_L2_AXI0_MINMAX_LATENCY 0x00100000
|
||||
#define VIVS_MC_PROFILE_CONFIG2_L2_AXI0_TOTAL_LATENCY 0x00110000
|
||||
#define VIVS_MC_PROFILE_CONFIG2_L2_AXI0_TOTAL_REQUEST_COUNT 0x00120000
|
||||
#define VIVS_MC_PROFILE_CONFIG2_L2_AXI1_MINMAX_LATENCY 0x00130000
|
||||
#define VIVS_MC_PROFILE_CONFIG2_L2_AXI1_TOTAL_LATENCY 0x00140000
|
||||
#define VIVS_MC_PROFILE_CONFIG2_L2_AXI1_TOTAL_REQUEST_COUNT 0x00150000
|
||||
#define VIVS_MC_PROFILE_CONFIG2_BLT__MASK 0xff000000
|
||||
#define VIVS_MC_PROFILE_CONFIG2_BLT__SHIFT 24
|
||||
#define VIVS_MC_PROFILE_CONFIG2_BLT_UNK0 0x00000000
|
||||
@ -566,5 +612,13 @@ DEALINGS IN THE SOFTWARE.
|
||||
|
||||
#define VIVS_MC_PROFILE_L2_READ 0x00000564
|
||||
|
||||
#define VIVS_MC_MC_LATENCY_RESET 0x00000568
|
||||
|
||||
#define VIVS_MC_MC_AXI_MAX_MIN_LATENCY 0x0000056c
|
||||
|
||||
#define VIVS_MC_MC_AXI_TOTAL_LATENCY 0x00000570
|
||||
|
||||
#define VIVS_MC_MC_AXI_SAMPLE_COUNT 0x00000574
|
||||
|
||||
|
||||
#endif /* STATE_HI_XML */
|
||||
|
||||
@ -906,6 +906,12 @@ drm_sched_get_cleanup_job(struct drm_gpu_scheduler *sched)
|
||||
|
||||
spin_unlock(&sched->job_list_lock);
|
||||
|
||||
if (job) {
|
||||
job->entity->elapsed_ns += ktime_to_ns(
|
||||
ktime_sub(job->s_fence->finished.timestamp,
|
||||
job->s_fence->scheduled.timestamp));
|
||||
}
|
||||
|
||||
return job;
|
||||
}
|
||||
|
||||
|
||||
@ -228,6 +228,13 @@ struct drm_sched_entity {
|
||||
*/
|
||||
struct rb_node rb_tree_node;
|
||||
|
||||
/**
|
||||
* @elapsed_ns:
|
||||
*
|
||||
* Records the amount of time where jobs from this entity were active
|
||||
* on the GPU.
|
||||
*/
|
||||
uint64_t elapsed_ns;
|
||||
};
|
||||
|
||||
/**
|
||||
|
||||
Loading…
Reference in New Issue
Block a user