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drm/ttm: nuke memory type flags

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It's not supported to specify more than one of those flags.
So it never made sense to make this a flag in the first place.

Nuke the flags and specify directly which memory type to use.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Link: https://patchwork.freedesktop.org/patch/389826/?series=81551&rev=1
This commit is contained in:
Christian König 2020-09-10 13:39:41 +02:00
parent e03d342c62
commit 48e07c23cb
16 changed files with 150 additions and 192 deletions
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24
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
View File

@ -136,8 +136,8 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
places[c].fpfn = 0; places[c].fpfn = 0;
places[c].lpfn = 0; places[c].lpfn = 0;
places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | places[c].mem_type = TTM_PL_VRAM;
TTM_PL_FLAG_VRAM; places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED;
if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
places[c].lpfn = visible_pfn; places[c].lpfn = visible_pfn;
@ -152,7 +152,8 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
if (domain & AMDGPU_GEM_DOMAIN_GTT) { if (domain & AMDGPU_GEM_DOMAIN_GTT) {
places[c].fpfn = 0; places[c].fpfn = 0;
places[c].lpfn = 0; places[c].lpfn = 0;
places[c].flags = TTM_PL_FLAG_TT; places[c].mem_type = TTM_PL_TT;
places[c].flags = 0;
if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
places[c].flags |= TTM_PL_FLAG_WC | places[c].flags |= TTM_PL_FLAG_WC |
TTM_PL_FLAG_UNCACHED; TTM_PL_FLAG_UNCACHED;
@ -164,7 +165,8 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
if (domain & AMDGPU_GEM_DOMAIN_CPU) { if (domain & AMDGPU_GEM_DOMAIN_CPU) {
places[c].fpfn = 0; places[c].fpfn = 0;
places[c].lpfn = 0; places[c].lpfn = 0;
places[c].flags = TTM_PL_FLAG_SYSTEM; places[c].mem_type = TTM_PL_SYSTEM;
places[c].flags = 0;
if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
places[c].flags |= TTM_PL_FLAG_WC | places[c].flags |= TTM_PL_FLAG_WC |
TTM_PL_FLAG_UNCACHED; TTM_PL_FLAG_UNCACHED;
@ -176,28 +178,32 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
if (domain & AMDGPU_GEM_DOMAIN_GDS) { if (domain & AMDGPU_GEM_DOMAIN_GDS) {
places[c].fpfn = 0; places[c].fpfn = 0;
places[c].lpfn = 0; places[c].lpfn = 0;
places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GDS; places[c].mem_type = AMDGPU_PL_GDS;
places[c].flags = TTM_PL_FLAG_UNCACHED;
c++; c++;
} }
if (domain & AMDGPU_GEM_DOMAIN_GWS) { if (domain & AMDGPU_GEM_DOMAIN_GWS) {
places[c].fpfn = 0; places[c].fpfn = 0;
places[c].lpfn = 0; places[c].lpfn = 0;
places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GWS; places[c].mem_type = AMDGPU_PL_GWS;
places[c].flags = TTM_PL_FLAG_UNCACHED;
c++; c++;
} }
if (domain & AMDGPU_GEM_DOMAIN_OA) { if (domain & AMDGPU_GEM_DOMAIN_OA) {
places[c].fpfn = 0; places[c].fpfn = 0;
places[c].lpfn = 0; places[c].lpfn = 0;
places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_OA; places[c].mem_type = AMDGPU_PL_OA;
places[c].flags = TTM_PL_FLAG_UNCACHED;
c++; c++;
} }
if (!c) { if (!c) {
places[c].fpfn = 0; places[c].fpfn = 0;
places[c].lpfn = 0; places[c].lpfn = 0;
places[c].flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; places[c].mem_type = TTM_PL_SYSTEM;
places[c].flags = TTM_PL_MASK_CACHING;
c++; c++;
} }
@ -591,7 +597,7 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev,
amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0); amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0);
if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED && if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&
bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) { bo->tbo.mem.mem_type == TTM_PL_VRAM) {
struct dma_fence *fence; struct dma_fence *fence;
r = amdgpu_fill_buffer(bo, 0, bo->tbo.base.resv, &fence); r = amdgpu_fill_buffer(bo, 0, bo->tbo.base.resv, &fence);

13
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
View File

@ -88,7 +88,8 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
static const struct ttm_place placements = { static const struct ttm_place placements = {
.fpfn = 0, .fpfn = 0,
.lpfn = 0, .lpfn = 0,
.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM .mem_type = TTM_PL_SYSTEM,
.flags = TTM_PL_MASK_CACHING
}; };
/* Don't handle scatter gather BOs */ /* Don't handle scatter gather BOs */
@ -533,7 +534,8 @@ static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict,
placement.busy_placement = &placements; placement.busy_placement = &placements;
placements.fpfn = 0; placements.fpfn = 0;
placements.lpfn = 0; placements.lpfn = 0;
placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; placements.mem_type = TTM_PL_TT;
placements.flags = TTM_PL_MASK_CACHING;
r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx); r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
if (unlikely(r)) { if (unlikely(r)) {
pr_err("Failed to find GTT space for blit from VRAM\n"); pr_err("Failed to find GTT space for blit from VRAM\n");
@ -589,7 +591,8 @@ static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict,
placement.busy_placement = &placements; placement.busy_placement = &placements;
placements.fpfn = 0; placements.fpfn = 0;
placements.lpfn = 0; placements.lpfn = 0;
placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; placements.mem_type = TTM_PL_TT;
placements.flags = TTM_PL_MASK_CACHING;
r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx); r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
if (unlikely(r)) { if (unlikely(r)) {
pr_err("Failed to find GTT space for blit to VRAM\n"); pr_err("Failed to find GTT space for blit to VRAM\n");
@ -1171,8 +1174,8 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
placement.busy_placement = &placements; placement.busy_placement = &placements;
placements.fpfn = 0; placements.fpfn = 0;
placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT; placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) | placements.mem_type = TTM_PL_TT;
TTM_PL_FLAG_TT; placements.flags = bo->mem.placement;
r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx); r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
if (unlikely(r)) if (unlikely(r))

4
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
View File

@ -32,10 +32,6 @@
#define AMDGPU_PL_GWS (TTM_PL_PRIV + 1) #define AMDGPU_PL_GWS (TTM_PL_PRIV + 1)
#define AMDGPU_PL_OA (TTM_PL_PRIV + 2) #define AMDGPU_PL_OA (TTM_PL_PRIV + 2)
#define AMDGPU_PL_FLAG_GDS (TTM_PL_FLAG_PRIV << 0)
#define AMDGPU_PL_FLAG_GWS (TTM_PL_FLAG_PRIV << 1)
#define AMDGPU_PL_FLAG_OA (TTM_PL_FLAG_PRIV << 2)
#define AMDGPU_GTT_MAX_TRANSFER_SIZE 512 #define AMDGPU_GTT_MAX_TRANSFER_SIZE 512
#define AMDGPU_GTT_NUM_TRANSFER_WINDOWS 2 #define AMDGPU_GTT_NUM_TRANSFER_WINDOWS 2

15
drivers/gpu/drm/drm_gem_vram_helper.c
View File

@ -145,21 +145,18 @@ static void drm_gem_vram_placement(struct drm_gem_vram_object *gbo,
gbo->placement.placement = gbo->placements; gbo->placement.placement = gbo->placements;
gbo->placement.busy_placement = gbo->placements; gbo->placement.busy_placement = gbo->placements;
if (pl_flag & DRM_GEM_VRAM_PL_FLAG_VRAM) if (pl_flag & DRM_GEM_VRAM_PL_FLAG_VRAM) {
gbo->placements[c].mem_type = TTM_PL_VRAM;
gbo->placements[c++].flags = TTM_PL_FLAG_WC | gbo->placements[c++].flags = TTM_PL_FLAG_WC |
TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_UNCACHED |
TTM_PL_FLAG_VRAM |
invariant_flags; invariant_flags;
}
if (pl_flag & DRM_GEM_VRAM_PL_FLAG_SYSTEM) if (pl_flag & DRM_GEM_VRAM_PL_FLAG_SYSTEM || !c) {
gbo->placements[c].mem_type = TTM_PL_SYSTEM;
gbo->placements[c++].flags = TTM_PL_MASK_CACHING | gbo->placements[c++].flags = TTM_PL_MASK_CACHING |
TTM_PL_FLAG_SYSTEM |
invariant_flags;
if (!c)
gbo->placements[c++].flags = TTM_PL_MASK_CACHING |
TTM_PL_FLAG_SYSTEM |
invariant_flags; invariant_flags;
}
gbo->placement.num_placement = c; gbo->placement.num_placement = c;
gbo->placement.num_busy_placement = c; gbo->placement.num_busy_placement = c;

24
drivers/gpu/drm/nouveau/nouveau_bo.c
View File

@ -345,12 +345,18 @@ set_placement_list(struct ttm_place *pl, unsigned *n, uint32_t domain,
{ {
*n = 0; *n = 0;
if (domain & NOUVEAU_GEM_DOMAIN_VRAM) if (domain & NOUVEAU_GEM_DOMAIN_VRAM) {
pl[(*n)++].flags = TTM_PL_FLAG_VRAM | flags; pl[*n].mem_type = TTM_PL_VRAM;
if (domain & NOUVEAU_GEM_DOMAIN_GART) pl[(*n)++].flags = flags;
pl[(*n)++].flags = TTM_PL_FLAG_TT | flags; }
if (domain & NOUVEAU_GEM_DOMAIN_CPU) if (domain & NOUVEAU_GEM_DOMAIN_GART) {
pl[(*n)++].flags = TTM_PL_FLAG_SYSTEM | flags; pl[*n].mem_type = TTM_PL_TT;
pl[(*n)++].flags = flags;
}
if (domain & NOUVEAU_GEM_DOMAIN_CPU) {
pl[*n].mem_type = TTM_PL_SYSTEM;
pl[(*n)++].flags = flags;
}
} }
static void static void
@ -882,7 +888,8 @@ nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
struct ttm_place placement_memtype = { struct ttm_place placement_memtype = {
.fpfn = 0, .fpfn = 0,
.lpfn = 0, .lpfn = 0,
.flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING .mem_type = TTM_PL_TT,
.flags = TTM_PL_MASK_CACHING
}; };
struct ttm_placement placement; struct ttm_placement placement;
struct ttm_resource tmp_reg; struct ttm_resource tmp_reg;
@ -919,7 +926,8 @@ nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
struct ttm_place placement_memtype = { struct ttm_place placement_memtype = {
.fpfn = 0, .fpfn = 0,
.lpfn = 0, .lpfn = 0,
.flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING .mem_type = TTM_PL_TT,
.flags = TTM_PL_MASK_CACHING
}; };
struct ttm_placement placement; struct ttm_placement placement;
struct ttm_resource tmp_reg; struct ttm_resource tmp_reg;

26
drivers/gpu/drm/qxl/qxl_object.c
View File

@ -64,16 +64,24 @@ void qxl_ttm_placement_from_domain(struct qxl_bo *qbo, u32 domain, bool pinned)
qbo->placement.placement = qbo->placements; qbo->placement.placement = qbo->placements;
qbo->placement.busy_placement = qbo->placements; qbo->placement.busy_placement = qbo->placements;
if (domain == QXL_GEM_DOMAIN_VRAM) if (domain == QXL_GEM_DOMAIN_VRAM) {
qbo->placements[c++].flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_VRAM | pflag; qbo->placements[c].mem_type = TTM_PL_VRAM;
if (domain == QXL_GEM_DOMAIN_SURFACE) { qbo->placements[c++].flags = TTM_PL_FLAG_CACHED | pflag;
qbo->placements[c++].flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_PRIV | pflag; }
qbo->placements[c++].flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_VRAM | pflag; if (domain == QXL_GEM_DOMAIN_SURFACE) {
qbo->placements[c].mem_type = TTM_PL_PRIV;
qbo->placements[c++].flags = TTM_PL_FLAG_CACHED | pflag;
qbo->placements[c].mem_type = TTM_PL_VRAM;
qbo->placements[c++].flags = TTM_PL_FLAG_CACHED | pflag;
}
if (domain == QXL_GEM_DOMAIN_CPU) {
qbo->placements[c].mem_type = TTM_PL_SYSTEM;
qbo->placements[c++].flags = TTM_PL_MASK_CACHING | pflag;
}
if (!c) {
qbo->placements[c].mem_type = TTM_PL_SYSTEM;
qbo->placements[c++].flags = TTM_PL_MASK_CACHING;
} }
if (domain == QXL_GEM_DOMAIN_CPU)
qbo->placements[c++].flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM | pflag;
if (!c)
qbo->placements[c++].flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
qbo->placement.num_placement = c; qbo->placement.num_placement = c;
qbo->placement.num_busy_placement = c; qbo->placement.num_busy_placement = c;
for (i = 0; i < c; ++i) { for (i = 0; i < c; ++i) {

3
drivers/gpu/drm/qxl/qxl_ttm.c
View File

@ -55,7 +55,8 @@ static void qxl_evict_flags(struct ttm_buffer_object *bo,
static const struct ttm_place placements = { static const struct ttm_place placements = {
.fpfn = 0, .fpfn = 0,
.lpfn = 0, .lpfn = 0,
.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM .mem_type = TTM_PL_SYSTEM,
.flags = TTM_PL_MASK_CACHING
}; };
if (!qxl_ttm_bo_is_qxl_bo(bo)) { if (!qxl_ttm_bo_is_qxl_bo(bo)) {

42
drivers/gpu/drm/radeon/radeon_object.c
View File

@ -112,58 +112,58 @@ void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size) { rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size) {
rbo->placements[c].fpfn = rbo->placements[c].fpfn =
rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
rbo->placements[c].mem_type = TTM_PL_VRAM;
rbo->placements[c++].flags = TTM_PL_FLAG_WC | rbo->placements[c++].flags = TTM_PL_FLAG_WC |
TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_UNCACHED;
TTM_PL_FLAG_VRAM;
} }
rbo->placements[c].fpfn = 0; rbo->placements[c].fpfn = 0;
rbo->placements[c].mem_type = TTM_PL_VRAM;
rbo->placements[c++].flags = TTM_PL_FLAG_WC | rbo->placements[c++].flags = TTM_PL_FLAG_WC |
TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_UNCACHED;
TTM_PL_FLAG_VRAM;
} }
if (domain & RADEON_GEM_DOMAIN_GTT) { if (domain & RADEON_GEM_DOMAIN_GTT) {
if (rbo->flags & RADEON_GEM_GTT_UC) { if (rbo->flags & RADEON_GEM_GTT_UC) {
rbo->placements[c].fpfn = 0; rbo->placements[c].fpfn = 0;
rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED | rbo->placements[c].mem_type = TTM_PL_TT;
TTM_PL_FLAG_TT; rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED;
} else if ((rbo->flags & RADEON_GEM_GTT_WC) || } else if ((rbo->flags & RADEON_GEM_GTT_WC) ||
(rbo->rdev->flags & RADEON_IS_AGP)) { (rbo->rdev->flags & RADEON_IS_AGP)) {
rbo->placements[c].fpfn = 0; rbo->placements[c].fpfn = 0;
rbo->placements[c].mem_type = TTM_PL_TT;
rbo->placements[c++].flags = TTM_PL_FLAG_WC | rbo->placements[c++].flags = TTM_PL_FLAG_WC |
TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_UNCACHED;
TTM_PL_FLAG_TT;
} else { } else {
rbo->placements[c].fpfn = 0; rbo->placements[c].fpfn = 0;
rbo->placements[c++].flags = TTM_PL_FLAG_CACHED | rbo->placements[c].mem_type = TTM_PL_TT;
TTM_PL_FLAG_TT; rbo->placements[c++].flags = TTM_PL_FLAG_CACHED;
} }
} }
if (domain & RADEON_GEM_DOMAIN_CPU) { if (domain & RADEON_GEM_DOMAIN_CPU) {
if (rbo->flags & RADEON_GEM_GTT_UC) { if (rbo->flags & RADEON_GEM_GTT_UC) {
rbo->placements[c].fpfn = 0; rbo->placements[c].fpfn = 0;
rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED | rbo->placements[c].mem_type = TTM_PL_SYSTEM;
TTM_PL_FLAG_SYSTEM; rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED;
} else if ((rbo->flags & RADEON_GEM_GTT_WC) || } else if ((rbo->flags & RADEON_GEM_GTT_WC) ||
rbo->rdev->flags & RADEON_IS_AGP) { rbo->rdev->flags & RADEON_IS_AGP) {
rbo->placements[c].fpfn = 0; rbo->placements[c].fpfn = 0;
rbo->placements[c].mem_type = TTM_PL_SYSTEM;
rbo->placements[c++].flags = TTM_PL_FLAG_WC | rbo->placements[c++].flags = TTM_PL_FLAG_WC |
TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_UNCACHED;
TTM_PL_FLAG_SYSTEM;
} else { } else {
rbo->placements[c].fpfn = 0; rbo->placements[c].fpfn = 0;
rbo->placements[c++].flags = TTM_PL_FLAG_CACHED | rbo->placements[c].mem_type = TTM_PL_SYSTEM;
TTM_PL_FLAG_SYSTEM; rbo->placements[c++].flags = TTM_PL_FLAG_CACHED;
} }
} }
if (!c) { if (!c) {
rbo->placements[c].fpfn = 0; rbo->placements[c].fpfn = 0;
rbo->placements[c++].flags = TTM_PL_MASK_CACHING | rbo->placements[c].mem_type = TTM_PL_SYSTEM;
TTM_PL_FLAG_SYSTEM; rbo->placements[c++].flags = TTM_PL_MASK_CACHING;
} }
rbo->placement.num_placement = c; rbo->placement.num_placement = c;
@ -171,7 +171,7 @@ void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
for (i = 0; i < c; ++i) { for (i = 0; i < c; ++i) {
if ((rbo->flags & RADEON_GEM_CPU_ACCESS) && if ((rbo->flags & RADEON_GEM_CPU_ACCESS) &&
(rbo->placements[i].flags & TTM_PL_FLAG_VRAM) && (rbo->placements[i].mem_type == TTM_PL_VRAM) &&
!rbo->placements[i].fpfn) !rbo->placements[i].fpfn)
rbo->placements[i].lpfn = rbo->placements[i].lpfn =
rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
@ -360,7 +360,7 @@ int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
radeon_ttm_placement_from_domain(bo, domain); radeon_ttm_placement_from_domain(bo, domain);
for (i = 0; i < bo->placement.num_placement; i++) { for (i = 0; i < bo->placement.num_placement; i++) {
/* force to pin into visible video ram */ /* force to pin into visible video ram */
if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) && if ((bo->placements[i].mem_type == TTM_PL_VRAM) &&
!(bo->flags & RADEON_GEM_NO_CPU_ACCESS) && !(bo->flags & RADEON_GEM_NO_CPU_ACCESS) &&
(!max_offset || max_offset > bo->rdev->mc.visible_vram_size)) (!max_offset || max_offset > bo->rdev->mc.visible_vram_size))
bo->placements[i].lpfn = bo->placements[i].lpfn =
@ -824,7 +824,7 @@ int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT; lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
for (i = 0; i < rbo->placement.num_placement; i++) { for (i = 0; i < rbo->placement.num_placement; i++) {
/* Force into visible VRAM */ /* Force into visible VRAM */
if ((rbo->placements[i].flags & TTM_PL_FLAG_VRAM) && if ((rbo->placements[i].mem_type == TTM_PL_VRAM) &&
(!rbo->placements[i].lpfn || rbo->placements[i].lpfn > lpfn)) (!rbo->placements[i].lpfn || rbo->placements[i].lpfn > lpfn))
rbo->placements[i].lpfn = lpfn; rbo->placements[i].lpfn = lpfn;
} }

11
drivers/gpu/drm/radeon/radeon_ttm.c
View File

@ -88,7 +88,8 @@ static void radeon_evict_flags(struct ttm_buffer_object *bo,
static const struct ttm_place placements = { static const struct ttm_place placements = {
.fpfn = 0, .fpfn = 0,
.lpfn = 0, .lpfn = 0,
.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM .mem_type = TTM_PL_SYSTEM,
.flags = TTM_PL_MASK_CACHING
}; };
struct radeon_bo *rbo; struct radeon_bo *rbo;
@ -119,7 +120,7 @@ static void radeon_evict_flags(struct ttm_buffer_object *bo,
RADEON_GEM_DOMAIN_GTT); RADEON_GEM_DOMAIN_GTT);
rbo->placement.num_busy_placement = 0; rbo->placement.num_busy_placement = 0;
for (i = 0; i < rbo->placement.num_placement; i++) { for (i = 0; i < rbo->placement.num_placement; i++) {
if (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) { if (rbo->placements[i].mem_type == TTM_PL_VRAM) {
if (rbo->placements[i].fpfn < fpfn) if (rbo->placements[i].fpfn < fpfn)
rbo->placements[i].fpfn = fpfn; rbo->placements[i].fpfn = fpfn;
} else { } else {
@ -224,7 +225,8 @@ static int radeon_move_vram_ram(struct ttm_buffer_object *bo,
placement.busy_placement = &placements; placement.busy_placement = &placements;
placements.fpfn = 0; placements.fpfn = 0;
placements.lpfn = 0; placements.lpfn = 0;
placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; placements.mem_type = TTM_PL_TT;
placements.flags = TTM_PL_MASK_CACHING;
r = ttm_bo_mem_space(bo, &placement, &tmp_mem, &ctx); r = ttm_bo_mem_space(bo, &placement, &tmp_mem, &ctx);
if (unlikely(r)) { if (unlikely(r)) {
return r; return r;
@ -269,7 +271,8 @@ static int radeon_move_ram_vram(struct ttm_buffer_object *bo,
placement.busy_placement = &placements; placement.busy_placement = &placements;
placements.fpfn = 0; placements.fpfn = 0;
placements.lpfn = 0; placements.lpfn = 0;
placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; placements.mem_type = TTM_PL_TT;
placements.flags = TTM_PL_MASK_CACHING;
r = ttm_bo_mem_space(bo, &placement, &tmp_mem, &ctx); r = ttm_bo_mem_space(bo, &placement, &tmp_mem, &ctx);
if (unlikely(r)) { if (unlikely(r)) {
return r; return r;

86
drivers/gpu/drm/ttm/ttm_bo.c
View File

@ -64,34 +64,18 @@ static void ttm_bo_default_destroy(struct ttm_buffer_object *bo)
kfree(bo); kfree(bo);
} }
static inline int ttm_mem_type_from_place(const struct ttm_place *place,
uint32_t *mem_type)
{
int pos;
pos = ffs(place->flags & TTM_PL_MASK_MEM);
if (unlikely(!pos))
return -EINVAL;
*mem_type = pos - 1;
return 0;
}
static void ttm_bo_mem_space_debug(struct ttm_buffer_object *bo, static void ttm_bo_mem_space_debug(struct ttm_buffer_object *bo,
struct ttm_placement *placement) struct ttm_placement *placement)
{ {
struct drm_printer p = drm_debug_printer(TTM_PFX); struct drm_printer p = drm_debug_printer(TTM_PFX);
int i, ret, mem_type;
struct ttm_resource_manager *man; struct ttm_resource_manager *man;
int i, mem_type;
drm_printf(&p, "No space for %p (%lu pages, %luK, %luM)\n", drm_printf(&p, "No space for %p (%lu pages, %luK, %luM)\n",
bo, bo->mem.num_pages, bo->mem.size >> 10, bo, bo->mem.num_pages, bo->mem.size >> 10,
bo->mem.size >> 20); bo->mem.size >> 20);
for (i = 0; i < placement->num_placement; i++) { for (i = 0; i < placement->num_placement; i++) {
ret = ttm_mem_type_from_place(&placement->placement[i], mem_type = placement->placement[i].mem_type;
&mem_type);
if (ret)
return;
drm_printf(&p, " placement[%d]=0x%08X (%d)\n", drm_printf(&p, " placement[%d]=0x%08X (%d)\n",
i, placement->placement[i].flags, mem_type); i, placement->placement[i].flags, mem_type);
man = ttm_manager_type(bo->bdev, mem_type); man = ttm_manager_type(bo->bdev, mem_type);
@ -125,12 +109,6 @@ static struct kobj_type ttm_bo_glob_kobj_type = {
.default_attrs = ttm_bo_global_attrs .default_attrs = ttm_bo_global_attrs
}; };
static inline uint32_t ttm_bo_type_flags(unsigned type)
{
return 1 << (type);
}
static void ttm_bo_add_mem_to_lru(struct ttm_buffer_object *bo, static void ttm_bo_add_mem_to_lru(struct ttm_buffer_object *bo,
struct ttm_resource *mem) struct ttm_resource *mem)
{ {
@ -910,25 +888,6 @@ static uint32_t ttm_bo_select_caching(struct ttm_resource_manager *man,
return result; return result;
} }
static bool ttm_bo_mt_compatible(struct ttm_resource_manager *man,
uint32_t mem_type,
const struct ttm_place *place,
uint32_t *masked_placement)
{
uint32_t cur_flags = ttm_bo_type_flags(mem_type);
if ((cur_flags & place->flags & TTM_PL_MASK_MEM) == 0)
return false;
if ((place->flags & man->available_caching) == 0)
return false;
cur_flags |= (place->flags & man->available_caching);
*masked_placement = cur_flags;
return true;
}
/** /**
* ttm_bo_mem_placement - check if placement is compatible * ttm_bo_mem_placement - check if placement is compatible
* @bo: BO to find memory for * @bo: BO to find memory for
@ -946,30 +905,21 @@ static int ttm_bo_mem_placement(struct ttm_buffer_object *bo,
struct ttm_operation_ctx *ctx) struct ttm_operation_ctx *ctx)
{ {
struct ttm_bo_device *bdev = bo->bdev; struct ttm_bo_device *bdev = bo->bdev;
uint32_t mem_type = TTM_PL_SYSTEM;
struct ttm_resource_manager *man; struct ttm_resource_manager *man;
uint32_t cur_flags = 0; uint32_t cur_flags = 0;
int ret;
ret = ttm_mem_type_from_place(place, &mem_type); man = ttm_manager_type(bdev, place->mem_type);
if (ret)
return ret;
man = ttm_manager_type(bdev, mem_type);
if (!man || !ttm_resource_manager_used(man)) if (!man || !ttm_resource_manager_used(man))
return -EBUSY; return -EBUSY;
if (!ttm_bo_mt_compatible(man, mem_type, place, &cur_flags)) if ((place->flags & man->available_caching) == 0)
return -EBUSY; return -EBUSY;
cur_flags = place->flags & man->available_caching;
cur_flags = ttm_bo_select_caching(man, bo->mem.placement, cur_flags); cur_flags = ttm_bo_select_caching(man, bo->mem.placement, cur_flags);
/* cur_flags |= place->flags & ~TTM_PL_MASK_CACHING;
* Use the access and other non-mapping-related flag bits from
* the memory placement flags to the current flags
*/
ttm_flag_masked(&cur_flags, place->flags, ~TTM_PL_MASK_MEMTYPE);
mem->mem_type = mem_type; mem->mem_type = place->mem_type;
mem->placement = cur_flags; mem->placement = cur_flags;
spin_lock(&ttm_bo_glob.lru_lock); spin_lock(&ttm_bo_glob.lru_lock);
@ -1006,10 +956,8 @@ int ttm_bo_mem_space(struct ttm_buffer_object *bo,
struct ttm_resource_manager *man; struct ttm_resource_manager *man;
ret = ttm_bo_mem_placement(bo, place, mem, ctx); ret = ttm_bo_mem_placement(bo, place, mem, ctx);
if (ret == -EBUSY)
continue;
if (ret) if (ret)
goto error; continue;
type_found = true; type_found = true;
ret = ttm_resource_alloc(bo, place, mem); ret = ttm_resource_alloc(bo, place, mem);
@ -1034,10 +982,8 @@ int ttm_bo_mem_space(struct ttm_buffer_object *bo,
const struct ttm_place *place = &placement->busy_placement[i]; const struct ttm_place *place = &placement->busy_placement[i];
ret = ttm_bo_mem_placement(bo, place, mem, ctx); ret = ttm_bo_mem_placement(bo, place, mem, ctx);
if (ret == -EBUSY)
continue;
if (ret) if (ret)
goto error; continue;
type_found = true; type_found = true;
ret = ttm_bo_mem_force_space(bo, place, mem, ctx); ret = ttm_bo_mem_force_space(bo, place, mem, ctx);
@ -1108,7 +1054,7 @@ static bool ttm_bo_places_compat(const struct ttm_place *places,
*new_flags = heap->flags; *new_flags = heap->flags;
if ((*new_flags & mem->placement & TTM_PL_MASK_CACHING) && if ((*new_flags & mem->placement & TTM_PL_MASK_CACHING) &&
(*new_flags & mem->placement & TTM_PL_MASK_MEM) && (mem->mem_type == heap->mem_type) &&
(!(*new_flags & TTM_PL_FLAG_CONTIGUOUS) || (!(*new_flags & TTM_PL_FLAG_CONTIGUOUS) ||
(mem->placement & TTM_PL_FLAG_CONTIGUOUS))) (mem->placement & TTM_PL_FLAG_CONTIGUOUS)))
return true; return true;
@ -1163,12 +1109,8 @@ int ttm_bo_validate(struct ttm_buffer_object *bo,
if (ret) if (ret)
return ret; return ret;
} else { } else {
/* bo->mem.placement &= TTM_PL_MASK_CACHING;
* Use the access and other non-mapping-related flag bits from bo->mem.placement |= new_flags & ~TTM_PL_MASK_CACHING;
* the compatible memory placement flags to the active flags
*/
ttm_flag_masked(&bo->mem.placement, new_flags,
~TTM_PL_MASK_MEMTYPE);
} }
/* /*
* We might need to add a TTM. * We might need to add a TTM.
@ -1236,7 +1178,7 @@ int ttm_bo_init_reserved(struct ttm_bo_device *bdev,
bo->mem.bus.offset = 0; bo->mem.bus.offset = 0;
bo->mem.bus.addr = NULL; bo->mem.bus.addr = NULL;
bo->moving = NULL; bo->moving = NULL;
bo->mem.placement = (TTM_PL_FLAG_SYSTEM | TTM_PL_FLAG_CACHED); bo->mem.placement = TTM_PL_FLAG_CACHED;
bo->acc_size = acc_size; bo->acc_size = acc_size;
bo->sg = sg; bo->sg = sg;
if (resv) { if (resv) {
@ -1627,7 +1569,7 @@ int ttm_bo_swapout(struct ttm_bo_global *glob, struct ttm_operation_ctx *ctx)
evict_mem = bo->mem; evict_mem = bo->mem;
evict_mem.mm_node = NULL; evict_mem.mm_node = NULL;
evict_mem.placement = TTM_PL_FLAG_SYSTEM | TTM_PL_FLAG_CACHED; evict_mem.placement = TTM_PL_FLAG_CACHED;
evict_mem.mem_type = TTM_PL_SYSTEM; evict_mem.mem_type = TTM_PL_SYSTEM;
ret = ttm_bo_handle_move_mem(bo, &evict_mem, true, &ctx); ret = ttm_bo_handle_move_mem(bo, &evict_mem, true, &ctx);

2
drivers/gpu/drm/ttm/ttm_bo_util.c
View File

@ -69,8 +69,6 @@ int ttm_bo_move_ttm(struct ttm_buffer_object *bo,
ttm_tt_unbind(bo->bdev, ttm); ttm_tt_unbind(bo->bdev, ttm);
ttm_bo_free_old_node(bo); ttm_bo_free_old_node(bo);
ttm_flag_masked(&old_mem->placement, TTM_PL_FLAG_SYSTEM,
TTM_PL_MASK_MEM);
old_mem->mem_type = TTM_PL_SYSTEM; old_mem->mem_type = TTM_PL_SYSTEM;
} }

1
drivers/gpu/drm/vmwgfx/vmwgfx_bo.c
View File

@ -354,6 +354,7 @@ void vmw_bo_pin_reserved(struct vmw_buffer_object *vbo, bool pin)
pl.fpfn = 0; pl.fpfn = 0;
pl.lpfn = 0; pl.lpfn = 0;
pl.mem_type = bo->mem.mem_type;
pl.flags = bo->mem.placement; pl.flags = bo->mem.placement;
if (pin) if (pin)
pl.flags |= TTM_PL_FLAG_NO_EVICT; pl.flags |= TTM_PL_FLAG_NO_EVICT;

2
drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
View File

@ -82,9 +82,7 @@
VMWGFX_NUM_GB_SCREEN_TARGET) VMWGFX_NUM_GB_SCREEN_TARGET)
#define VMW_PL_GMR (TTM_PL_PRIV + 0) #define VMW_PL_GMR (TTM_PL_PRIV + 0)
#define VMW_PL_FLAG_GMR (TTM_PL_FLAG_PRIV << 0)
#define VMW_PL_MOB (TTM_PL_PRIV + 1) #define VMW_PL_MOB (TTM_PL_PRIV + 1)
#define VMW_PL_FLAG_MOB (TTM_PL_FLAG_PRIV << 1)
#define VMW_RES_CONTEXT ttm_driver_type0 #define VMW_RES_CONTEXT ttm_driver_type0
#define VMW_RES_SURFACE ttm_driver_type1 #define VMW_RES_SURFACE ttm_driver_type1

63
drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c
View File

@ -33,49 +33,57 @@
static const struct ttm_place vram_placement_flags = { static const struct ttm_place vram_placement_flags = {
.fpfn = 0, .fpfn = 0,
.lpfn = 0, .lpfn = 0,
.flags = TTM_PL_FLAG_VRAM | TTM_PL_FLAG_CACHED .mem_type = TTM_PL_VRAM,
.flags = TTM_PL_FLAG_CACHED
}; };
static const struct ttm_place vram_ne_placement_flags = { static const struct ttm_place vram_ne_placement_flags = {
.fpfn = 0, .fpfn = 0,
.lpfn = 0, .lpfn = 0,
.flags = TTM_PL_FLAG_VRAM | TTM_PL_FLAG_CACHED | TTM_PL_FLAG_NO_EVICT .mem_type = TTM_PL_VRAM,
.flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_NO_EVICT
}; };
static const struct ttm_place sys_placement_flags = { static const struct ttm_place sys_placement_flags = {
.fpfn = 0, .fpfn = 0,
.lpfn = 0, .lpfn = 0,
.flags = TTM_PL_FLAG_SYSTEM | TTM_PL_FLAG_CACHED .mem_type = TTM_PL_SYSTEM,
.flags = TTM_PL_FLAG_CACHED
}; };
static const struct ttm_place sys_ne_placement_flags = { static const struct ttm_place sys_ne_placement_flags = {
.fpfn = 0, .fpfn = 0,
.lpfn = 0, .lpfn = 0,
.flags = TTM_PL_FLAG_SYSTEM | TTM_PL_FLAG_CACHED | TTM_PL_FLAG_NO_EVICT .mem_type = TTM_PL_SYSTEM,
.flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_NO_EVICT
}; };
static const struct ttm_place gmr_placement_flags = { static const struct ttm_place gmr_placement_flags = {
.fpfn = 0, .fpfn = 0,
.lpfn = 0, .lpfn = 0,
.flags = VMW_PL_FLAG_GMR | TTM_PL_FLAG_CACHED .mem_type = VMW_PL_GMR,
.flags = TTM_PL_FLAG_CACHED
}; };
static const struct ttm_place gmr_ne_placement_flags = { static const struct ttm_place gmr_ne_placement_flags = {
.fpfn = 0, .fpfn = 0,
.lpfn = 0, .lpfn = 0,
.flags = VMW_PL_FLAG_GMR | TTM_PL_FLAG_CACHED | TTM_PL_FLAG_NO_EVICT .mem_type = VMW_PL_GMR,
.flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_NO_EVICT
}; };
static const struct ttm_place mob_placement_flags = { static const struct ttm_place mob_placement_flags = {
.fpfn = 0, .fpfn = 0,
.lpfn = 0, .lpfn = 0,
.flags = VMW_PL_FLAG_MOB | TTM_PL_FLAG_CACHED .mem_type = VMW_PL_MOB,
.flags = TTM_PL_FLAG_CACHED
}; };
static const struct ttm_place mob_ne_placement_flags = { static const struct ttm_place mob_ne_placement_flags = {
.fpfn = 0, .fpfn = 0,
.lpfn = 0, .lpfn = 0,
.flags = VMW_PL_FLAG_MOB | TTM_PL_FLAG_CACHED | TTM_PL_FLAG_NO_EVICT .mem_type = VMW_PL_MOB,
.flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_NO_EVICT
}; };
struct ttm_placement vmw_vram_placement = { struct ttm_placement vmw_vram_placement = {
@ -89,11 +97,13 @@ static const struct ttm_place vram_gmr_placement_flags[] = {
{ {
.fpfn = 0, .fpfn = 0,
.lpfn = 0, .lpfn = 0,
.flags = TTM_PL_FLAG_VRAM | TTM_PL_FLAG_CACHED .mem_type = TTM_PL_VRAM,
.flags = TTM_PL_FLAG_CACHED
}, { }, {
.fpfn = 0, .fpfn = 0,
.lpfn = 0, .lpfn = 0,
.flags = VMW_PL_FLAG_GMR | TTM_PL_FLAG_CACHED .mem_type = VMW_PL_GMR,
.flags = TTM_PL_FLAG_CACHED
} }
}; };
@ -101,11 +111,13 @@ static const struct ttm_place gmr_vram_placement_flags[] = {
{ {
.fpfn = 0, .fpfn = 0,
.lpfn = 0, .lpfn = 0,
.flags = VMW_PL_FLAG_GMR | TTM_PL_FLAG_CACHED .mem_type = VMW_PL_GMR,
.flags = TTM_PL_FLAG_CACHED
}, { }, {
.fpfn = 0, .fpfn = 0,
.lpfn = 0, .lpfn = 0,
.flags = TTM_PL_FLAG_VRAM | TTM_PL_FLAG_CACHED .mem_type = TTM_PL_VRAM,
.flags = TTM_PL_FLAG_CACHED
} }
}; };
@ -120,12 +132,14 @@ static const struct ttm_place vram_gmr_ne_placement_flags[] = {
{ {
.fpfn = 0, .fpfn = 0,
.lpfn = 0, .lpfn = 0,
.flags = TTM_PL_FLAG_VRAM | TTM_PL_FLAG_CACHED | .mem_type = TTM_PL_VRAM,
.flags = TTM_PL_FLAG_CACHED |
TTM_PL_FLAG_NO_EVICT TTM_PL_FLAG_NO_EVICT
}, { }, {
.fpfn = 0, .fpfn = 0,
.lpfn = 0, .lpfn = 0,
.flags = VMW_PL_FLAG_GMR | TTM_PL_FLAG_CACHED | .mem_type = VMW_PL_GMR,
.flags = TTM_PL_FLAG_CACHED |
TTM_PL_FLAG_NO_EVICT TTM_PL_FLAG_NO_EVICT
} }
}; };
@ -169,19 +183,23 @@ static const struct ttm_place evictable_placement_flags[] = {
{ {
.fpfn = 0, .fpfn = 0,
.lpfn = 0, .lpfn = 0,
.flags = TTM_PL_FLAG_SYSTEM | TTM_PL_FLAG_CACHED .mem_type = TTM_PL_SYSTEM,
.flags = TTM_PL_FLAG_CACHED
}, { }, {
.fpfn = 0, .fpfn = 0,
.lpfn = 0, .lpfn = 0,
.flags = TTM_PL_FLAG_VRAM | TTM_PL_FLAG_CACHED .mem_type = TTM_PL_VRAM,
.flags = TTM_PL_FLAG_CACHED
}, { }, {
.fpfn = 0, .fpfn = 0,
.lpfn = 0, .lpfn = 0,
.flags = VMW_PL_FLAG_GMR | TTM_PL_FLAG_CACHED .mem_type = VMW_PL_GMR,
.flags = TTM_PL_FLAG_CACHED
}, { }, {
.fpfn = 0, .fpfn = 0,
.lpfn = 0, .lpfn = 0,
.flags = VMW_PL_FLAG_MOB | TTM_PL_FLAG_CACHED .mem_type = VMW_PL_MOB,
.flags = TTM_PL_FLAG_CACHED
} }
}; };
@ -189,15 +207,18 @@ static const struct ttm_place nonfixed_placement_flags[] = {
{ {
.fpfn = 0, .fpfn = 0,
.lpfn = 0, .lpfn = 0,
.flags = TTM_PL_FLAG_SYSTEM | TTM_PL_FLAG_CACHED .mem_type = TTM_PL_SYSTEM,
.flags = TTM_PL_FLAG_CACHED
}, { }, {
.fpfn = 0, .fpfn = 0,
.lpfn = 0, .lpfn = 0,
.flags = VMW_PL_FLAG_GMR | TTM_PL_FLAG_CACHED .mem_type = VMW_PL_GMR,
.flags = TTM_PL_FLAG_CACHED
}, { }, {
.fpfn = 0, .fpfn = 0,
.lpfn = 0, .lpfn = 0,
.flags = VMW_PL_FLAG_MOB | TTM_PL_FLAG_CACHED .mem_type = VMW_PL_MOB,
.flags = TTM_PL_FLAG_CACHED
} }
}; };

17
include/drm/ttm/ttm_bo_driver.h
View File

@ -393,23 +393,6 @@ struct ttm_lru_bulk_move {
struct ttm_lru_bulk_move_pos swap[TTM_MAX_BO_PRIORITY]; struct ttm_lru_bulk_move_pos swap[TTM_MAX_BO_PRIORITY];
}; };
/**
* ttm_flag_masked
*
* @old: Pointer to the result and original value.
* @new: New value of bits.
* @mask: Mask of bits to change.
*
* Convenience function to change a number of bits identified by a mask.
*/
static inline uint32_t
ttm_flag_masked(uint32_t *old, uint32_t new, uint32_t mask)
{
*old ^= (*old ^ new) & mask;
return *old;
}
/* /*
* ttm_bo.c * ttm_bo.c
*/ */

9
include/drm/ttm/ttm_placement.h
View File

@ -42,12 +42,6 @@
#define TTM_PL_VRAM 2 #define TTM_PL_VRAM 2
#define TTM_PL_PRIV 3 #define TTM_PL_PRIV 3
#define TTM_PL_FLAG_SYSTEM (1 << TTM_PL_SYSTEM)
#define TTM_PL_FLAG_TT (1 << TTM_PL_TT)
#define TTM_PL_FLAG_VRAM (1 << TTM_PL_VRAM)
#define TTM_PL_FLAG_PRIV (1 << TTM_PL_PRIV)
#define TTM_PL_MASK_MEM 0x0000FFFF
/* /*
* Other flags that affects data placement. * Other flags that affects data placement.
* TTM_PL_FLAG_CACHED indicates cache-coherent mappings * TTM_PL_FLAG_CACHED indicates cache-coherent mappings
@ -71,8 +65,6 @@
TTM_PL_FLAG_UNCACHED | \ TTM_PL_FLAG_UNCACHED | \
TTM_PL_FLAG_WC) TTM_PL_FLAG_WC)
#define TTM_PL_MASK_MEMTYPE (TTM_PL_MASK_MEM | TTM_PL_MASK_CACHING)
/** /**
* struct ttm_place * struct ttm_place
* *
@ -85,6 +77,7 @@
struct ttm_place { struct ttm_place {
unsigned fpfn; unsigned fpfn;
unsigned lpfn; unsigned lpfn;
uint32_t mem_type;
uint32_t flags; uint32_t flags;
}; };