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drm/amd/display: Disable idle optimization when PSR is enabled

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[Why]
Idle optimization and PSR conflict each other. If both enabled
at the same time, display flickering will be observed.

[How]
Disable idle optimization when PSR is enabled.

Signed-off-by: Zhan Liu <zhan.liu@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Zhan Liu 2020-08-28 14:18:56 -04:00 committed by Alex Deucher
parent bd80d584cd
commit 48e48e5984
1 changed files with 10 additions and 13 deletions
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23
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
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@ -690,26 +690,23 @@ void dcn30_program_dmdata_engine(struct pipe_ctx *pipe_ctx)
bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)
{
unsigned int surface_size;
if (!dc->ctx->dmub_srv)
return false;
if (enable) {
if (dc->current_state
&& dc->current_state->stream_count == 1 // single display only
&& dc->current_state->stream_status[0].plane_count == 1 // single surface only
&& dc->current_state->stream_status[0].plane_states[0]->address.page_table_base.quad_part == 0 // no VM
// Only 8 and 16 bit formats
&& dc->current_state->stream_status[0].plane_states[0]->format <= SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F
&& dc->current_state->stream_status[0].plane_states[0]->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB8888) {
surface_size = dc->current_state->stream_status[0].plane_states[0]->plane_size.surface_pitch *
dc->current_state->stream_status[0].plane_states[0]->plane_size.surface_size.height *
(dc->current_state->stream_status[0].plane_states[0]->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4);
if (dc->current_state) {
int i;
/* First, check no-memory-requests case */
for (i = 0; i < dc->current_state->stream_count; i++) {
if (dc->current_state->stream_status[i]
.plane_count)
/* Fail eligibility on a visible stream */
break;
}
}
/* No applicable optimizations */
return false;
}