From 48f034120d1e43cf15af9e913e2656dc1bed1c65 Mon Sep 17 00:00:00 2001 From: Jonathan Cameron Date: Sun, 8 May 2022 18:56:55 +0100 Subject: [PATCH] iio: gyro: fxas210002c: Fix alignment for DMA safety MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 3aafe923987cb4a15e16f03c6185ed4b6a78ca00 ] ____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Updated the comment to 'may' require. Fixes: a0701b6263ae ("iio: gyro: add core driver for fxas21002c") Signed-off-by: Jonathan Cameron Reviewed-by: Rui Miguel Silva Acked-by: Nuno Sá Link: https://lore.kernel.org/r/20220508175712.647246-76-jic23@kernel.org Signed-off-by: Sasha Levin --- drivers/iio/gyro/fxas21002c_core.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/iio/gyro/fxas21002c_core.c b/drivers/iio/gyro/fxas21002c_core.c index 0923fd793492..a36d71d9e3ea 100644 --- a/drivers/iio/gyro/fxas21002c_core.c +++ b/drivers/iio/gyro/fxas21002c_core.c @@ -150,10 +150,10 @@ struct fxas21002c_data { struct regulator *vddio; /* - * DMA (thus cache coherency maintenance) requires the - * transfer buffers to live in their own cache lines. + * DMA (thus cache coherency maintenance) may require the + * transfer buffers live in their own cache lines. */ - s16 buffer[8] ____cacheline_aligned; + s16 buffer[8] __aligned(IIO_DMA_MINALIGN); }; enum fxas21002c_channel_index {