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x86/tsc: Trust initial offset in architectural TSC-adjust MSRs

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commit 455f9075f14484f358b3c1d6845b4a438de198a7 upstream.

When the BIOS configures the architectural TSC-adjust MSRs on secondary
sockets to correct a constant inter-chassis offset, after Linux brings the
cores online, the TSC sync check later resets the core-local MSR to 0,
triggering HPET fallback and leading to performance loss.

Fix this by unconditionally using the initial adjust values read from the
MSRs. Trusting the initial offsets in this architectural mechanism is a
better approach than special-casing workarounds for specific platforms.

Signed-off-by: Daniel J Blueman <daniel@quora.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Steffen Persvold <sp@numascale.com>
Reviewed-by: James Cleverdon <james.cleverdon.external@eviden.com>
Reviewed-by: Dimitri Sivanich <sivanich@hpe.com>
Reviewed-by: Prarit Bhargava <prarit@redhat.com>
Link: https://lore.kernel.org/r/20240419085146.175665-1-daniel@quora.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Daniel J Blueman 2024-04-19 16:51:46 +08:00 committed by Greg Kroah-Hartman
parent 4a548b29cd
commit 491bd4d7aa
1 changed files with 2 additions and 4 deletions
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6
arch/x86/kernel/tsc_sync.c
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@ -192,11 +192,9 @@ bool tsc_store_and_check_tsc_adjust(bool bootcpu)
cur->warned = false;
/*
* If a non-zero TSC value for socket 0 may be valid then the default
* adjusted value cannot assumed to be zero either.
* The default adjust value cannot be assumed to be zero on any socket.
*/
if (tsc_async_resets)
cur->adjusted = bootval;
cur->adjusted = bootval;
/*
* Check whether this CPU is the first in a package to come up. In