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ARM: tegra: multi-platform conversion

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This branch converts Tegra to support multi-platform/single-zImage.
 
 One header is made accessible to drivers. The earlyprintk implementation
 is moved to the multi-platform location. Some Kconfig changes are made
 to enable multi-platform. Some dead files are deleted.
 
 The APIs exposed in the now-global tegra-powergate.h should be replaced
 with standard reset and power domain APIs in the future.
 
 This branch is based on (part of) the previous soc pull request.
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Merge tag 'tegra-for-3.10-multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/multiplatform

From Stephen Warren <swarren@wwwdotorg.org>:

ARM: tegra: multi-platform conversion

This branch converts Tegra to support multi-platform/single-zImage.

One header is made accessible to drivers. The earlyprintk implementation
is moved to the multi-platform location. Some Kconfig changes are made
to enable multi-platform. Some dead files are deleted.

The APIs exposed in the now-global tegra-powergate.h should be replaced
with standard reset and power domain APIs in the future.

This branch is based on (part of) the previous soc pull request.

* tag 'tegra-for-3.10-multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
  ARM: tegra: convert to multi-platform
  ARM: tegra: move <mach/powergate.h> to <linux/tegra-powergate.h>

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2013-04-09 16:55:15 +02:00
commit 494cc76061
11 changed files with 24 additions and 243 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
arch/arm/Kconfig
View File

@ -600,25 +600,6 @@ config ARCH_LPC32XX
help help
Support for the NXP LPC32XX family of processors Support for the NXP LPC32XX family of processors
config ARCH_TEGRA
bool "NVIDIA Tegra"
select ARCH_HAS_CPUFREQ
select ARCH_REQUIRE_GPIOLIB
select CLKDEV_LOOKUP
select CLKSRC_MMIO
select CLKSRC_OF
select COMMON_CLK
select GENERIC_CLOCKEVENTS
select HAVE_CLK
select HAVE_SMP
select MIGHT_HAVE_CACHE_L2X0
select SOC_BUS
select SPARSE_IRQ
select USE_OF
help
This enables support for NVIDIA Tegra based systems (Tegra APX,
Tegra 6xx and Tegra 2 series).
config ARCH_PXA config ARCH_PXA
bool "PXA2xx/PXA3xx-based" bool "PXA2xx/PXA3xx-based"
depends on MMU depends on MMU

27
arch/arm/mach-tegra/Kconfig
View File

@ -1,13 +1,28 @@
if ARCH_TEGRA config ARCH_TEGRA
bool "NVIDIA Tegra" if ARCH_MULTI_V7
select ARCH_HAS_CPUFREQ
select ARCH_REQUIRE_GPIOLIB
select CLKDEV_LOOKUP
select CLKSRC_MMIO
select CLKSRC_OF
select COMMON_CLK
select GENERIC_CLOCKEVENTS
select HAVE_CLK
select HAVE_SMP
select MIGHT_HAVE_CACHE_L2X0
select SOC_BUS
select SPARSE_IRQ
select USE_OF
help
This enables support for NVIDIA Tegra based systems.
comment "NVIDIA Tegra options" menu "NVIDIA Tegra options"
depends on ARCH_TEGRA
config ARCH_TEGRA_2x_SOC config ARCH_TEGRA_2x_SOC
bool "Enable support for Tegra20 family" bool "Enable support for Tegra20 family"
select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
select ARM_ERRATA_720789 select ARM_ERRATA_720789
select ARM_ERRATA_742230 if SMP
select ARM_ERRATA_751472
select ARM_ERRATA_754327 if SMP select ARM_ERRATA_754327 if SMP
select ARM_ERRATA_764369 if SMP select ARM_ERRATA_764369 if SMP
select ARM_GIC select ARM_GIC
@ -26,8 +41,6 @@ config ARCH_TEGRA_2x_SOC
config ARCH_TEGRA_3x_SOC config ARCH_TEGRA_3x_SOC
bool "Enable support for Tegra30 family" bool "Enable support for Tegra30 family"
select ARM_ERRATA_743622
select ARM_ERRATA_751472
select ARM_ERRATA_754322 select ARM_ERRATA_754322
select ARM_ERRATA_764369 if SMP select ARM_ERRATA_764369 if SMP
select ARM_GIC select ARM_GIC
@ -71,4 +84,4 @@ config TEGRA_AHB
config TEGRA_EMC_SCALING_ENABLE config TEGRA_EMC_SCALING_ENABLE
bool "Enable scaling the memory frequency" bool "Enable scaling the memory frequency"
endif endmenu

3
arch/arm/mach-tegra/Makefile.boot
View File

@ -1,3 +0,0 @@
zreladdr-$(CONFIG_ARCH_TEGRA_2x_SOC) += 0x00008000
params_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00000100
initrd_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00800000

1
arch/arm/mach-tegra/board.h
View File

@ -40,6 +40,7 @@ int tegra_clk_debugfs_init(void);
static inline int tegra_clk_debugfs_init(void) { return 0; } static inline int tegra_clk_debugfs_init(void) { return 0; }
#endif #endif
int __init tegra_powergate_init(void);
#if defined(CONFIG_ARCH_TEGRA_2x_SOC) && defined(CONFIG_DEBUG_FS) #if defined(CONFIG_ARCH_TEGRA_2x_SOC) && defined(CONFIG_DEBUG_FS)
int __init tegra_powergate_debugfs_init(void); int __init tegra_powergate_debugfs_init(void);
#else #else

2
arch/arm/mach-tegra/common.c
View File

@ -27,8 +27,6 @@
#include <asm/hardware/cache-l2x0.h> #include <asm/hardware/cache-l2x0.h>
#include <mach/powergate.h>
#include "board.h" #include "board.h"
#include "common.h" #include "common.h"
#include "fuse.h" #include "fuse.h"

26
arch/arm/mach-tegra/include/mach/timex.h
View File

@ -1,26 +0,0 @@
/*
* arch/arm/mach-tegra/include/mach/timex.h
*
* Copyright (C) 2010 Google, Inc.
*
* Author:
* Colin Cross <ccross@google.com>
* Erik Gilling <konkers@google.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __MACH_TEGRA_TIMEX_H
#define __MACH_TEGRA_TIMEX_H
#define CLOCK_TICK_RATE 1000000
#endif

175
arch/arm/mach-tegra/include/mach/uncompress.h
View File

@ -1,175 +0,0 @@
/*
* arch/arm/mach-tegra/include/mach/uncompress.h
*
* Copyright (C) 2010 Google, Inc.
* Copyright (C) 2011 Google, Inc.
* Copyright (C) 2011-2012 NVIDIA CORPORATION. All Rights Reserved.
*
* Author:
* Colin Cross <ccross@google.com>
* Erik Gilling <konkers@google.com>
* Doug Anderson <dianders@chromium.org>
* Stephen Warren <swarren@nvidia.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __MACH_TEGRA_UNCOMPRESS_H
#define __MACH_TEGRA_UNCOMPRESS_H
#include <linux/types.h>
#include <linux/serial_reg.h>
#include "../../iomap.h"
#define BIT(x) (1 << (x))
#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
#define DEBUG_UART_SHIFT 2
volatile u8 *uart;
static void putc(int c)
{
if (uart == NULL)
return;
while (!(uart[UART_LSR << DEBUG_UART_SHIFT] & UART_LSR_THRE))
barrier();
uart[UART_TX << DEBUG_UART_SHIFT] = c;
}
static inline void flush(void)
{
}
static const struct {
u32 base;
u32 reset_reg;
u32 clock_reg;
u32 bit;
} uarts[] = {
{
TEGRA_UARTA_BASE,
TEGRA_CLK_RESET_BASE + 0x04,
TEGRA_CLK_RESET_BASE + 0x10,
6,
},
{
TEGRA_UARTB_BASE,
TEGRA_CLK_RESET_BASE + 0x04,
TEGRA_CLK_RESET_BASE + 0x10,
7,
},
{
TEGRA_UARTC_BASE,
TEGRA_CLK_RESET_BASE + 0x08,
TEGRA_CLK_RESET_BASE + 0x14,
23,
},
{
TEGRA_UARTD_BASE,
TEGRA_CLK_RESET_BASE + 0x0c,
TEGRA_CLK_RESET_BASE + 0x18,
1,
},
{
TEGRA_UARTE_BASE,
TEGRA_CLK_RESET_BASE + 0x0c,
TEGRA_CLK_RESET_BASE + 0x18,
2,
},
};
static inline bool uart_clocked(int i)
{
if (*(u8 *)uarts[i].reset_reg & BIT(uarts[i].bit))
return false;
if (!(*(u8 *)uarts[i].clock_reg & BIT(uarts[i].bit)))
return false;
return true;
}
#ifdef CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA
int auto_odmdata(void)
{
volatile u32 *pmc = (volatile u32 *)TEGRA_PMC_BASE;
u32 odmdata = pmc[0xa0 / 4];
/*
* Bits 19:18 are the console type: 0=default, 1=none, 2==DCC, 3==UART
* Some boards apparently swap the last two values, but we don't have
* any way of catering for that here, so we just accept either. If this
* doesn't make sense for your board, just don't enable this feature.
*
* Bits 17:15 indicate the UART to use, 0/1/2/3/4 are UART A/B/C/D/E.
*/
switch ((odmdata >> 18) & 3) {
case 2:
case 3:
break;
default:
return -1;
}
return (odmdata >> 15) & 7;
}
#endif
/*
* Setup before decompression. This is where we do UART selection for
* earlyprintk and init the uart_base register.
*/
static inline void arch_decomp_setup(void)
{
int uart_id;
volatile u32 *apb_misc = (volatile u32 *)TEGRA_APB_MISC_BASE;
u32 chip, div;
#if defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
uart_id = auto_odmdata();
#elif defined(CONFIG_TEGRA_DEBUG_UARTA)
uart_id = 0;
#elif defined(CONFIG_TEGRA_DEBUG_UARTB)
uart_id = 1;
#elif defined(CONFIG_TEGRA_DEBUG_UARTC)
uart_id = 2;
#elif defined(CONFIG_TEGRA_DEBUG_UARTD)
uart_id = 3;
#elif defined(CONFIG_TEGRA_DEBUG_UARTE)
uart_id = 4;
#endif
if (uart_id < 0 || uart_id >= ARRAY_SIZE(uarts) ||
!uart_clocked(uart_id))
uart = NULL;
else
uart = (volatile u8 *)uarts[uart_id].base;
if (uart == NULL)
return;
chip = (apb_misc[0x804 / 4] >> 8) & 0xff;
if (chip == 0x20)
div = 0x0075;
else
div = 0x00dd;
uart[UART_LCR << DEBUG_UART_SHIFT] |= UART_LCR_DLAB;
uart[UART_DLL << DEBUG_UART_SHIFT] = div & 0xff;
uart[UART_DLM << DEBUG_UART_SHIFT] = div >> 8;
uart[UART_LCR << DEBUG_UART_SHIFT] = 3;
}
#endif

3
arch/arm/mach-tegra/pcie.c
View File

@ -34,12 +34,11 @@
#include <linux/delay.h> #include <linux/delay.h>
#include <linux/export.h> #include <linux/export.h>
#include <linux/clk/tegra.h> #include <linux/clk/tegra.h>
#include <linux/tegra-powergate.h>
#include <asm/sizes.h> #include <asm/sizes.h>
#include <asm/mach/pci.h> #include <asm/mach/pci.h>
#include <mach/powergate.h>
#include "board.h" #include "board.h"
#include "iomap.h" #include "iomap.h"

3
arch/arm/mach-tegra/powergate.c
View File

@ -27,8 +27,7 @@
#include <linux/seq_file.h> #include <linux/seq_file.h>
#include <linux/spinlock.h> #include <linux/spinlock.h>
#include <linux/clk/tegra.h> #include <linux/clk/tegra.h>
#include <linux/tegra-powergate.h>
#include <mach/powergate.h>
#include "fuse.h" #include "fuse.h"
#include "iomap.h" #include "iomap.h"

3
drivers/clk/tegra/clk-tegra30.c
View File

@ -22,8 +22,7 @@
#include <linux/of.h> #include <linux/of.h>
#include <linux/of_address.h> #include <linux/of_address.h>
#include <linux/clk/tegra.h> #include <linux/clk/tegra.h>
#include <linux/tegra-powergate.h>
#include <mach/powergate.h>
#include "clk.h" #include "clk.h"

5
arch/arm/mach-tegra/include/mach/powergate.h → include/linux/tegra-powergate.h
View File

@ -1,6 +1,4 @@
/* /*
* drivers/regulator/tegra-regulator.c
*
* Copyright (c) 2010 Google, Inc * Copyright (c) 2010 Google, Inc
* *
* Author: * Author:
@ -40,9 +38,6 @@ struct clk;
#define TEGRA_POWERGATE_CPU0 TEGRA_POWERGATE_CPU #define TEGRA_POWERGATE_CPU0 TEGRA_POWERGATE_CPU
#define TEGRA_POWERGATE_3D0 TEGRA_POWERGATE_3D #define TEGRA_POWERGATE_3D0 TEGRA_POWERGATE_3D
int __init tegra_powergate_init(void);
int tegra_cpu_powergate_id(int cpuid);
int tegra_powergate_is_powered(int id); int tegra_powergate_is_powered(int id);
int tegra_powergate_power_on(int id); int tegra_powergate_power_on(int id);
int tegra_powergate_power_off(int id); int tegra_powergate_power_off(int id);