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iio: dac: ad5764: Fix alignment for DMA safety

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[ Upstream commit b378722a3e9bb51318c0de7eeb4d71f2fcd6987f ]

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Update the comment to include 'may'.

Fixes: 68b14d7ea956 ("staging:iio:dac: Add AD5764 driver")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-53-jic23@kernel.org
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Jonathan Cameron 2022-05-08 18:56:32 +01:00 committed by Greg Kroah-Hartman
parent c0c4bb0311
commit 49713818d5
1 changed files with 2 additions and 2 deletions
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4
drivers/iio/dac/ad5764.c
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@ -56,13 +56,13 @@ struct ad5764_state {
struct mutex lock;
/*
* DMA (thus cache coherency maintenance) requires the
* DMA (thus cache coherency maintenance) may require the
* transfer buffers to live in their own cache lines.
*/
union {
__be32 d32;
u8 d8[4];
} data[2] ____cacheline_aligned;
} data[2] __aligned(IIO_DMA_MINALIGN);
};
enum ad5764_type {