ath11k: HAL changes to support WCN6750
Add HAL changes required to support WCN6750. Offsets of some registers for WCN6750 are different from other supported devices; move such register offsets to platform specific ath11k_hw_regs. Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00887-QCAMSLSWPLZ-1 Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1 Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1 Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1 Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com> Signed-off-by: Kalle Valo <quic_kvalo@quicinc.com> Link: https://lore.kernel.org/r/20220429170502.20080-8-quic_mpubbise@quicinc.com
This commit is contained in:
Manikanta Pubbisetty
Kalle Valo
parent
73d3e71306
commit
49890d9c93
@ -491,8 +491,10 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
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},
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.max_radios = 1,
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.bdf_addr = 0x4B0C0000,
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.hw_ops = &wcn6750_ops,
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.ring_mask = &ath11k_hw_ring_mask_qca6390,
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.internal_sleep_clock = false,
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.regs = &wcn6750_regs,
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.qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_WCN6750,
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.host_ce_config = ath11k_host_ce_config_qca6390,
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.ce_count = 9,
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@ -1,6 +1,7 @@
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// SPDX-License-Identifier: BSD-3-Clause-Clear
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/*
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* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
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* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <linux/dma-mapping.h>
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#include "hal_tx.h"
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@ -1082,10 +1083,10 @@ static void ath11k_hal_srng_update_hp_tp_addr(struct ath11k_base *ab,
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srng = &hal->srng_list[ring_id];
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if (srng_config->ring_dir == HAL_SRNG_DIR_DST)
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srng->u.dst_ring.tp_addr = (u32 *)(HAL_SHADOW_REG(shadow_cfg_idx) +
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srng->u.dst_ring.tp_addr = (u32 *)(HAL_SHADOW_REG(ab, shadow_cfg_idx) +
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(unsigned long)ab->mem);
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else
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srng->u.src_ring.hp_addr = (u32 *)(HAL_SHADOW_REG(shadow_cfg_idx) +
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srng->u.src_ring.hp_addr = (u32 *)(HAL_SHADOW_REG(ab, shadow_cfg_idx) +
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(unsigned long)ab->mem);
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}
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@ -1120,7 +1121,7 @@ int ath11k_hal_srng_update_shadow_config(struct ath11k_base *ab,
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ath11k_dbg(ab, ATH11k_DBG_HAL,
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"target_reg %x, shadow reg 0x%x shadow_idx 0x%x, ring_type %d, ring num %d",
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target_reg,
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HAL_SHADOW_REG(shadow_cfg_idx),
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HAL_SHADOW_REG(ab, shadow_cfg_idx),
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shadow_cfg_idx,
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ring_type, ring_num);
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@ -1193,12 +1194,12 @@ static int ath11k_hal_srng_create_config(struct ath11k_base *ab)
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s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_TCL_RING_HP(ab);
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s = &hal->srng_config[HAL_REO_REINJECT];
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s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_BASE_LSB;
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s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_HP;
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s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_BASE_LSB(ab);
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s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_HP(ab);
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s = &hal->srng_config[HAL_REO_CMD];
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s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_RING_BASE_LSB;
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s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_HP;
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s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_RING_BASE_LSB(ab);
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s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_HP(ab);
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s = &hal->srng_config[HAL_REO_STATUS];
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s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_STATUS_RING_BASE_LSB(ab);
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@ -1,6 +1,7 @@
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/* SPDX-License-Identifier: BSD-3-Clause-Clear */
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/*
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* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
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* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef ATH11K_HAL_H
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@ -31,12 +32,12 @@ struct ath11k_base;
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#define HAL_DSCP_TID_TBL_SIZE 24
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/* calculate the register address from bar0 of shadow register x */
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#define HAL_SHADOW_BASE_ADDR 0x000008fc
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#define HAL_SHADOW_BASE_ADDR(ab) ab->hw_params.regs->hal_shadow_base_addr
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#define HAL_SHADOW_NUM_REGS 36
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#define HAL_HP_OFFSET_IN_REG_START 1
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#define HAL_OFFSET_FROM_HP_TO_TP 4
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#define HAL_SHADOW_REG(x) (HAL_SHADOW_BASE_ADDR + (4 * (x)))
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#define HAL_SHADOW_REG(ab, x) (HAL_SHADOW_BASE_ADDR(ab) + (4 * (x)))
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/* WCSS Relative address */
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#define HAL_SEQ_WCSS_UMAC_OFFSET 0x00a00000
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@ -180,16 +181,18 @@ struct ath11k_base;
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#define HAL_REO_TCL_RING_HP(ab) ab->hw_params.regs->hal_reo_tcl_ring_hp
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/* REO CMD R0 address */
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#define HAL_REO_CMD_RING_BASE_LSB 0x00000194
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#define HAL_REO_CMD_RING_BASE_LSB(ab) \
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ab->hw_params.regs->hal_reo_cmd_ring_base_lsb
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/* REO CMD R2 address */
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#define HAL_REO_CMD_HP 0x00003020
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#define HAL_REO_CMD_HP(ab) ab->hw_params.regs->hal_reo_cmd_ring_hp
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/* SW2REO R0 address */
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#define HAL_SW2REO_RING_BASE_LSB 0x000001ec
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#define HAL_SW2REO_RING_BASE_LSB(ab) \
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ab->hw_params.regs->hal_sw2reo_ring_base_lsb
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/* SW2REO R2 address */
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#define HAL_SW2REO_RING_HP 0x00003028
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#define HAL_SW2REO_RING_HP(ab) ab->hw_params.regs->hal_sw2reo_ring_hp
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/* CE ring R0 address */
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#define HAL_CE_DST_RING_BASE_LSB 0x00000000
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@ -1,6 +1,7 @@
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// SPDX-License-Identifier: BSD-3-Clause-Clear
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/*
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* Copyright (c) 2018-2020 The Linux Foundation. All rights reserved.
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* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <linux/types.h>
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@ -1014,6 +1015,13 @@ const struct ath11k_hw_ops wcn6855_ops = {
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.rx_desc_mpdu_start_addr2 = ath11k_hw_wcn6855_rx_desc_mpdu_start_addr2,
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};
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const struct ath11k_hw_ops wcn6750_ops = {
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.get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id,
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.wmi_init_config = ath11k_init_wmi_config_qca6390,
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.mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390,
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.mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390,
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};
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#define ATH11K_TX_RING_MASK_0 0x1
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#define ATH11K_TX_RING_MASK_1 0x2
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#define ATH11K_TX_RING_MASK_2 0x4
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@ -1908,10 +1916,18 @@ const struct ath11k_hw_regs ipq8074_regs = {
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.hal_reo_tcl_ring_base_lsb = 0x000003fc,
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.hal_reo_tcl_ring_hp = 0x00003058,
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/* REO CMD ring address */
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.hal_reo_cmd_ring_base_lsb = 0x00000194,
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.hal_reo_cmd_ring_hp = 0x00003020,
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/* REO status address */
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.hal_reo_status_ring_base_lsb = 0x00000504,
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.hal_reo_status_hp = 0x00003070,
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/* SW2REO ring address */
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.hal_sw2reo_ring_base_lsb = 0x000001ec,
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.hal_sw2reo_ring_hp = 0x00003028,
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/* WCSS relative address */
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.hal_seq_wcss_umac_ce0_src_reg = 0x00a00000,
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.hal_seq_wcss_umac_ce0_dst_reg = 0x00a01000,
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@ -1932,6 +1948,9 @@ const struct ath11k_hw_regs ipq8074_regs = {
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/* PCIe base address */
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.pcie_qserdes_sysclk_en_sel = 0x0,
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.pcie_pcs_osc_dtct_config_base = 0x0,
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/* Shadow register area */
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.hal_shadow_base_addr = 0x0,
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};
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const struct ath11k_hw_regs qca6390_regs = {
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@ -1979,10 +1998,18 @@ const struct ath11k_hw_regs qca6390_regs = {
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.hal_reo_tcl_ring_base_lsb = 0x000003a4,
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.hal_reo_tcl_ring_hp = 0x00003050,
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/* REO CMD ring address */
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.hal_reo_cmd_ring_base_lsb = 0x00000194,
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.hal_reo_cmd_ring_hp = 0x00003020,
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/* REO status address */
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.hal_reo_status_ring_base_lsb = 0x000004ac,
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.hal_reo_status_hp = 0x00003068,
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/* SW2REO ring address */
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.hal_sw2reo_ring_base_lsb = 0x000001ec,
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.hal_sw2reo_ring_hp = 0x00003028,
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/* WCSS relative address */
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.hal_seq_wcss_umac_ce0_src_reg = 0x00a00000,
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.hal_seq_wcss_umac_ce0_dst_reg = 0x00a01000,
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@ -2003,6 +2030,9 @@ const struct ath11k_hw_regs qca6390_regs = {
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/* PCIe base address */
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.pcie_qserdes_sysclk_en_sel = 0x01e0c0ac,
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.pcie_pcs_osc_dtct_config_base = 0x01e0c628,
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/* Shadow register area */
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.hal_shadow_base_addr = 0x000008fc,
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};
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const struct ath11k_hw_regs qcn9074_regs = {
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@ -2050,10 +2080,18 @@ const struct ath11k_hw_regs qcn9074_regs = {
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.hal_reo_tcl_ring_base_lsb = 0x000003fc,
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.hal_reo_tcl_ring_hp = 0x00003058,
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/* REO CMD ring address */
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.hal_reo_cmd_ring_base_lsb = 0x00000194,
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.hal_reo_cmd_ring_hp = 0x00003020,
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/* REO status address */
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.hal_reo_status_ring_base_lsb = 0x00000504,
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.hal_reo_status_hp = 0x00003070,
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/* SW2REO ring address */
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.hal_sw2reo_ring_base_lsb = 0x000001ec,
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.hal_sw2reo_ring_hp = 0x00003028,
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/* WCSS relative address */
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.hal_seq_wcss_umac_ce0_src_reg = 0x01b80000,
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.hal_seq_wcss_umac_ce0_dst_reg = 0x01b81000,
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@ -2074,6 +2112,9 @@ const struct ath11k_hw_regs qcn9074_regs = {
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/* PCIe base address */
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.pcie_qserdes_sysclk_en_sel = 0x01e0e0a8,
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.pcie_pcs_osc_dtct_config_base = 0x01e0f45c,
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/* Shadow register area */
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.hal_shadow_base_addr = 0x0,
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};
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const struct ath11k_hw_regs wcn6855_regs = {
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@ -2121,10 +2162,18 @@ const struct ath11k_hw_regs wcn6855_regs = {
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.hal_reo_tcl_ring_base_lsb = 0x00000454,
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.hal_reo_tcl_ring_hp = 0x00003060,
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/* REO CMD ring address */
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.hal_reo_cmd_ring_base_lsb = 0x00000194,
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.hal_reo_cmd_ring_hp = 0x00003020,
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/* REO status address */
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.hal_reo_status_ring_base_lsb = 0x0000055c,
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.hal_reo_status_hp = 0x00003078,
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/* SW2REO ring address */
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.hal_sw2reo_ring_base_lsb = 0x000001ec,
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.hal_sw2reo_ring_hp = 0x00003028,
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/* WCSS relative address */
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.hal_seq_wcss_umac_ce0_src_reg = 0x1b80000,
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.hal_seq_wcss_umac_ce0_dst_reg = 0x1b81000,
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@ -2145,6 +2194,91 @@ const struct ath11k_hw_regs wcn6855_regs = {
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/* PCIe base address */
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.pcie_qserdes_sysclk_en_sel = 0x01e0c0ac,
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.pcie_pcs_osc_dtct_config_base = 0x01e0c628,
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/* Shadow register area */
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.hal_shadow_base_addr = 0x000008fc,
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};
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const struct ath11k_hw_regs wcn6750_regs = {
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/* SW2TCL(x) R0 ring configuration address */
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.hal_tcl1_ring_base_lsb = 0x00000694,
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.hal_tcl1_ring_base_msb = 0x00000698,
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.hal_tcl1_ring_id = 0x0000069c,
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.hal_tcl1_ring_misc = 0x000006a4,
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.hal_tcl1_ring_tp_addr_lsb = 0x000006b0,
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.hal_tcl1_ring_tp_addr_msb = 0x000006b4,
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.hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006c4,
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.hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006c8,
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.hal_tcl1_ring_msi1_base_lsb = 0x000006dc,
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.hal_tcl1_ring_msi1_base_msb = 0x000006e0,
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.hal_tcl1_ring_msi1_data = 0x000006e4,
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.hal_tcl2_ring_base_lsb = 0x000006ec,
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.hal_tcl_ring_base_lsb = 0x0000079c,
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/* TCL STATUS ring address */
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.hal_tcl_status_ring_base_lsb = 0x000008a4,
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/* REO2SW(x) R0 ring configuration address */
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.hal_reo1_ring_base_lsb = 0x000001ec,
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.hal_reo1_ring_base_msb = 0x000001f0,
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.hal_reo1_ring_id = 0x000001f4,
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.hal_reo1_ring_misc = 0x000001fc,
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.hal_reo1_ring_hp_addr_lsb = 0x00000200,
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.hal_reo1_ring_hp_addr_msb = 0x00000204,
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.hal_reo1_ring_producer_int_setup = 0x00000210,
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.hal_reo1_ring_msi1_base_lsb = 0x00000234,
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.hal_reo1_ring_msi1_base_msb = 0x00000238,
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.hal_reo1_ring_msi1_data = 0x0000023c,
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.hal_reo2_ring_base_lsb = 0x00000244,
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.hal_reo1_aging_thresh_ix_0 = 0x00000564,
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.hal_reo1_aging_thresh_ix_1 = 0x00000568,
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.hal_reo1_aging_thresh_ix_2 = 0x0000056c,
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.hal_reo1_aging_thresh_ix_3 = 0x00000570,
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/* REO2SW(x) R2 ring pointers (head/tail) address */
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.hal_reo1_ring_hp = 0x00003028,
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.hal_reo1_ring_tp = 0x0000302c,
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.hal_reo2_ring_hp = 0x00003030,
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/* REO2TCL R0 ring configuration address */
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.hal_reo_tcl_ring_base_lsb = 0x000003fc,
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.hal_reo_tcl_ring_hp = 0x00003058,
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/* REO CMD ring address */
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.hal_reo_cmd_ring_base_lsb = 0x000000e4,
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.hal_reo_cmd_ring_hp = 0x00003010,
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/* REO status address */
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.hal_reo_status_ring_base_lsb = 0x00000504,
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.hal_reo_status_hp = 0x00003070,
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/* SW2REO ring address */
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.hal_sw2reo_ring_base_lsb = 0x0000013c,
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.hal_sw2reo_ring_hp = 0x00003018,
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/* WCSS relative address */
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.hal_seq_wcss_umac_ce0_src_reg = 0x01b80000,
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.hal_seq_wcss_umac_ce0_dst_reg = 0x01b81000,
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.hal_seq_wcss_umac_ce1_src_reg = 0x01b82000,
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.hal_seq_wcss_umac_ce1_dst_reg = 0x01b83000,
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/* WBM Idle address */
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.hal_wbm_idle_link_ring_base_lsb = 0x00000874,
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.hal_wbm_idle_link_ring_misc = 0x00000884,
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/* SW2WBM release address */
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.hal_wbm_release_ring_base_lsb = 0x000001ec,
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/* WBM2SW release address */
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.hal_wbm0_release_ring_base_lsb = 0x00000924,
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.hal_wbm1_release_ring_base_lsb = 0x0000097c,
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/* PCIe base address */
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.pcie_qserdes_sysclk_en_sel = 0x0,
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.pcie_pcs_osc_dtct_config_base = 0x0,
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/* Shadow register area */
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.hal_shadow_base_addr = 0x00000504,
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};
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const struct ath11k_hw_hal_params ath11k_hw_hal_params_ipq8074 = {
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@ -253,6 +253,7 @@ extern const struct ath11k_hw_ops ipq6018_ops;
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extern const struct ath11k_hw_ops qca6390_ops;
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extern const struct ath11k_hw_ops qcn9074_ops;
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extern const struct ath11k_hw_ops wcn6855_ops;
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extern const struct ath11k_hw_ops wcn6750_ops;
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extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_ipq8074;
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extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qca6390;
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@ -355,6 +356,12 @@ struct ath11k_hw_regs {
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u32 hal_reo_status_ring_base_lsb;
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||||
u32 hal_reo_status_hp;
|
||||
|
||||
u32 hal_reo_cmd_ring_base_lsb;
|
||||
u32 hal_reo_cmd_ring_hp;
|
||||
|
||||
u32 hal_sw2reo_ring_base_lsb;
|
||||
u32 hal_sw2reo_ring_hp;
|
||||
|
||||
u32 hal_seq_wcss_umac_ce0_src_reg;
|
||||
u32 hal_seq_wcss_umac_ce0_dst_reg;
|
||||
u32 hal_seq_wcss_umac_ce1_src_reg;
|
||||
@ -370,12 +377,15 @@ struct ath11k_hw_regs {
|
||||
|
||||
u32 pcie_qserdes_sysclk_en_sel;
|
||||
u32 pcie_pcs_osc_dtct_config_base;
|
||||
|
||||
u32 hal_shadow_base_addr;
|
||||
};
|
||||
|
||||
extern const struct ath11k_hw_regs ipq8074_regs;
|
||||
extern const struct ath11k_hw_regs qca6390_regs;
|
||||
extern const struct ath11k_hw_regs qcn9074_regs;
|
||||
extern const struct ath11k_hw_regs wcn6855_regs;
|
||||
extern const struct ath11k_hw_regs wcn6750_regs;
|
||||
|
||||
static inline const char *ath11k_bd_ie_type_str(enum ath11k_bd_ie_type type)
|
||||
{
|
||||
|
||||
Loading…
Reference in New Issue
Block a user