net: ethernet: ti: am65-cpsw-qos: Add Frame Preemption MAC Merge support
Add driver support for viewing / changing the MAC Merge sublayer parameters and seeing the verification state machine's current state via ethtool. As hardware does not support interrupt notification for verification events we resort to polling on link up. On link up we try a couple of times for verification success and if unsuccessful then give up. The Frame Preemption feature is described in the Technical Reference Manual [1] in section: 12.3.1.4.6.7 Intersperced Express Traffic (IET – P802.3br/D2.0) Due to Silicon Errata i2208 [2] we set limit min IET fragment size to 124 (excluding 4 bytes mCRC). [1] AM62x TRM - https://www.ti.com/lit/ug/spruiv7a/spruiv7a.pdf [2] AM62x Silicon Errata - https://www.ti.com/lit/er/sprz487c/sprz487c.pdf Signed-off-by: Roger Quadros <rogerq@kernel.org> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Roger Quadros
David S. Miller
parent
bc8d62e16e
commit
49a2eb9068
@ -139,8 +139,9 @@ config TI_AM65_CPSW_QOS
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depends on TI_K3_AM65_CPSW_NUSS && NET_SCH_TAPRIO && TI_K3_AM65_CPTS
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help
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This option enables QoS offload features in AM65 CPSW like
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Time Aware Shaper (TAS) / Enhanced Scheduled Traffic (EST)
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and MQPRIO qdisc offload.
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Time Aware Shaper (TAS) / Enhanced Scheduled Traffic (EST),
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MQPRIO qdisc offload and Frame-Preemption MAC Merge / Interspersing
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Express Traffic (IET).
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The EST scheduler runs on CPTS and the TAS/EST schedule is
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updated in the Fetch RAM memory of the CPSW.
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@ -11,6 +11,7 @@
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#include <linux/pm_runtime.h>
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#include "am65-cpsw-nuss.h"
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#include "am65-cpsw-qos.h"
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#include "cpsw_ale.h"
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#include "am65-cpts.h"
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@ -670,6 +671,9 @@ static void am65_cpsw_get_eth_mac_stats(struct net_device *ndev,
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stats = port->stat_base;
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if (s->src != ETHTOOL_MAC_STATS_SRC_AGGREGATE)
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return;
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s->FramesTransmittedOK = readl_relaxed(&stats->tx_good_frames);
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s->SingleCollisionFrames = readl_relaxed(&stats->tx_single_coll_frames);
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s->MultipleCollisionFrames = readl_relaxed(&stats->tx_mult_coll_frames);
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@ -740,6 +744,166 @@ static int am65_cpsw_set_ethtool_priv_flags(struct net_device *ndev, u32 flags)
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return 0;
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}
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static void am65_cpsw_port_iet_rx_enable(struct am65_cpsw_port *port, bool enable)
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{
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u32 val;
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val = readl(port->port_base + AM65_CPSW_PN_REG_CTL);
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if (enable)
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val |= AM65_CPSW_PN_CTL_IET_PORT_EN;
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else
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val &= ~AM65_CPSW_PN_CTL_IET_PORT_EN;
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writel(val, port->port_base + AM65_CPSW_PN_REG_CTL);
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am65_cpsw_iet_common_enable(port->common);
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}
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static void am65_cpsw_port_iet_tx_enable(struct am65_cpsw_port *port, bool enable)
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{
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u32 val;
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val = readl(port->port_base + AM65_CPSW_PN_REG_IET_CTRL);
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if (enable)
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val |= AM65_CPSW_PN_IET_MAC_PENABLE;
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else
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val &= ~AM65_CPSW_PN_IET_MAC_PENABLE;
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writel(val, port->port_base + AM65_CPSW_PN_REG_IET_CTRL);
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}
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static int am65_cpsw_get_mm(struct net_device *ndev, struct ethtool_mm_state *state)
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{
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struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
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struct am65_cpsw_ndev_priv *priv = netdev_priv(ndev);
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u32 port_ctrl, iet_ctrl, iet_status;
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u32 add_frag_size;
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if (!IS_ENABLED(CONFIG_TI_AM65_CPSW_QOS))
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return -EOPNOTSUPP;
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mutex_lock(&priv->mm_lock);
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iet_ctrl = readl(port->port_base + AM65_CPSW_PN_REG_IET_CTRL);
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port_ctrl = readl(port->port_base + AM65_CPSW_PN_REG_CTL);
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state->tx_enabled = !!(iet_ctrl & AM65_CPSW_PN_IET_MAC_PENABLE);
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state->pmac_enabled = !!(port_ctrl & AM65_CPSW_PN_CTL_IET_PORT_EN);
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iet_status = readl(port->port_base + AM65_CPSW_PN_REG_IET_STATUS);
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if (iet_ctrl & AM65_CPSW_PN_IET_MAC_DISABLEVERIFY)
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state->verify_status = ETHTOOL_MM_VERIFY_STATUS_DISABLED;
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else if (iet_status & AM65_CPSW_PN_MAC_VERIFIED)
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state->verify_status = ETHTOOL_MM_VERIFY_STATUS_SUCCEEDED;
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else if (iet_status & AM65_CPSW_PN_MAC_VERIFY_FAIL)
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state->verify_status = ETHTOOL_MM_VERIFY_STATUS_FAILED;
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else
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state->verify_status = ETHTOOL_MM_VERIFY_STATUS_UNKNOWN;
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add_frag_size = AM65_CPSW_PN_IET_MAC_GET_ADDFRAGSIZE(iet_ctrl);
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state->tx_min_frag_size = ethtool_mm_frag_size_add_to_min(add_frag_size);
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/* Errata i2208: RX min fragment size cannot be less than 124 */
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state->rx_min_frag_size = 124;
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/* FPE active if common tx_enabled and verification success or disabled (forced) */
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state->tx_active = state->tx_enabled &&
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(state->verify_status == ETHTOOL_MM_VERIFY_STATUS_SUCCEEDED ||
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state->verify_status == ETHTOOL_MM_VERIFY_STATUS_DISABLED);
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state->verify_enabled = !(iet_ctrl & AM65_CPSW_PN_IET_MAC_DISABLEVERIFY);
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state->verify_time = port->qos.iet.verify_time_ms;
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/* 802.3-2018 clause 30.14.1.6, says that the aMACMergeVerifyTime
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* variable has a range between 1 and 128 ms inclusive. Limit to that.
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*/
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state->max_verify_time = 128;
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mutex_unlock(&priv->mm_lock);
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return 0;
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}
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static int am65_cpsw_set_mm(struct net_device *ndev, struct ethtool_mm_cfg *cfg,
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struct netlink_ext_ack *extack)
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{
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struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
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struct am65_cpsw_ndev_priv *priv = netdev_priv(ndev);
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struct am65_cpsw_iet *iet = &port->qos.iet;
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u32 val, add_frag_size;
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int err;
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if (!IS_ENABLED(CONFIG_TI_AM65_CPSW_QOS))
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return -EOPNOTSUPP;
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err = ethtool_mm_frag_size_min_to_add(cfg->tx_min_frag_size, &add_frag_size, extack);
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if (err)
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return err;
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mutex_lock(&priv->mm_lock);
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if (cfg->pmac_enabled) {
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/* change TX & RX FIFO MAX_BLKS as per TRM recommendation */
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if (!iet->original_max_blks)
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iet->original_max_blks = readl(port->port_base + AM65_CPSW_PN_REG_MAX_BLKS);
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writel(AM65_CPSW_PN_TX_RX_MAX_BLKS_IET,
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port->port_base + AM65_CPSW_PN_REG_MAX_BLKS);
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} else if (iet->original_max_blks) {
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/* restore RX & TX FIFO MAX_BLKS */
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writel(iet->original_max_blks,
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port->port_base + AM65_CPSW_PN_REG_MAX_BLKS);
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}
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am65_cpsw_port_iet_rx_enable(port, cfg->pmac_enabled);
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am65_cpsw_port_iet_tx_enable(port, cfg->tx_enabled);
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val = readl(port->port_base + AM65_CPSW_PN_REG_IET_CTRL);
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if (cfg->verify_enabled) {
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val &= ~AM65_CPSW_PN_IET_MAC_DISABLEVERIFY;
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/* Reset Verify state machine. Verification won't start here.
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* Verification will be done once link-up.
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*/
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val |= AM65_CPSW_PN_IET_MAC_LINKFAIL;
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} else {
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val |= AM65_CPSW_PN_IET_MAC_DISABLEVERIFY;
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/* Clear LINKFAIL to allow verify/response packets */
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val &= ~AM65_CPSW_PN_IET_MAC_LINKFAIL;
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}
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val &= ~AM65_CPSW_PN_IET_MAC_MAC_ADDFRAGSIZE_MASK;
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val |= AM65_CPSW_PN_IET_MAC_SET_ADDFRAGSIZE(add_frag_size);
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writel(val, port->port_base + AM65_CPSW_PN_REG_IET_CTRL);
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/* verify_timeout_count can only be set at valid link */
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port->qos.iet.verify_time_ms = cfg->verify_time;
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/* enable/disable preemption based on link status */
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am65_cpsw_iet_commit_preemptible_tcs(port);
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mutex_unlock(&priv->mm_lock);
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return 0;
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}
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static void am65_cpsw_get_mm_stats(struct net_device *ndev,
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struct ethtool_mm_stats *s)
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{
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struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
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void __iomem *base = port->stat_base;
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s->MACMergeFrameAssOkCount = readl(base + AM65_CPSW_STATN_IET_RX_ASSEMBLY_OK);
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s->MACMergeFrameAssErrorCount = readl(base + AM65_CPSW_STATN_IET_RX_ASSEMBLY_ERROR);
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s->MACMergeFrameSmdErrorCount = readl(base + AM65_CPSW_STATN_IET_RX_SMD_ERROR);
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/* CPSW Functional Spec states:
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* "The IET stat aMACMergeFragCountRx is derived by adding the
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* Receive Assembly Error count to this value. i.e. AM65_CPSW_STATN_IET_RX_FRAG"
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*/
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s->MACMergeFragCountRx = readl(base + AM65_CPSW_STATN_IET_RX_FRAG) + s->MACMergeFrameAssErrorCount;
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s->MACMergeFragCountTx = readl(base + AM65_CPSW_STATN_IET_TX_FRAG);
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s->MACMergeHoldCount = readl(base + AM65_CPSW_STATN_IET_TX_HOLD);
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}
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const struct ethtool_ops am65_cpsw_ethtool_ops_slave = {
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.begin = am65_cpsw_ethtool_op_begin,
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.complete = am65_cpsw_ethtool_op_complete,
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@ -769,4 +933,7 @@ const struct ethtool_ops am65_cpsw_ethtool_ops_slave = {
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.get_eee = am65_cpsw_get_eee,
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.set_eee = am65_cpsw_set_eee,
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.nway_reset = am65_cpsw_nway_reset,
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.get_mm = am65_cpsw_get_mm,
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.set_mm = am65_cpsw_set_mm,
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.get_mm_stats = am65_cpsw_get_mm_stats,
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};
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@ -2194,6 +2194,8 @@ am65_cpsw_nuss_init_port_ndev(struct am65_cpsw_common *common, u32 port_idx)
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ndev_priv = netdev_priv(port->ndev);
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ndev_priv->port = port;
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ndev_priv->msg_enable = AM65_CPSW_DEBUG;
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mutex_init(&ndev_priv->mm_lock);
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port->qos.link_speed = SPEED_UNKNOWN;
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SET_NETDEV_DEV(port->ndev, dev);
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eth_hw_addr_set(port->ndev, port->slave.mac_addr);
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@ -145,6 +145,7 @@ struct am65_cpsw_common {
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bool pf_p0_rx_ptype_rrobin;
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struct am65_cpts *cpts;
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int est_enabled;
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bool iet_enabled;
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bool is_emac_mode;
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u16 br_members;
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@ -170,6 +171,10 @@ struct am65_cpsw_ndev_priv {
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struct am65_cpsw_port *port;
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struct am65_cpsw_ndev_stats __percpu *stats;
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bool offload_fwd_mark;
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/* Serialize access to MAC Merge state between ethtool requests
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* and link state updates
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*/
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struct mutex mm_lock;
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};
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#define am65_ndev_to_priv(ndev) \
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@ -4,6 +4,7 @@
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*
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* quality of service module includes:
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* Enhanced Scheduler Traffic (EST - P802.1Qbv/D2.2)
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* Interspersed Express Traffic (IET - P802.3br/D2.0)
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*/
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#include <linux/pm_runtime.h>
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@ -25,6 +26,8 @@ enum timer_act {
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TACT_SKIP_PROG, /* just buffer can be updated */
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};
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static void am65_cpsw_iet_change_preemptible_tcs(struct am65_cpsw_port *port, u8 preemptible_tcs);
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static u32
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am65_cpsw_qos_tx_rate_calc(u32 rate_mbps, unsigned long bus_freq)
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{
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@ -192,6 +195,8 @@ static void am65_cpsw_reset_tc_mqprio(struct net_device *ndev)
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/* Reset all Queue priorities to 0 */
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writel(0, port->port_base + AM65_CPSW_PN_REG_TX_PRI_MAP);
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am65_cpsw_iet_change_preemptible_tcs(port, 0);
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}
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static int am65_cpsw_setup_mqprio(struct net_device *ndev, void *type_data)
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@ -254,6 +259,7 @@ static int am65_cpsw_setup_mqprio(struct net_device *ndev, void *type_data)
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writel(tx_prio_map, port->port_base + AM65_CPSW_PN_REG_TX_PRI_MAP);
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am65_cpsw_tx_pn_shaper_apply(port);
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am65_cpsw_iet_change_preemptible_tcs(port, mqprio->preemptible_tcs);
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exit_put:
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pm_runtime_put(common->dev);
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@ -261,6 +267,171 @@ exit_put:
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return ret;
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}
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static int am65_cpsw_iet_set_verify_timeout_count(struct am65_cpsw_port *port)
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{
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int verify_time_ms = port->qos.iet.verify_time_ms;
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u32 val;
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/* The number of wireside clocks contained in the verify
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* timeout counter. The default is 0x1312d0
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* (10ms at 125Mhz in 1G mode).
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*/
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val = 125 * HZ_PER_MHZ; /* assuming 125MHz wireside clock */
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val /= MILLIHZ_PER_HZ; /* count per ms timeout */
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val *= verify_time_ms; /* count for timeout ms */
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if (val > AM65_CPSW_PN_MAC_VERIFY_CNT_MASK)
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return -EINVAL;
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writel(val, port->port_base + AM65_CPSW_PN_REG_IET_VERIFY);
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return 0;
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}
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static int am65_cpsw_iet_verify_wait(struct am65_cpsw_port *port)
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{
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u32 ctrl, status;
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int try;
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try = 20;
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do {
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/* Reset the verify state machine by writing 1
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* to LINKFAIL
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*/
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ctrl = readl(port->port_base + AM65_CPSW_PN_REG_IET_CTRL);
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ctrl |= AM65_CPSW_PN_IET_MAC_LINKFAIL;
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writel(ctrl, port->port_base + AM65_CPSW_PN_REG_IET_CTRL);
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/* Clear MAC_LINKFAIL bit to start Verify. */
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ctrl = readl(port->port_base + AM65_CPSW_PN_REG_IET_CTRL);
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ctrl &= ~AM65_CPSW_PN_IET_MAC_LINKFAIL;
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writel(ctrl, port->port_base + AM65_CPSW_PN_REG_IET_CTRL);
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msleep(port->qos.iet.verify_time_ms);
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status = readl(port->port_base + AM65_CPSW_PN_REG_IET_STATUS);
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if (status & AM65_CPSW_PN_MAC_VERIFIED)
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return 0;
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if (status & AM65_CPSW_PN_MAC_VERIFY_FAIL) {
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netdev_dbg(port->ndev,
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"MAC Merge verify failed, trying again\n");
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continue;
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}
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if (status & AM65_CPSW_PN_MAC_RESPOND_ERR) {
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netdev_dbg(port->ndev, "MAC Merge respond error\n");
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return -ENODEV;
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}
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if (status & AM65_CPSW_PN_MAC_VERIFY_ERR) {
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netdev_dbg(port->ndev, "MAC Merge verify error\n");
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return -ENODEV;
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}
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} while (try-- > 0);
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netdev_dbg(port->ndev, "MAC Merge verify timeout\n");
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return -ETIMEDOUT;
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}
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static void am65_cpsw_iet_set_preempt_mask(struct am65_cpsw_port *port, u8 preemptible_tcs)
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{
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u32 val;
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val = readl(port->port_base + AM65_CPSW_PN_REG_IET_CTRL);
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val &= ~AM65_CPSW_PN_IET_MAC_PREMPT_MASK;
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val |= AM65_CPSW_PN_IET_MAC_SET_PREEMPT(preemptible_tcs);
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writel(val, port->port_base + AM65_CPSW_PN_REG_IET_CTRL);
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}
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/* enable common IET_ENABLE only if at least 1 port has rx IET enabled.
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* UAPI doesn't allow tx enable without rx enable.
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*/
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void am65_cpsw_iet_common_enable(struct am65_cpsw_common *common)
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{
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struct am65_cpsw_port *port;
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bool rx_enable = false;
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u32 val;
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int i;
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for (i = 0; i < common->port_num; i++) {
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port = &common->ports[i];
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val = readl(port->port_base + AM65_CPSW_PN_REG_CTL);
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rx_enable = !!(val & AM65_CPSW_PN_CTL_IET_PORT_EN);
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if (rx_enable)
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break;
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}
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val = readl(common->cpsw_base + AM65_CPSW_REG_CTL);
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if (rx_enable)
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val |= AM65_CPSW_CTL_IET_EN;
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else
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val &= ~AM65_CPSW_CTL_IET_EN;
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writel(val, common->cpsw_base + AM65_CPSW_REG_CTL);
|
||||
common->iet_enabled = rx_enable;
|
||||
}
|
||||
|
||||
/* CPSW does not have an IRQ to notify changes to the MAC Merge TX status
|
||||
* (active/inactive), but the preemptible traffic classes should only be
|
||||
* committed to hardware once TX is active. Resort to polling.
|
||||
*/
|
||||
void am65_cpsw_iet_commit_preemptible_tcs(struct am65_cpsw_port *port)
|
||||
{
|
||||
u8 preemptible_tcs;
|
||||
int err;
|
||||
u32 val;
|
||||
|
||||
if (port->qos.link_speed == SPEED_UNKNOWN)
|
||||
return;
|
||||
|
||||
val = readl(port->port_base + AM65_CPSW_PN_REG_CTL);
|
||||
if (!(val & AM65_CPSW_PN_CTL_IET_PORT_EN))
|
||||
return;
|
||||
|
||||
/* update common IET enable */
|
||||
am65_cpsw_iet_common_enable(port->common);
|
||||
|
||||
/* update verify count */
|
||||
err = am65_cpsw_iet_set_verify_timeout_count(port);
|
||||
if (err) {
|
||||
netdev_err(port->ndev, "couldn't set verify count: %d\n", err);
|
||||
return;
|
||||
}
|
||||
|
||||
val = readl(port->port_base + AM65_CPSW_PN_REG_IET_CTRL);
|
||||
if (!(val & AM65_CPSW_PN_IET_MAC_DISABLEVERIFY)) {
|
||||
err = am65_cpsw_iet_verify_wait(port);
|
||||
if (err)
|
||||
return;
|
||||
}
|
||||
|
||||
preemptible_tcs = port->qos.iet.preemptible_tcs;
|
||||
am65_cpsw_iet_set_preempt_mask(port, preemptible_tcs);
|
||||
}
|
||||
|
||||
static void am65_cpsw_iet_change_preemptible_tcs(struct am65_cpsw_port *port, u8 preemptible_tcs)
|
||||
{
|
||||
struct am65_cpsw_ndev_priv *priv = am65_ndev_to_priv(port->ndev);
|
||||
|
||||
port->qos.iet.preemptible_tcs = preemptible_tcs;
|
||||
mutex_lock(&priv->mm_lock);
|
||||
am65_cpsw_iet_commit_preemptible_tcs(port);
|
||||
mutex_unlock(&priv->mm_lock);
|
||||
}
|
||||
|
||||
static void am65_cpsw_iet_link_state_update(struct net_device *ndev)
|
||||
{
|
||||
struct am65_cpsw_ndev_priv *priv = am65_ndev_to_priv(ndev);
|
||||
struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
|
||||
|
||||
mutex_lock(&priv->mm_lock);
|
||||
am65_cpsw_iet_commit_preemptible_tcs(port);
|
||||
mutex_unlock(&priv->mm_lock);
|
||||
}
|
||||
|
||||
static int am65_cpsw_port_est_enabled(struct am65_cpsw_port *port)
|
||||
{
|
||||
return port->qos.est_oper || port->qos.est_admin;
|
||||
@ -737,6 +908,7 @@ static int am65_cpsw_taprio_replace(struct net_device *ndev,
|
||||
|
||||
devm_kfree(&ndev->dev, port->qos.est_admin);
|
||||
port->qos.est_admin = est_new;
|
||||
am65_cpsw_iet_change_preemptible_tcs(port, taprio->mqprio.preemptible_tcs);
|
||||
|
||||
return 0;
|
||||
|
||||
@ -1116,6 +1288,7 @@ void am65_cpsw_qos_link_up(struct net_device *ndev, int link_speed)
|
||||
|
||||
port->qos.link_speed = link_speed;
|
||||
am65_cpsw_tx_pn_shaper_apply(port);
|
||||
am65_cpsw_iet_link_state_update(ndev);
|
||||
|
||||
am65_cpsw_est_link_up(ndev, link_speed);
|
||||
port->qos.link_down_time = 0;
|
||||
@ -1127,6 +1300,7 @@ void am65_cpsw_qos_link_down(struct net_device *ndev)
|
||||
|
||||
port->qos.link_speed = SPEED_UNKNOWN;
|
||||
am65_cpsw_tx_pn_shaper_apply(port);
|
||||
am65_cpsw_iet_link_state_update(ndev);
|
||||
|
||||
if (!port->qos.link_down_time)
|
||||
port->qos.link_down_time = ktime_get();
|
||||
|
||||
@ -23,6 +23,12 @@ struct am65_cpsw_mqprio {
|
||||
bool shaper_en;
|
||||
};
|
||||
|
||||
struct am65_cpsw_iet {
|
||||
u8 preemptible_tcs;
|
||||
u32 original_max_blks;
|
||||
int verify_time_ms;
|
||||
};
|
||||
|
||||
struct am65_cpsw_ale_ratelimit {
|
||||
unsigned long cookie;
|
||||
u64 rate_packet_ps;
|
||||
@ -34,6 +40,7 @@ struct am65_cpsw_qos {
|
||||
ktime_t link_down_time;
|
||||
int link_speed;
|
||||
struct am65_cpsw_mqprio mqprio;
|
||||
struct am65_cpsw_iet iet;
|
||||
|
||||
struct am65_cpsw_ale_ratelimit ale_bc_ratelimit;
|
||||
struct am65_cpsw_ale_ratelimit ale_mc_ratelimit;
|
||||
@ -93,6 +100,8 @@ void am65_cpsw_qos_link_up(struct net_device *ndev, int link_speed);
|
||||
void am65_cpsw_qos_link_down(struct net_device *ndev);
|
||||
int am65_cpsw_qos_ndo_tx_p0_set_maxrate(struct net_device *ndev, int queue, u32 rate_mbps);
|
||||
void am65_cpsw_qos_tx_p0_rate_init(struct am65_cpsw_common *common);
|
||||
void am65_cpsw_iet_commit_preemptible_tcs(struct am65_cpsw_port *port);
|
||||
void am65_cpsw_iet_common_enable(struct am65_cpsw_common *common);
|
||||
#else
|
||||
static inline int am65_cpsw_qos_ndo_setup_tc(struct net_device *ndev,
|
||||
enum tc_setup_type type,
|
||||
@ -117,6 +126,102 @@ static inline int am65_cpsw_qos_ndo_tx_p0_set_maxrate(struct net_device *ndev,
|
||||
|
||||
static inline void am65_cpsw_qos_tx_p0_rate_init(struct am65_cpsw_common *common)
|
||||
{ }
|
||||
static inline void am65_cpsw_iet_commit_preemptible_tcs(struct am65_cpsw_port *port)
|
||||
{ }
|
||||
static inline void am65_cpsw_iet_common_enable(struct am65_cpsw_common *common)
|
||||
{ }
|
||||
#endif
|
||||
|
||||
#define AM65_CPSW_REG_CTL 0x004
|
||||
#define AM65_CPSW_PN_REG_CTL 0x004
|
||||
#define AM65_CPSW_PN_REG_MAX_BLKS 0x008
|
||||
#define AM65_CPSW_PN_REG_TX_PRI_MAP 0x018
|
||||
#define AM65_CPSW_PN_REG_RX_PRI_MAP 0x020
|
||||
#define AM65_CPSW_PN_REG_IET_CTRL 0x040
|
||||
#define AM65_CPSW_PN_REG_IET_STATUS 0x044
|
||||
#define AM65_CPSW_PN_REG_IET_VERIFY 0x048
|
||||
#define AM65_CPSW_PN_REG_FIFO_STATUS 0x050
|
||||
#define AM65_CPSW_PN_REG_EST_CTL 0x060
|
||||
#define AM65_CPSW_PN_REG_PRI_CIR(pri) (0x140 + 4 * (pri))
|
||||
#define AM65_CPSW_PN_REG_PRI_EIR(pri) (0x160 + 4 * (pri))
|
||||
|
||||
/* AM65_CPSW_REG_CTL register fields */
|
||||
#define AM65_CPSW_CTL_IET_EN BIT(17)
|
||||
#define AM65_CPSW_CTL_EST_EN BIT(18)
|
||||
|
||||
/* AM65_CPSW_PN_REG_CTL register fields */
|
||||
#define AM65_CPSW_PN_CTL_IET_PORT_EN BIT(16)
|
||||
#define AM65_CPSW_PN_CTL_EST_PORT_EN BIT(17)
|
||||
|
||||
/* AM65_CPSW_PN_REG_EST_CTL register fields */
|
||||
#define AM65_CPSW_PN_EST_ONEBUF BIT(0)
|
||||
#define AM65_CPSW_PN_EST_BUFSEL BIT(1)
|
||||
#define AM65_CPSW_PN_EST_TS_EN BIT(2)
|
||||
#define AM65_CPSW_PN_EST_TS_FIRST BIT(3)
|
||||
#define AM65_CPSW_PN_EST_ONEPRI BIT(4)
|
||||
#define AM65_CPSW_PN_EST_TS_PRI_MSK GENMASK(7, 5)
|
||||
|
||||
/* AM65_CPSW_PN_REG_IET_CTRL register fields */
|
||||
#define AM65_CPSW_PN_IET_MAC_PENABLE BIT(0)
|
||||
#define AM65_CPSW_PN_IET_MAC_DISABLEVERIFY BIT(2)
|
||||
#define AM65_CPSW_PN_IET_MAC_LINKFAIL BIT(3)
|
||||
#define AM65_CPSW_PN_IET_MAC_MAC_ADDFRAGSIZE_MASK GENMASK(10, 8)
|
||||
#define AM65_CPSW_PN_IET_MAC_MAC_ADDFRAGSIZE_OFFSET 8
|
||||
#define AM65_CPSW_PN_IET_MAC_PREMPT_MASK GENMASK(23, 16)
|
||||
#define AM65_CPSW_PN_IET_MAC_PREMPT_OFFSET 16
|
||||
|
||||
#define AM65_CPSW_PN_IET_MAC_SET_ADDFRAGSIZE(n) (((n) << AM65_CPSW_PN_IET_MAC_MAC_ADDFRAGSIZE_OFFSET) & \
|
||||
AM65_CPSW_PN_IET_MAC_MAC_ADDFRAGSIZE_MASK)
|
||||
#define AM65_CPSW_PN_IET_MAC_GET_ADDFRAGSIZE(n) (((n) & AM65_CPSW_PN_IET_MAC_MAC_ADDFRAGSIZE_MASK) >> \
|
||||
AM65_CPSW_PN_IET_MAC_MAC_ADDFRAGSIZE_OFFSET)
|
||||
#define AM65_CPSW_PN_IET_MAC_SET_PREEMPT(n) (((n) << AM65_CPSW_PN_IET_MAC_PREMPT_OFFSET) & \
|
||||
AM65_CPSW_PN_IET_MAC_PREMPT_MASK)
|
||||
#define AM65_CPSW_PN_IET_MAC_GET_PREEMPT(n) (((n) & AM65_CPSW_PN_IET_MAC_PREMPT_MASK) >> \
|
||||
AM65_CPSW_PN_IET_MAC_PREMPT_OFFSET)
|
||||
|
||||
/* AM65_CPSW_PN_REG_IET_STATUS register fields */
|
||||
#define AM65_CPSW_PN_MAC_STATUS GENMASK(3, 0)
|
||||
#define AM65_CPSW_PN_MAC_VERIFIED BIT(0)
|
||||
#define AM65_CPSW_PN_MAC_VERIFY_FAIL BIT(1)
|
||||
#define AM65_CPSW_PN_MAC_RESPOND_ERR BIT(2)
|
||||
#define AM65_CPSW_PN_MAC_VERIFY_ERR BIT(3)
|
||||
|
||||
/* AM65_CPSW_PN_REG_IET_VERIFY register fields */
|
||||
#define AM65_CPSW_PN_MAC_VERIFY_CNT_MASK GENMASK(23, 0)
|
||||
#define AM65_CPSW_PN_MAC_GET_VERIFY_CNT(n) ((n) & AM65_CPSW_PN_MAC_VERIFY_CNT_MASK)
|
||||
/* 10 msec converted to NSEC */
|
||||
#define AM65_CPSW_IET_VERIFY_CNT_MS (10)
|
||||
#define AM65_CPSW_IET_VERIFY_CNT_NS (AM65_CPSW_IET_VERIFY_CNT_MS * \
|
||||
NSEC_PER_MSEC)
|
||||
|
||||
/* AM65_CPSW_PN_REG_FIFO_STATUS register fields */
|
||||
#define AM65_CPSW_PN_FST_TX_PRI_ACTIVE_MSK GENMASK(7, 0)
|
||||
#define AM65_CPSW_PN_FST_TX_E_MAC_ALLOW_MSK GENMASK(15, 8)
|
||||
#define AM65_CPSW_PN_FST_EST_CNT_ERR BIT(16)
|
||||
#define AM65_CPSW_PN_FST_EST_ADD_ERR BIT(17)
|
||||
#define AM65_CPSW_PN_FST_EST_BUFACT BIT(18)
|
||||
|
||||
/* EST FETCH COMMAND RAM */
|
||||
#define AM65_CPSW_FETCH_RAM_CMD_NUM 0x80
|
||||
#define AM65_CPSW_FETCH_CNT_MSK GENMASK(21, 8)
|
||||
#define AM65_CPSW_FETCH_CNT_MAX (AM65_CPSW_FETCH_CNT_MSK >> 8)
|
||||
#define AM65_CPSW_FETCH_CNT_OFFSET 8
|
||||
#define AM65_CPSW_FETCH_ALLOW_MSK GENMASK(7, 0)
|
||||
#define AM65_CPSW_FETCH_ALLOW_MAX AM65_CPSW_FETCH_ALLOW_MSK
|
||||
|
||||
/* AM65_CPSW_PN_REG_MAX_BLKS fields for IET and No IET cases */
|
||||
/* 7 blocks for pn_rx_max_blks, 13 for pn_tx_max_blks*/
|
||||
#define AM65_CPSW_PN_TX_RX_MAX_BLKS_IET 0xD07
|
||||
|
||||
/* Slave IET Stats. register offsets */
|
||||
#define AM65_CPSW_STATN_IET_RX_ASSEMBLY_ERROR 0x140
|
||||
#define AM65_CPSW_STATN_IET_RX_ASSEMBLY_OK 0x144
|
||||
#define AM65_CPSW_STATN_IET_RX_SMD_ERROR 0x148
|
||||
#define AM65_CPSW_STATN_IET_RX_FRAG 0x14c
|
||||
#define AM65_CPSW_STATN_IET_TX_HOLD 0x150
|
||||
#define AM65_CPSW_STATN_IET_TX_FRAG 0x154
|
||||
|
||||
/* number of priority queues per port FIFO */
|
||||
#define AM65_CPSW_PN_FIFO_PRIO_NUM 8
|
||||
|
||||
#endif /* AM65_CPSW_QOS_H_ */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user