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Merge branch 'octeontx2-af-dynamically-allocate-BPIDs'

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Geetha sowjanya says:

====================
Dynamically allocate BPIDs for LBK

In current driver 64 BPIDs are reserved for LBK interfaces.
These bpids are 1-to-1 mapped to LBK interface channel numbers.
In some usecases one LBK interface required more than one bpids
and in some case they may not require at all. These usescas
can't be address with the current implementation as it always
reserves only one bpid per LBK channel.

This patch addresses this issue by creating free bpid pool from
these 64 bpids instead of 1-to-1 mapping to the lbk channel.
Now based on usecase LBK interface can request a bpid using (bp_enable()).

v1 -> v2:
   - Modified commit message.
   - Dropped patch2, as for now rvu netdev have no usecase. Will
     be upstream along with the CPT driver.
   - Addressed review comments by Simon Horman.
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller 2024-02-02 12:12:36 +00:00
commit 49d703c8f4
7 changed files with 182 additions and 53 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
View File

@ -837,6 +837,8 @@ enum nix_af_status {
NIX_AF_ERR_CQ_CTX_WRITE_ERR = -429,
NIX_AF_ERR_AQ_CTX_RETRY_WRITE = -430,
NIX_AF_ERR_LINK_CREDITS = -431,
NIX_AF_ERR_INVALID_BPID = -434,
NIX_AF_ERR_INVALID_BPID_REQ = -435,
NIX_AF_ERR_INVALID_MCAST_GRP = -436,
NIX_AF_ERR_INVALID_MCAST_DEL_REQ = -437,
NIX_AF_ERR_NON_CONTIG_MCE_LIST = -438,

14
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
View File

@ -1484,7 +1484,7 @@ int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc)
/* All CGX mapped PFs are set with assigned NIX block during init */
if (is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc))) {
blkaddr = pf->nix_blkaddr;
} else if (is_afvf(pcifunc)) {
} else if (is_lbk_vf(rvu, pcifunc)) {
vf = pcifunc - 1;
/* Assign NIX based on VF number. All even numbered VFs get
* NIX0 and odd numbered gets NIX1
@ -2034,7 +2034,7 @@ int rvu_mbox_handler_set_vf_perm(struct rvu *rvu, struct set_vf_perm *req,
u16 target;
/* Only PF can add VF permissions */
if ((pcifunc & RVU_PFVF_FUNC_MASK) || is_afvf(pcifunc))
if ((pcifunc & RVU_PFVF_FUNC_MASK) || is_lbk_vf(rvu, pcifunc))
return -EOPNOTSUPP;
target = (pcifunc & ~RVU_PFVF_FUNC_MASK) | (req->vf + 1);
@ -2618,6 +2618,9 @@ static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc)
* 3. Cleanup pools (NPA)
*/
/* Free allocated BPIDs */
rvu_nix_flr_free_bpids(rvu, pcifunc);
/* Free multicast/mirror node associated with the 'pcifunc' */
rvu_nix_mcast_flr_free_entries(rvu, pcifunc);
@ -3151,6 +3154,7 @@ static int rvu_enable_sriov(struct rvu *rvu)
{
struct pci_dev *pdev = rvu->pdev;
int err, chans, vfs;
int pos = 0;
if (!rvu_afvf_msix_vectors_num_ok(rvu)) {
dev_warn(&pdev->dev,
@ -3158,6 +3162,12 @@ static int rvu_enable_sriov(struct rvu *rvu)
return 0;
}
/* Get RVU VFs device id */
pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
if (!pos)
return 0;
pci_read_config_word(pdev, pos + PCI_SRIOV_VF_DID, &rvu->vf_devid);
chans = rvu_get_num_lbk_chans();
if (chans < 0)
return chans;

21
drivers/net/ethernet/marvell/octeontx2/af/rvu.h
View File

@ -288,6 +288,16 @@ enum rvu_pfvf_flags {
#define RVU_CLEAR_VF_PERM ~GENMASK(PF_SET_VF_TRUSTED, PF_SET_VF_MAC)
struct nix_bp {
struct rsrc_bmap bpids; /* free bpids bitmap */
u16 cgx_bpid_cnt;
u16 sdp_bpid_cnt;
u16 free_pool_base;
u16 *fn_map; /* pcifunc mapping */
u8 *intf_map; /* interface type map */
u8 *ref_cnt;
};
struct nix_txsch {
struct rsrc_bmap schq;
u8 lvl;
@ -363,6 +373,7 @@ struct nix_hw {
struct nix_lso lso;
struct nix_txvlan txvlan;
struct nix_ipolicer *ipolicer;
struct nix_bp bp;
u64 *tx_credits;
u8 cc_mcs_cnt;
};
@ -503,6 +514,7 @@ struct rvu {
struct mutex rsrc_lock; /* Serialize resource alloc/free */
struct mutex alias_lock; /* Serialize bar2 alias access */
int vfs; /* Number of VFs attached to RVU */
u16 vf_devid; /* VF devices id */
int nix_blkaddr[MAX_NIX_BLKS];
/* Mbox */
@ -732,9 +744,11 @@ static inline bool is_rvu_supports_nix1(struct rvu *rvu)
/* Function Prototypes
* RVU
*/
static inline bool is_afvf(u16 pcifunc)
#define RVU_LBK_VF_DEVID 0xA0F8
static inline bool is_lbk_vf(struct rvu *rvu, u16 pcifunc)
{
return !(pcifunc & ~RVU_PFVF_FUNC_MASK);
return (!(pcifunc & ~RVU_PFVF_FUNC_MASK) &&
(rvu->vf_devid == RVU_LBK_VF_DEVID));
}
static inline bool is_vf(u16 pcifunc)
@ -794,7 +808,7 @@ void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq);
int rvu_sdp_init(struct rvu *rvu);
bool is_sdp_pfvf(u16 pcifunc);
bool is_sdp_pf(u16 pcifunc);
bool is_sdp_vf(u16 pcifunc);
bool is_sdp_vf(struct rvu *rvu, u16 pcifunc);
/* CGX APIs */
static inline bool is_pf_cgxmapped(struct rvu *rvu, u8 pf)
@ -873,6 +887,7 @@ int rvu_nix_mcast_get_mce_index(struct rvu *rvu, u16 pcifunc,
u32 mcast_grp_idx);
int rvu_nix_mcast_update_mcam_entry(struct rvu *rvu, u16 pcifunc,
u32 mcast_grp_idx, u16 mcam_index);
void rvu_nix_flr_free_bpids(struct rvu *rvu, u16 pcifunc);
/* NPC APIs */
void rvu_npc_freemem(struct rvu *rvu);

181
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
View File

@ -499,29 +499,115 @@ static void nix_interface_deinit(struct rvu *rvu, u16 pcifunc, u8 nixlf)
rvu_cgx_disable_dmac_entries(rvu, pcifunc);
}
#define NIX_BPIDS_PER_LMAC 8
#define NIX_BPIDS_PER_CPT 1
static int nix_setup_bpids(struct rvu *rvu, struct nix_hw *hw, int blkaddr)
{
struct nix_bp *bp = &hw->bp;
int err, max_bpids;
u64 cfg;
cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST1);
max_bpids = FIELD_GET(NIX_CONST_MAX_BPIDS, cfg);
/* Reserve the BPIds for CGX and SDP */
bp->cgx_bpid_cnt = rvu->hw->cgx_links * NIX_BPIDS_PER_LMAC;
bp->sdp_bpid_cnt = rvu->hw->sdp_links * FIELD_GET(NIX_CONST_SDP_CHANS, cfg);
bp->free_pool_base = bp->cgx_bpid_cnt + bp->sdp_bpid_cnt +
NIX_BPIDS_PER_CPT;
bp->bpids.max = max_bpids - bp->free_pool_base;
err = rvu_alloc_bitmap(&bp->bpids);
if (err)
return err;
bp->fn_map = devm_kcalloc(rvu->dev, bp->bpids.max,
sizeof(u16), GFP_KERNEL);
if (!bp->fn_map)
return -ENOMEM;
bp->intf_map = devm_kcalloc(rvu->dev, bp->bpids.max,
sizeof(u8), GFP_KERNEL);
if (!bp->intf_map)
return -ENOMEM;
bp->ref_cnt = devm_kcalloc(rvu->dev, bp->bpids.max,
sizeof(u8), GFP_KERNEL);
if (!bp->ref_cnt)
return -ENOMEM;
return 0;
}
void rvu_nix_flr_free_bpids(struct rvu *rvu, u16 pcifunc)
{
int blkaddr, bpid, err;
struct nix_hw *nix_hw;
struct nix_bp *bp;
if (!is_lbk_vf(rvu, pcifunc))
return;
err = nix_get_struct_ptrs(rvu, pcifunc, &nix_hw, &blkaddr);
if (err)
return;
bp = &nix_hw->bp;
mutex_lock(&rvu->rsrc_lock);
for (bpid = 0; bpid < bp->bpids.max; bpid++) {
if (bp->fn_map[bpid] == pcifunc) {
bp->ref_cnt[bpid]--;
if (bp->ref_cnt[bpid])
continue;
rvu_free_rsrc(&bp->bpids, bpid);
bp->fn_map[bpid] = 0;
}
}
mutex_unlock(&rvu->rsrc_lock);
}
int rvu_mbox_handler_nix_bp_disable(struct rvu *rvu,
struct nix_bp_cfg_req *req,
struct msg_rsp *rsp)
{
u16 pcifunc = req->hdr.pcifunc;
int blkaddr, pf, type, err;
u16 chan_base, chan, bpid;
struct rvu_pfvf *pfvf;
int blkaddr, pf, type;
u16 chan_base, chan;
struct nix_hw *nix_hw;
struct nix_bp *bp;
u64 cfg;
pf = rvu_get_pf(pcifunc);
type = is_afvf(pcifunc) ? NIX_INTF_TYPE_LBK : NIX_INTF_TYPE_CGX;
type = is_lbk_vf(rvu, pcifunc) ? NIX_INTF_TYPE_LBK : NIX_INTF_TYPE_CGX;
if (!is_pf_cgxmapped(rvu, pf) && type != NIX_INTF_TYPE_LBK)
return 0;
pfvf = rvu_get_pfvf(rvu, pcifunc);
blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);
err = nix_get_struct_ptrs(rvu, pcifunc, &nix_hw, &blkaddr);
if (err)
return err;
bp = &nix_hw->bp;
chan_base = pfvf->rx_chan_base + req->chan_base;
for (chan = chan_base; chan < (chan_base + req->chan_cnt); chan++) {
cfg = rvu_read64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan));
rvu_write64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan),
cfg & ~BIT_ULL(16));
if (type == NIX_INTF_TYPE_LBK) {
bpid = cfg & GENMASK(8, 0);
mutex_lock(&rvu->rsrc_lock);
rvu_free_rsrc(&bp->bpids, bpid - bp->free_pool_base);
for (bpid = 0; bpid < bp->bpids.max; bpid++) {
if (bp->fn_map[bpid] == pcifunc) {
bp->fn_map[bpid] = 0;
bp->ref_cnt[bpid] = 0;
}
}
mutex_unlock(&rvu->rsrc_lock);
}
}
return 0;
}
@ -529,26 +615,21 @@ int rvu_mbox_handler_nix_bp_disable(struct rvu *rvu,
static int rvu_nix_get_bpid(struct rvu *rvu, struct nix_bp_cfg_req *req,
int type, int chan_id)
{
int bpid, blkaddr, lmac_chan_cnt, sdp_chan_cnt;
u16 cgx_bpid_cnt, lbk_bpid_cnt, sdp_bpid_cnt;
int bpid, blkaddr, sdp_chan_base, err;
struct rvu_hwinfo *hw = rvu->hw;
struct rvu_pfvf *pfvf;
struct nix_hw *nix_hw;
u8 cgx_id, lmac_id;
u64 cfg;
blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, req->hdr.pcifunc);
cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST);
lmac_chan_cnt = cfg & 0xFF;
cgx_bpid_cnt = hw->cgx_links * lmac_chan_cnt;
lbk_bpid_cnt = hw->lbk_links * ((cfg >> 16) & 0xFF);
cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST1);
sdp_chan_cnt = cfg & 0xFFF;
sdp_bpid_cnt = hw->sdp_links * sdp_chan_cnt;
struct nix_bp *bp;
pfvf = rvu_get_pfvf(rvu, req->hdr.pcifunc);
err = nix_get_struct_ptrs(rvu, req->hdr.pcifunc, &nix_hw, &blkaddr);
if (err)
return err;
bp = &nix_hw->bp;
/* Backpressure IDs range division
* CGX channles are mapped to (0 - 191) BPIDs
* LBK channles are mapped to (192 - 255) BPIDs
@ -561,38 +642,48 @@ static int rvu_nix_get_bpid(struct rvu *rvu, struct nix_bp_cfg_req *req,
*/
switch (type) {
case NIX_INTF_TYPE_CGX:
if ((req->chan_base + req->chan_cnt) > 16)
return -EINVAL;
if ((req->chan_base + req->chan_cnt) > NIX_BPIDS_PER_LMAC)
return NIX_AF_ERR_INVALID_BPID_REQ;
rvu_get_cgx_lmac_id(pfvf->cgx_lmac, &cgx_id, &lmac_id);
/* Assign bpid based on cgx, lmac and chan id */
bpid = (cgx_id * hw->lmac_per_cgx * lmac_chan_cnt) +
(lmac_id * lmac_chan_cnt) + req->chan_base;
bpid = (cgx_id * hw->lmac_per_cgx * NIX_BPIDS_PER_LMAC) +
(lmac_id * NIX_BPIDS_PER_LMAC) + req->chan_base;
if (req->bpid_per_chan)
bpid += chan_id;
if (bpid > cgx_bpid_cnt)
return -EINVAL;
if (bpid > bp->cgx_bpid_cnt)
return NIX_AF_ERR_INVALID_BPID;
break;
case NIX_INTF_TYPE_LBK:
if ((req->chan_base + req->chan_cnt) > 63)
return -EINVAL;
bpid = cgx_bpid_cnt + req->chan_base;
if (req->bpid_per_chan)
bpid += chan_id;
if (bpid > (cgx_bpid_cnt + lbk_bpid_cnt))
return -EINVAL;
/* Alloc bpid from the free pool */
mutex_lock(&rvu->rsrc_lock);
bpid = rvu_alloc_rsrc(&bp->bpids);
if (bpid < 0) {
mutex_unlock(&rvu->rsrc_lock);
return NIX_AF_ERR_INVALID_BPID;
}
bp->fn_map[bpid] = req->hdr.pcifunc;
bp->ref_cnt[bpid]++;
bpid += bp->free_pool_base;
mutex_unlock(&rvu->rsrc_lock);
break;
case NIX_INTF_TYPE_SDP:
if ((req->chan_base + req->chan_cnt) > 255)
return -EINVAL;
if ((req->chan_base + req->chan_cnt) > bp->sdp_bpid_cnt)
return NIX_AF_ERR_INVALID_BPID_REQ;
bpid = sdp_bpid_cnt + req->chan_base;
/* Handle usecase of 2 SDP blocks */
if (!hw->cap.programmable_chans)
sdp_chan_base = pfvf->rx_chan_base - NIX_CHAN_SDP_CH_START;
else
sdp_chan_base = pfvf->rx_chan_base - hw->sdp_chan_base;
bpid = bp->cgx_bpid_cnt + req->chan_base + sdp_chan_base;
if (req->bpid_per_chan)
bpid += chan_id;
if (bpid > (cgx_bpid_cnt + lbk_bpid_cnt + sdp_bpid_cnt))
return -EINVAL;
if (bpid > (bp->cgx_bpid_cnt + bp->sdp_bpid_cnt))
return NIX_AF_ERR_INVALID_BPID;
break;
default:
return -EINVAL;
@ -612,7 +703,7 @@ int rvu_mbox_handler_nix_bp_enable(struct rvu *rvu,
u64 cfg;
pf = rvu_get_pf(pcifunc);
type = is_afvf(pcifunc) ? NIX_INTF_TYPE_LBK : NIX_INTF_TYPE_CGX;
type = is_lbk_vf(rvu, pcifunc) ? NIX_INTF_TYPE_LBK : NIX_INTF_TYPE_CGX;
if (is_sdp_pfvf(pcifunc))
type = NIX_INTF_TYPE_SDP;
@ -1523,7 +1614,7 @@ int rvu_mbox_handler_nix_lf_alloc(struct rvu *rvu,
cfg = NPC_TX_DEF_PKIND;
rvu_write64(rvu, blkaddr, NIX_AF_LFX_TX_PARSE_CFG(nixlf), cfg);
intf = is_afvf(pcifunc) ? NIX_INTF_TYPE_LBK : NIX_INTF_TYPE_CGX;
intf = is_lbk_vf(rvu, pcifunc) ? NIX_INTF_TYPE_LBK : NIX_INTF_TYPE_CGX;
if (is_sdp_pfvf(pcifunc))
intf = NIX_INTF_TYPE_SDP;
@ -1899,7 +1990,7 @@ static int nix_get_tx_link(struct rvu *rvu, u16 pcifunc)
int pf = rvu_get_pf(pcifunc);
u8 cgx_id = 0, lmac_id = 0;
if (is_afvf(pcifunc)) {/* LBK links */
if (is_lbk_vf(rvu, pcifunc)) {/* LBK links */
return hw->cgx_links;
} else if (is_pf_cgxmapped(rvu, pf)) {
rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
@ -1916,7 +2007,7 @@ static void nix_get_txschq_range(struct rvu *rvu, u16 pcifunc,
struct rvu_hwinfo *hw = rvu->hw;
int pf = rvu_get_pf(pcifunc);
if (is_afvf(pcifunc)) { /* LBK links */
if (is_lbk_vf(rvu, pcifunc)) { /* LBK links */
*start = hw->cap.nix_txsch_per_cgx_lmac * link;
*end = *start + hw->cap.nix_txsch_per_lbk_lmac;
} else if (is_pf_cgxmapped(rvu, pf)) { /* CGX links */
@ -3356,7 +3447,7 @@ static int nix_update_mce_rule(struct rvu *rvu, u16 pcifunc,
int pf;
/* skip multicast pkt replication for AF's VFs & SDP links */
if (is_afvf(pcifunc) || is_sdp_pfvf(pcifunc))
if (is_lbk_vf(rvu, pcifunc) || is_sdp_pfvf(pcifunc))
return 0;
if (!hw->cap.nix_rx_multicast)
@ -3703,7 +3794,7 @@ int rvu_mbox_handler_nix_get_hw_info(struct rvu *rvu, struct msg_req *req,
if (blkaddr < 0)
return NIX_AF_ERR_AF_LF_INVALID;
if (is_afvf(pcifunc))
if (is_lbk_vf(rvu, pcifunc))
rvu_get_lbk_link_max_frs(rvu, &rsp->max_mtu);
else
rvu_get_lmac_link_max_frs(rvu, &rsp->max_mtu);
@ -4427,7 +4518,7 @@ int rvu_mbox_handler_nix_set_hw_frs(struct rvu *rvu, struct nix_frs_cfg *req,
if (!nix_hw)
return NIX_AF_ERR_INVALID_NIXBLK;
if (is_afvf(pcifunc))
if (is_lbk_vf(rvu, pcifunc))
rvu_get_lbk_link_max_frs(rvu, &max_mtu);
else
rvu_get_lmac_link_max_frs(rvu, &max_mtu);
@ -4791,6 +4882,10 @@ static int rvu_nix_block_init(struct rvu *rvu, struct nix_hw *nix_hw)
if (err)
return err;
err = nix_setup_bpids(rvu, nix_hw, blkaddr);
if (err)
return err;
/* Configure segmentation offload formats */
nix_setup_lso(rvu, nix_hw, blkaddr);

8
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c
View File

@ -417,7 +417,7 @@ static void npc_fixup_vf_rule(struct rvu *rvu, struct npc_mcam *mcam,
owner = mcam->entry2pfvf_map[index];
target_func = (entry->action >> 4) & 0xffff;
/* do nothing when target is LBK/PF or owner is not PF */
if (is_pffunc_af(owner) || is_afvf(target_func) ||
if (is_pffunc_af(owner) || is_lbk_vf(rvu, target_func) ||
(owner & RVU_PFVF_FUNC_MASK) ||
!(target_func & RVU_PFVF_FUNC_MASK))
return;
@ -626,7 +626,7 @@ void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc,
int blkaddr, index;
/* AF's and SDP VFs work in promiscuous mode */
if (is_afvf(pcifunc) || is_sdp_vf(pcifunc))
if (is_lbk_vf(rvu, pcifunc) || is_sdp_vf(rvu, pcifunc))
return;
blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
@ -791,7 +791,7 @@ void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc,
return;
/* Skip LBK VFs */
if (is_afvf(pcifunc))
if (is_lbk_vf(rvu, pcifunc))
return;
/* If pkt replication is not supported,
@ -871,7 +871,7 @@ void rvu_npc_install_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
u16 vf_func;
/* Only CGX PF/VF can add allmulticast entry */
if (is_afvf(pcifunc) && is_sdp_vf(pcifunc))
if (is_lbk_vf(rvu, pcifunc) && is_sdp_vf(rvu, pcifunc))
return;
blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);

3
drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h
View File

@ -439,6 +439,9 @@
#define NIX_AF_LINKX_RANGE_MASK GENMASK_ULL(19, 16)
#define NIX_AF_LINKX_MCS_CNT_MASK GENMASK_ULL(33, 32)
#define NIX_CONST_MAX_BPIDS GENMASK_ULL(23, 12)
#define NIX_CONST_SDP_CHANS GENMASK_ULL(11, 0)
/* SSO */
#define SSO_AF_CONST (0x1000)
#define SSO_AF_CONST1 (0x1008)

6
drivers/net/ethernet/marvell/octeontx2/af/rvu_sdp.c
View File

@ -40,8 +40,12 @@ bool is_sdp_pf(u16 pcifunc)
!(pcifunc & RVU_PFVF_FUNC_MASK));
}
bool is_sdp_vf(u16 pcifunc)
#define RVU_SDP_VF_DEVID 0xA0F7
bool is_sdp_vf(struct rvu *rvu, u16 pcifunc)
{
if (!(pcifunc & ~RVU_PFVF_FUNC_MASK))
return (rvu->vf_devid == RVU_SDP_VF_DEVID);
return (is_sdp_pfvf(pcifunc) &&
!!(pcifunc & RVU_PFVF_FUNC_MASK));
}