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ARC changes for 4.9-rc1

Browse Source 
- ARCv2 support for native 64-bit atomics using LLOCK/SCONDD instructions
  - Support for upcoming 3.0 release of HS38 cores
  - Dwarf unwindinder improvements
    - Ebaling unwinding out of hand written assembler code using CFI pseudo-ops
    - switching to .eh_frame (as opposed to historic .debug_frame)
    - getting rid of bunch of adhoc band-aids in the process
  - Miscll fixes
    - perf supporting generic cache-referecnes and cache-misses (Alexey)
    - default NODE_SHIFT (Noam Camus)
    - usage of KFLAG instruction to set IE (Yuriy)
  - Platforms
    - Adding "model" proprty across the DT (Alexey)
    - Enabling MODULE_* in defconfigs
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Merge tag 'arc-4.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc

Pull ARC updates from Vineet Gupta:

 - ARCv2 support for native 64-bit atomics using LLOCK/SCONDD
   instructions

 - Support for upcoming 3.0 release of HS38 cores

 - Dwarf unwindinder improvements:
   - enable unwinding of hand written assembler code using CFI
     pseudo-ops
   - switch to .eh_frame (as opposed to historic .debug_frame)
   - get rid of a bunch of adhoc band-aids in the process

 - Misc fixes:
   - perf supporting generic cache-references and cache-misses (Alexey)
   - default NODE_SHIFT (Noam Camus)
   - usage of KFLAG instruction to set IE (Yuriy)

 - Platforms:
   - Add "model" property across the DT (Alexey)
   - Enable MODULE_* in defconfigs

* tag 'arc-4.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc:
  ARC: [plat*] enables MODULE*
  ARCv2: fix local_save_flags
  ARC: CONFIG_NODES_SHIFT fix default values
  ARCv2: intc: Use kflag if STATUS32.IE must be reset
  ARC: .exit.* sections can be discarded in .eh_frame regime
  ARC: dw2 unwind: enable cfi pseudo ops in string lib
  ARC: dw2 unwind: add infrastructure for adding cfi pseudo ops to asm
  ARC: entry: make ret_from_system_call local label
  ARC: dw2 unwind: don't force dwarf 2
  ARC: dw2 unwind: switch to .eh_frame based unwinding
  ARC: dw2 unwind: factor CIE specifics for .eh_frame/.debug_frame
  ARC: module: support R_ARC_32_PCREL relocation
  arc: perf: Enable generic "cache-references" and "cache-misses" events
  ARC: [plat-eznps] add missing atomic_fetch_xxx operations
  ARCv2: Implement atomic64 based on LLOCKD/SCONDD instructions
  ARCv2: Support dynamic peripheral address space in HS38 rel 3.0 cores
  ARCv2: identify HS38 rel 3.0 cores
  ARCv2: Add support for ZeBu Emulation platform for HS cores
  arc: Add "model" properly in device tree description of all boards
This commit is contained in:
Linus Torvalds 2016-10-03 18:02:47 -07:00
commit 49deffe0b0
53 changed files with 769 additions and 114 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
arch/arc/Kconfig
View File

@ -13,7 +13,7 @@ config ARC
select CLKSRC_OF
select CLONE_BACKWARDS
select COMMON_CLK
select GENERIC_ATOMIC64
select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC)
select GENERIC_CLOCKEVENTS
select GENERIC_FIND_FIRST_BIT
# for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
@ -353,8 +353,8 @@ endchoice
config NODES_SHIFT
int "Maximum NUMA Nodes (as a power of 2)"
default "1" if !DISCONTIGMEM
default "2" if DISCONTIGMEM
default "0" if !DISCONTIGMEM
default "1" if DISCONTIGMEM
depends on NEED_MULTIPLE_NODES
---help---
Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory

7
arch/arc/Makefile
View File

@ -47,7 +47,6 @@ endif
upto_gcc44 := $(call cc-ifversion, -le, 0404, y)
atleast_gcc44 := $(call cc-ifversion, -ge, 0404, y)
atleast_gcc48 := $(call cc-ifversion, -ge, 0408, y)
cflags-$(atleast_gcc44) += -fsection-anchors
@ -66,10 +65,8 @@ endif
endif
# By default gcc 4.8 generates dwarf4 which kernel unwinder can't grok
ifeq ($(atleast_gcc48),y)
cflags-$(CONFIG_ARC_DW2_UNWIND) += -gdwarf-2
endif
cfi := $(call as-instr,.cfi_startproc\n.cfi_endproc,-DARC_DW2_UNWIND_AS_CFI)
cflags-$(CONFIG_ARC_DW2_UNWIND) += -fasynchronous-unwind-tables $(cfi)
ifndef CONFIG_CC_OPTIMIZE_FOR_SIZE
# Generic build system uses -O2, we want -O3

1
arch/arc/boot/dts/abilis_tb100_dvk.dts
View File

@ -24,6 +24,7 @@
/include/ "abilis_tb100.dtsi"
/ {
model = "abilis,tb100";
chosen {
bootargs = "earlycon=uart8250,mmio32,0xff100000,9600n8 console=ttyS0,9600n8";
};

1
arch/arc/boot/dts/abilis_tb101_dvk.dts
View File

@ -24,6 +24,7 @@
/include/ "abilis_tb101.dtsi"
/ {
model = "abilis,tb101";
chosen {
bootargs = "earlycon=uart8250,mmio32,0xff100000,9600n8 console=ttyS0,9600n8";
};

1
arch/arc/boot/dts/axs101.dts
View File

@ -13,6 +13,7 @@
/include/ "axs10x_mb.dtsi"
/ {
model = "snps,axs101";
compatible = "snps,axs101", "snps,arc-sdp";
chosen {

1
arch/arc/boot/dts/axs103.dts
View File

@ -16,6 +16,7 @@
/include/ "axs10x_mb.dtsi"
/ {
model = "snps,axs103";
compatible = "snps,axs103", "snps,arc-sdp";
chosen {

1
arch/arc/boot/dts/axs103_idu.dts
View File

@ -16,6 +16,7 @@
/include/ "axs10x_mb.dtsi"
/ {
model = "snps,axs103-smp";
compatible = "snps,axs103", "snps,arc-sdp";
chosen {

1
arch/arc/boot/dts/nsim_700.dts
View File

@ -10,6 +10,7 @@
/include/ "skeleton.dtsi"
/ {
model = "snps,nsim";
compatible = "snps,nsim";
#address-cells = <1>;
#size-cells = <1>;

1
arch/arc/boot/dts/nsim_hs.dts
View File

@ -10,6 +10,7 @@
/include/ "skeleton_hs.dtsi"
/ {
model = "snps,nsim_hs";
compatible = "snps,nsim_hs";
#address-cells = <2>;
#size-cells = <2>;

1
arch/arc/boot/dts/nsim_hs_idu.dts
View File

@ -10,6 +10,7 @@
/include/ "skeleton_hs_idu.dtsi"
/ {
model = "snps,nsim_hs-smp";
compatible = "snps,nsim_hs";
interrupt-parent = <&core_intc>;

1
arch/arc/boot/dts/nsimosci.dts
View File

@ -10,6 +10,7 @@
/include/ "skeleton.dtsi"
/ {
model = "snps,nsimosci";
compatible = "snps,nsimosci";
#address-cells = <1>;
#size-cells = <1>;

1
arch/arc/boot/dts/nsimosci_hs.dts
View File

@ -10,6 +10,7 @@
/include/ "skeleton_hs.dtsi"
/ {
model = "snps,nsimosci_hs";
compatible = "snps,nsimosci_hs";
#address-cells = <1>;
#size-cells = <1>;

1
arch/arc/boot/dts/nsimosci_hs_idu.dts
View File

@ -10,6 +10,7 @@
/include/ "skeleton_hs_idu.dtsi"
/ {
model = "snps,nsimosci_hs-smp";
compatible = "snps,nsimosci_hs";
#address-cells = <1>;
#size-cells = <1>;

1
arch/arc/boot/dts/vdk_hs38.dts
View File

@ -13,6 +13,7 @@
/include/ "vdk_axs10x_mb.dtsi"
/ {
model = "snps,vdk_archs";
compatible = "snps,axs103";
chosen {

1
arch/arc/boot/dts/vdk_hs38_smp.dts
View File

@ -13,6 +13,7 @@
/include/ "vdk_axs10x_mb.dtsi"
/ {
model = "snps,vdk_archs-smp";
compatible = "snps,axs103";
chosen {

69
arch/arc/boot/dts/zebu_hs.dts Normal file
View File

@ -0,0 +1,69 @@
/*
* Copyright (C) 2016-2014 Synopsys, Inc. (www.synopsys.com)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
/include/ "skeleton_hs.dtsi"
/ {
model = "snps,zebu_hs";
compatible = "snps,zebu_hs";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&core_intc>;
memory {
device_type = "memory";
reg = <0x80000000 0x20000000>; /* 512 */
};
chosen {
bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
};
aliases {
serial0 = &uart0;
};
fpga {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
/* child and parent address space 1:1 mapped */
ranges;
core_clk: core_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
core_intc: interrupt-controller {
compatible = "snps,archs-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
uart0: serial@f0000000 {
compatible = "ns8250";
reg = <0xf0000000 0x2000>;
interrupts = <24>;
clock-frequency = <50000000>;
baud = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
no-loopback-test = <1>;
};
arcpct0: pct {
compatible = "snps,archs-pct";
#interrupt-cells = <1>;
interrupts = <20>;
};
};
};

85
arch/arc/boot/dts/zebu_hs_idu.dts Normal file
View File

@ -0,0 +1,85 @@
/*
* Copyright (C) 2016-2014 Synopsys, Inc. (www.synopsys.com)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
/include/ "skeleton_hs_idu.dtsi"
/ {
model = "snps,zebu_hs-smp";
compatible = "snps,zebu_hs";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&core_intc>;
memory {
device_type = "memory";
reg = <0x80000000 0x20000000>; /* 512 */
};
chosen {
bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug";
};
aliases {
serial0 = &uart0;
};
fpga {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
/* child and parent address space 1:1 mapped */
ranges;
core_clk: core_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>; /* 50 MHZ */
};
core_intc: interrupt-controller {
compatible = "snps,archs-intc";
interrupt-controller;
#interrupt-cells = <1>;
/* interrupts = <16 17 18 19 20 21 22 23 24 25>; */
};
idu_intc: idu-interrupt-controller {
compatible = "snps,archs-idu-intc";
interrupt-controller;
interrupt-parent = <&core_intc>;
/* <hwirq distribution>
distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3 */
#interrupt-cells = <2>;
interrupts = <24 25 26 27 28 29 30 31>;
};
uart0: serial@f0000000 {
/* compatible = "ns8250"; Doesn't use FIFOs */
compatible = "ns16550a";
reg = <0xf0000000 0x2000>;
interrupt-parent = <&idu_intc>;
/* interrupts = <0 1>; DEST=1*/
/* interrupts = <0 2>; DEST=2*/
interrupts = <0 0>; /* RR*/
clock-frequency = <50000000>;
baud = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
no-loopback-test = <1>;
};
arcpct0: pct {
compatible = "snps,archs-pct";
#interrupt-cells = <1>;
interrupts = <20>;
};
};
};

3
arch/arc/configs/axs101_defconfig
View File

@ -18,6 +18,9 @@ CONFIG_PERF_EVENTS=y
# CONFIG_SLUB_DEBUG is not set
# CONFIG_COMPAT_BRK is not set
CONFIG_MODULES=y
CONFIG_MODULE_FORCE_LOAD=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_ARC_PLAT_AXS10X=y
CONFIG_AXS101=y

3
arch/arc/configs/axs103_defconfig
View File

@ -18,6 +18,9 @@ CONFIG_PERF_EVENTS=y
# CONFIG_SLUB_DEBUG is not set
# CONFIG_COMPAT_BRK is not set
CONFIG_MODULES=y
CONFIG_MODULE_FORCE_LOAD=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_ARC_PLAT_AXS10X=y
CONFIG_AXS103=y

3
arch/arc/configs/axs103_smp_defconfig
View File

@ -18,6 +18,9 @@ CONFIG_PERF_EVENTS=y
# CONFIG_COMPAT_BRK is not set
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_FORCE_LOAD=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_ARC_PLAT_AXS10X=y
CONFIG_AXS103=y

5
arch/arc/configs/nsim_hs_defconfig
View File

@ -11,13 +11,16 @@ CONFIG_NAMESPACES=y
# CONFIG_UTS_NS is not set
# CONFIG_PID_NS is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE="../arc_initramfs_hs/"
CONFIG_INITRAMFS_SOURCE="../../arc_initramfs_hs/"
CONFIG_KALLSYMS_ALL=y
CONFIG_EMBEDDED=y
# CONFIG_SLUB_DEBUG is not set
# CONFIG_COMPAT_BRK is not set
CONFIG_KPROBES=y
CONFIG_MODULES=y
CONFIG_MODULE_FORCE_LOAD=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
# CONFIG_LBDAF is not set
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set

3
arch/arc/configs/nsim_hs_smp_defconfig
View File

@ -16,6 +16,9 @@ CONFIG_EMBEDDED=y
# CONFIG_COMPAT_BRK is not set
CONFIG_KPROBES=y
CONFIG_MODULES=y
CONFIG_MODULE_FORCE_LOAD=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
# CONFIG_LBDAF is not set
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set

86
arch/arc/configs/zebu_hs_defconfig Normal file
View File

@ -0,0 +1,86 @@
CONFIG_DEFAULT_HOSTNAME="ARCLinux"
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
# CONFIG_CROSS_MEMORY_ATTACH is not set
CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_NAMESPACES=y
# CONFIG_UTS_NS is not set
# CONFIG_PID_NS is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE="../../arc_initramfs_hs/"
CONFIG_EXPERT=y
CONFIG_PERF_EVENTS=y
# CONFIG_COMPAT_BRK is not set
CONFIG_SLAB=y
CONFIG_MODULES=y
# CONFIG_LBDAF is not set
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARC_PLAT_SIM=y
CONFIG_ISA_ARCV2=y
CONFIG_ARC_BUILTIN_DTB_NAME="zebu_hs"
CONFIG_PREEMPT=y
# CONFIG_COMPACTION is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_PACKET_DIAG=y
CONFIG_UNIX=y
CONFIG_UNIX_DIAG=y
CONFIG_NET_KEY=y
CONFIG_INET=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_IPV6 is not set
# CONFIG_WIRELESS is not set
CONFIG_DEVTMPFS=y
# CONFIG_STANDALONE is not set
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
# CONFIG_FIRMWARE_IN_KERNEL is not set
# CONFIG_BLK_DEV is not set
CONFIG_NETDEVICES=y
# CONFIG_NET_VENDOR_ARC is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_INTEL is not set
# CONFIG_NET_VENDOR_MARVELL is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_STMICRO is not set
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
# CONFIG_WLAN is not set
CONFIG_INPUT_EVDEV=y
CONFIG_MOUSE_PS2_TOUCHKIT=y
# CONFIG_SERIO_SERPORT is not set
CONFIG_SERIO_ARC_PS2=y
# CONFIG_LEGACY_PTYS is not set
# CONFIG_DEVKMEM is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=1
CONFIG_SERIAL_8250_RUNTIME_UARTS=1
CONFIG_SERIAL_8250_DW=y
CONFIG_SERIAL_OF_PLATFORM=y
# CONFIG_HW_RANDOM is not set
# CONFIG_HWMON is not set
CONFIG_FB=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_LOGO=y
# CONFIG_HID is not set
# CONFIG_USB_SUPPORT is not set
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_TMPFS=y
# CONFIG_MISC_FILESYSTEMS is not set
CONFIG_NFS_FS=y
# CONFIG_ENABLE_WARN_DEPRECATED is not set
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_DEBUG_MEMORY_INIT=y
# CONFIG_DEBUG_PREEMPT is not set

89
arch/arc/configs/zebu_hs_smp_defconfig Normal file
View File

@ -0,0 +1,89 @@
CONFIG_DEFAULT_HOSTNAME="ARCLinux"
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
# CONFIG_CROSS_MEMORY_ATTACH is not set
CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_NAMESPACES=y
# CONFIG_UTS_NS is not set
# CONFIG_PID_NS is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE="../../arc_initramfs_hs/"
CONFIG_EMBEDDED=y
CONFIG_PERF_EVENTS=y
# CONFIG_VM_EVENT_COUNTERS is not set
# CONFIG_COMPAT_BRK is not set
CONFIG_SLAB=y
CONFIG_KPROBES=y
CONFIG_MODULES=y
# CONFIG_LBDAF is not set
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARC_PLAT_SIM=y
CONFIG_ISA_ARCV2=y
CONFIG_SMP=y
CONFIG_ARC_BUILTIN_DTB_NAME="zebu_hs_idu"
CONFIG_PREEMPT=y
# CONFIG_COMPACTION is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_PACKET_DIAG=y
CONFIG_UNIX=y
CONFIG_UNIX_DIAG=y
CONFIG_NET_KEY=y
CONFIG_INET=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_IPV6 is not set
# CONFIG_WIRELESS is not set
CONFIG_DEVTMPFS=y
# CONFIG_STANDALONE is not set
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
# CONFIG_FIRMWARE_IN_KERNEL is not set
# CONFIG_BLK_DEV is not set
CONFIG_NETDEVICES=y
# CONFIG_NET_VENDOR_ARC is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_INTEL is not set
# CONFIG_NET_VENDOR_MARVELL is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_STMICRO is not set
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
# CONFIG_WLAN is not set
CONFIG_INPUT_EVDEV=y
CONFIG_MOUSE_PS2_TOUCHKIT=y
# CONFIG_SERIO_SERPORT is not set
CONFIG_SERIO_ARC_PS2=y
# CONFIG_LEGACY_PTYS is not set
# CONFIG_DEVKMEM is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=1
CONFIG_SERIAL_8250_RUNTIME_UARTS=1
CONFIG_SERIAL_8250_DW=y
CONFIG_SERIAL_OF_PLATFORM=y
# CONFIG_HW_RANDOM is not set
# CONFIG_HWMON is not set
CONFIG_FB=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_LOGO=y
# CONFIG_HID is not set
# CONFIG_USB_SUPPORT is not set
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_TMPFS=y
# CONFIG_MISC_FILESYSTEMS is not set
CONFIG_NFS_FS=y
# CONFIG_ENABLE_WARN_DEPRECATED is not set
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_LOCKUP_DETECTOR=y
# CONFIG_DEBUG_PREEMPT is not set

10
arch/arc/include/asm/arcregs.h
View File

@ -95,7 +95,7 @@
/* Auxiliary registers */
#define AUX_IDENTITY 4
#define AUX_INTR_VEC_BASE 0x25
#define AUX_NON_VOL 0x5e
#define AUX_VOL 0x5e
/*
* Floating Pt Registers
@ -240,14 +240,6 @@ struct bcr_extn_xymem {
#endif
};
struct bcr_perip {
#ifdef CONFIG_CPU_BIG_ENDIAN
unsigned int start:8, pad2:8, sz:8, ver:8;
#else
unsigned int ver:8, sz:8, pad2:8, start:8;
#endif
};
struct bcr_iccm_arcompact {
#ifdef CONFIG_CPU_BIG_ENDIAN
unsigned int base:16, pad:5, sz:3, ver:8;

263
arch/arc/include/asm/atomic.h
View File

@ -20,6 +20,7 @@
#ifndef CONFIG_ARC_PLAT_EZNPS
#define atomic_read(v) READ_ONCE((v)->counter)
#define ATOMIC_INIT(i) { (i) }
#ifdef CONFIG_ARC_HAS_LLSC
@ -284,6 +285,7 @@ static inline int atomic_fetch_##op(int i, atomic_t *v) \
ATOMIC_OPS(add, +=, CTOP_INST_AADD_DI_R2_R2_R3)
#define atomic_sub(i, v) atomic_add(-(i), (v))
#define atomic_sub_return(i, v) atomic_add_return(-(i), (v))
#define atomic_fetch_sub(i, v) atomic_fetch_add(-(i), (v))
#undef ATOMIC_OPS
#define ATOMIC_OPS(op, c_op, asm_op) \
@ -292,6 +294,7 @@ ATOMIC_OPS(add, +=, CTOP_INST_AADD_DI_R2_R2_R3)
ATOMIC_OPS(and, &=, CTOP_INST_AAND_DI_R2_R2_R3)
#define atomic_andnot(mask, v) atomic_and(~(mask), (v))
#define atomic_fetch_andnot(mask, v) atomic_fetch_and(~(mask), (v))
ATOMIC_OPS(or, |=, CTOP_INST_AOR_DI_R2_R2_R3)
ATOMIC_OPS(xor, ^=, CTOP_INST_AXOR_DI_R2_R2_R3)
@ -343,10 +346,266 @@ ATOMIC_OPS(xor, ^=, CTOP_INST_AXOR_DI_R2_R2_R3)
#define atomic_add_negative(i, v) (atomic_add_return(i, v) < 0)
#define ATOMIC_INIT(i) { (i) }
#ifdef CONFIG_GENERIC_ATOMIC64
#include <asm-generic/atomic64.h>
#endif
#else /* Kconfig ensures this is only enabled with needed h/w assist */
/*
* ARCv2 supports 64-bit exclusive load (LLOCKD) / store (SCONDD)
* - The address HAS to be 64-bit aligned
* - There are 2 semantics involved here:
* = exclusive implies no interim update between load/store to same addr
* = both words are observed/updated together: this is guaranteed even
* for regular 64-bit load (LDD) / store (STD). Thus atomic64_set()
* is NOT required to use LLOCKD+SCONDD, STD suffices
*/
typedef struct {
aligned_u64 counter;
} atomic64_t;
#define ATOMIC64_INIT(a) { (a) }
static inline long long atomic64_read(const atomic64_t *v)
{
unsigned long long val;
__asm__ __volatile__(
" ldd %0, [%1] \n"
: "=r"(val)
: "r"(&v->counter));
return val;
}
static inline void atomic64_set(atomic64_t *v, long long a)
{
/*
* This could have been a simple assignment in "C" but would need
* explicit volatile. Otherwise gcc optimizers could elide the store
* which borked atomic64 self-test
* In the inline asm version, memory clobber needed for exact same
* reason, to tell gcc about the store.
*
* This however is not needed for sibling atomic64_add() etc since both
* load/store are explicitly done in inline asm. As long as API is used
* for each access, gcc has no way to optimize away any load/store
*/
__asm__ __volatile__(
" std %0, [%1] \n"
:
: "r"(a), "r"(&v->counter)
: "memory");
}
#define ATOMIC64_OP(op, op1, op2) \
static inline void atomic64_##op(long long a, atomic64_t *v) \
{ \
unsigned long long val; \
\
__asm__ __volatile__( \
"1: \n" \
" llockd %0, [%1] \n" \
" " #op1 " %L0, %L0, %L2 \n" \
" " #op2 " %H0, %H0, %H2 \n" \
" scondd %0, [%1] \n" \
" bnz 1b \n" \
: "=&r"(val) \
: "r"(&v->counter), "ir"(a) \
: "cc"); \
} \
#define ATOMIC64_OP_RETURN(op, op1, op2) \
static inline long long atomic64_##op##_return(long long a, atomic64_t *v) \
{ \
unsigned long long val; \
\
smp_mb(); \
\
__asm__ __volatile__( \
"1: \n" \
" llockd %0, [%1] \n" \
" " #op1 " %L0, %L0, %L2 \n" \
" " #op2 " %H0, %H0, %H2 \n" \
" scondd %0, [%1] \n" \
" bnz 1b \n" \
: [val] "=&r"(val) \
: "r"(&v->counter), "ir"(a) \
: "cc"); /* memory clobber comes from smp_mb() */ \
\
smp_mb(); \
\
return val; \
}
#define ATOMIC64_FETCH_OP(op, op1, op2) \
static inline long long atomic64_fetch_##op(long long a, atomic64_t *v) \
{ \
unsigned long long val, orig; \
\
smp_mb(); \
\
__asm__ __volatile__( \
"1: \n" \
" llockd %0, [%2] \n" \
" " #op1 " %L1, %L0, %L3 \n" \
" " #op2 " %H1, %H0, %H3 \n" \
" scondd %1, [%2] \n" \
" bnz 1b \n" \
: "=&r"(orig), "=&r"(val) \
: "r"(&v->counter), "ir"(a) \
: "cc"); /* memory clobber comes from smp_mb() */ \
\
smp_mb(); \
\
return orig; \
}
#define ATOMIC64_OPS(op, op1, op2) \
ATOMIC64_OP(op, op1, op2) \
ATOMIC64_OP_RETURN(op, op1, op2) \
ATOMIC64_FETCH_OP(op, op1, op2)
#define atomic64_andnot atomic64_andnot
ATOMIC64_OPS(add, add.f, adc)
ATOMIC64_OPS(sub, sub.f, sbc)
ATOMIC64_OPS(and, and, and)
ATOMIC64_OPS(andnot, bic, bic)
ATOMIC64_OPS(or, or, or)
ATOMIC64_OPS(xor, xor, xor)
#undef ATOMIC64_OPS
#undef ATOMIC64_FETCH_OP
#undef ATOMIC64_OP_RETURN
#undef ATOMIC64_OP
static inline long long
atomic64_cmpxchg(atomic64_t *ptr, long long expected, long long new)
{
long long prev;
smp_mb();
__asm__ __volatile__(
"1: llockd %0, [%1] \n"
" brne %L0, %L2, 2f \n"
" brne %H0, %H2, 2f \n"
" scondd %3, [%1] \n"
" bnz 1b \n"
"2: \n"
: "=&r"(prev)
: "r"(ptr), "ir"(expected), "r"(new)
: "cc"); /* memory clobber comes from smp_mb() */
smp_mb();
return prev;
}
static inline long long atomic64_xchg(atomic64_t *ptr, long long new)
{
long long prev;
smp_mb();
__asm__ __volatile__(
"1: llockd %0, [%1] \n"
" scondd %2, [%1] \n"
" bnz 1b \n"
"2: \n"
: "=&r"(prev)
: "r"(ptr), "r"(new)
: "cc"); /* memory clobber comes from smp_mb() */
smp_mb();
return prev;
}
/**
* atomic64_dec_if_positive - decrement by 1 if old value positive
* @v: pointer of type atomic64_t
*
* The function returns the old value of *v minus 1, even if
* the atomic variable, v, was not decremented.
*/
static inline long long atomic64_dec_if_positive(atomic64_t *v)
{
long long val;
smp_mb();
__asm__ __volatile__(
"1: llockd %0, [%1] \n"
" sub.f %L0, %L0, 1 # w0 - 1, set C on borrow\n"
" sub.c %H0, %H0, 1 # if C set, w1 - 1\n"
" brlt %H0, 0, 2f \n"
" scondd %0, [%1] \n"
" bnz 1b \n"
"2: \n"
: "=&r"(val)
: "r"(&v->counter)
: "cc"); /* memory clobber comes from smp_mb() */
smp_mb();
return val;
}
/**
* atomic64_add_unless - add unless the number is a given value
* @v: pointer of type atomic64_t
* @a: the amount to add to v...
* @u: ...unless v is equal to u.
*
* if (v != u) { v += a; ret = 1} else {ret = 0}
* Returns 1 iff @v was not @u (i.e. if add actually happened)
*/
static inline int atomic64_add_unless(atomic64_t *v, long long a, long long u)
{
long long val;
int op_done;
smp_mb();
__asm__ __volatile__(
"1: llockd %0, [%2] \n"
" mov %1, 1 \n"
" brne %L0, %L4, 2f # continue to add since v != u \n"
" breq.d %H0, %H4, 3f # return since v == u \n"
" mov %1, 0 \n"
"2: \n"
" add.f %L0, %L0, %L3 \n"
" adc %H0, %H0, %H3 \n"
" scondd %0, [%2] \n"
" bnz 1b \n"
"3: \n"
: "=&r"(val), "=&r" (op_done)
: "r"(&v->counter), "r"(a), "r"(u)
: "cc"); /* memory clobber comes from smp_mb() */
smp_mb();
return op_done;
}
#define atomic64_add_negative(a, v) (atomic64_add_return((a), (v)) < 0)
#define atomic64_inc(v) atomic64_add(1LL, (v))
#define atomic64_inc_return(v) atomic64_add_return(1LL, (v))
#define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
#define atomic64_sub_and_test(a, v) (atomic64_sub_return((a), (v)) == 0)
#define atomic64_dec(v) atomic64_sub(1LL, (v))
#define atomic64_dec_return(v) atomic64_sub_return(1LL, (v))
#define atomic64_dec_and_test(v) (atomic64_dec_return((v)) == 0)
#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1LL, 0LL)
#endif /* !CONFIG_GENERIC_ATOMIC64 */
#endif /* !__ASSEMBLY__ */
#endif

2
arch/arc/include/asm/cache.h
View File

@ -54,7 +54,7 @@ extern char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len);
extern void read_decode_cache_bcr(void);
extern int ioc_exists;
extern unsigned long perip_base;
extern unsigned long perip_base, perip_end;
#endif /* !__ASSEMBLY__ */

38
arch/arc/include/asm/dwarf.h Normal file
View File

@ -0,0 +1,38 @@
/*
* Copyright (C) 2016-17 Synopsys, Inc. (www.synopsys.com)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _ASM_ARC_DWARF_H
#define _ASM_ARC_DWARF_H
#ifdef __ASSEMBLY__
#ifdef ARC_DW2_UNWIND_AS_CFI
#define CFI_STARTPROC .cfi_startproc
#define CFI_ENDPROC .cfi_endproc
#define CFI_DEF_CFA .cfi_def_cfa
#define CFI_REGISTER .cfi_register
#define CFI_REL_OFFSET .cfi_rel_offset
#define CFI_UNDEFINED .cfi_undefined
#else
#define CFI_IGNORE #
#define CFI_STARTPROC CFI_IGNORE
#define CFI_ENDPROC CFI_IGNORE
#define CFI_DEF_CFA CFI_IGNORE
#define CFI_REGISTER CFI_IGNORE
#define CFI_REL_OFFSET CFI_IGNORE
#define CFI_UNDEFINED CFI_IGNORE
#endif /* !ARC_DW2_UNWIND_AS_CFI */
#endif /* __ASSEMBLY__ */
#endif /* _ASM_ARC_DWARF_H */

3
arch/arc/include/asm/elf.h
View File

@ -23,8 +23,7 @@
/* ARC Relocations (kernel Modules only) */
#define R_ARC_32 0x4
#define R_ARC_32_ME 0x1B
#define R_ARC_S25H_PCREL 0x10
#define R_ARC_S25W_PCREL 0x11
#define R_ARC_32_PCREL 0x31
/*to set parameters in the core dumps */
#define ELF_ARCH EM_ARCOMPACT

2
arch/arc/include/asm/irqflags-arcv2.h
View File

@ -112,7 +112,7 @@ static inline long arch_local_save_flags(void)
*/
temp = (1 << 5) |
((!!(temp & STATUS_IE_MASK)) << CLRI_STATUS_IE_BIT) |
(temp & CLRI_STATUS_E_MASK);
((temp >> 1) & CLRI_STATUS_E_MASK);
return temp;
}

12
arch/arc/include/asm/linkage.h
View File

@ -9,6 +9,8 @@
#ifndef __ASM_LINKAGE_H
#define __ASM_LINKAGE_H
#include <asm/dwarf.h>
#ifdef __ASSEMBLY__
#define ASM_NL ` /* use '`' to mark new line in macro */
@ -32,6 +34,16 @@
#endif
.endm
#define ENTRY_CFI(name) \
.globl name ASM_NL \
ALIGN ASM_NL \
name: ASM_NL \
CFI_STARTPROC ASM_NL
#define END_CFI(name) \
CFI_ENDPROC ASM_NL \
.size name, .-name
#else /* !__ASSEMBLY__ */
#ifdef CONFIG_ARC_HAS_ICCM

3
arch/arc/include/asm/perf_event.h
View File

@ -118,6 +118,9 @@ static const char * const arc_pmu_ev_hw_map[] = {
[PERF_COUNT_ARC_ICM] = "icm", /* I-cache Miss */
[PERF_COUNT_ARC_EDTLB] = "edtlb", /* D-TLB Miss */
[PERF_COUNT_ARC_EITLB] = "eitlb", /* I-TLB Miss */
[PERF_COUNT_HW_CACHE_REFERENCES] = "imemrdc", /* Instr: mem read cached */
[PERF_COUNT_HW_CACHE_MISSES] = "dclm", /* D-cache Load Miss */
};
#define C(_x) PERF_COUNT_HW_CACHE_##_x

3
arch/arc/kernel/ctx_sw_asm.S
View File

@ -23,6 +23,7 @@
.global __switch_to
.type __switch_to, @function
__switch_to:
CFI_STARTPROC
/* Save regs on kernel mode stack of task */
st.a blink, [sp, -4]
@ -59,4 +60,4 @@ __switch_to:
ld.ab blink, [sp, 4]
j [blink]
END(__switch_to)
END_CFI(__switch_to)

24
arch/arc/kernel/entry.S
View File

@ -35,7 +35,7 @@ ENTRY(sys_clone_wrapper)
btst r10, TIF_SYSCALL_TRACE
bnz tracesys_exit
b ret_from_system_call
b .Lret_from_system_call
END(sys_clone_wrapper)
ENTRY(ret_from_fork)
@ -61,18 +61,6 @@ ENTRY(ret_from_fork)
b ret_from_exception
END(ret_from_fork)
#ifdef CONFIG_ARC_DW2_UNWIND
; Workaround for bug 94179 (STAR ):
; Despite -fasynchronous-unwind-tables, linker is not making dwarf2 unwinder
; section (.debug_frame) as loadable. So we force it here.
; This also fixes STAR 9000487933 where the prev-workaround (objcopy --setflag)
; would not work after a clean build due to kernel build system dependencies.
.section .debug_frame, "wa",@progbits
; Reset to .text as this file is included in entry-<isa>.S
.section .text, "ax",@progbits
#endif
;################### Non TLB Exception Handling #############################
; ---------------------------------------------
@ -260,20 +248,18 @@ ENTRY(EV_Trap)
; syscall num shd not exceed the total system calls avail
cmp r8, NR_syscalls
mov.hi r0, -ENOSYS
bhi ret_from_system_call
bhi .Lret_from_system_call
; Offset into the syscall_table and call handler
ld.as r9,[sys_call_table, r8]
jl [r9] ; Entry into Sys Call Handler
; fall through to ret_from_system_call
END(EV_Trap)
ENTRY(ret_from_system_call)
.Lret_from_system_call:
st r0, [sp, PT_r0] ; sys call return value in pt_regs
; fall through yet again to ret_from_exception
; fall through to ret_from_exception
END(EV_Trap)
;############# Return from Intr/Excp/Trap (Linux Specifics) ##############
;

2
arch/arc/kernel/intc-arcv2.c
View File

@ -74,7 +74,7 @@ void arc_init_IRQ(void)
tmp = read_aux_reg(0xa);
tmp |= STATUS_AD_MASK | (irq_prio << 1);
tmp &= ~STATUS_IE_MASK;
asm volatile("flag %0 \n"::"r"(tmp));
asm volatile("kflag %0 \n"::"r"(tmp));
}
static void arcv2_irq_mask(struct irq_data *data)

19
arch/arc/kernel/module.c
View File

@ -22,13 +22,9 @@ static inline void arc_write_me(unsigned short *addr, unsigned long value)
*(addr + 1) = (value & 0xffff);
}
/* ARC specific section quirks - before relocation loop in generic loader
*
* For dwarf unwinding out of modules, this needs to
* 1. Ensure the .debug_frame is allocatable (ARC Linker bug: despite
* -fasynchronous-unwind-tables it doesn't).
* 2. Since we are iterating thru sec hdr tbl anyways, make a note of
* the exact section index, for later use.
/*
* This gets called before relocation loop in generic loader
* Make a note of the section index of unwinding section
*/
int module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs,
char *secstr, struct module *mod)
@ -40,8 +36,7 @@ int module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs,
mod->arch.unw_info = NULL;
for (i = 1; i < hdr->e_shnum; i++) {
if (strcmp(secstr+sechdrs[i].sh_name, ".debug_frame") == 0) {
sechdrs[i].sh_flags |= SHF_ALLOC;
if (strcmp(secstr+sechdrs[i].sh_name, ".eh_frame") == 0) {
mod->arch.unw_sec_idx = i;
break;
}
@ -106,10 +101,12 @@ int apply_relocate_add(Elf32_Shdr *sechdrs,
*/
relo_type = ELF32_R_TYPE(rel_entry[i].r_info);
if (likely(R_ARC_32_ME == relo_type))
if (likely(R_ARC_32_ME == relo_type)) /* ME ( S + A ) */
arc_write_me((unsigned short *)location, relocation);
else if (R_ARC_32 == relo_type)
else if (R_ARC_32 == relo_type) /* ( S + A ) */
*((Elf32_Addr *) location) = relocation;
else if (R_ARC_32_PCREL == relo_type) /* ( S + A ) - PDATA ) */
*((Elf32_Addr *) location) = relocation - location;
else
goto relo_err;

6
arch/arc/kernel/perf_event.c
View File

@ -179,8 +179,8 @@ static int arc_pmu_event_init(struct perf_event *event)
if (arc_pmu->ev_hw_idx[event->attr.config] < 0)
return -ENOENT;
hwc->config |= arc_pmu->ev_hw_idx[event->attr.config];
pr_debug("init event %d with h/w %d \'%s\'\n",
(int) event->attr.config, (int) hwc->config,
pr_debug("init event %d with h/w %08x \'%s\'\n",
(int)event->attr.config, (int)hwc->config,
arc_pmu_ev_hw_map[event->attr.config]);
return 0;
@ -189,6 +189,8 @@ static int arc_pmu_event_init(struct perf_event *event)
if (ret < 0)
return ret;
hwc->config |= arc_pmu->ev_hw_idx[ret];
pr_debug("init cache event with h/w %08x \'%s\'\n",
(int)hwc->config, arc_pmu_ev_hw_map[ret]);
return 0;
default:
return -ENOENT;

5
arch/arc/kernel/setup.c
View File

@ -171,6 +171,7 @@ static const struct cpuinfo_data arc_cpu_tbl[] = {
#else
{ {0x50, "ARC HS38 R2.0"}, 0x51},
{ {0x52, "ARC HS38 R2.1"}, 0x52},
{ {0x53, "ARC HS38 R3.0"}, 0x53},
#endif
{ {0x00, NULL } }
};
@ -272,8 +273,8 @@ static char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len)
FIX_PTR(cpu);
n += scnprintf(buf + n, len - n,
"Vector Table\t: %#x\nUncached Base\t: %#lx\n",
cpu->vec_base, perip_base);
"Vector Table\t: %#x\nPeripherals\t: %#lx:%#lx\n",
cpu->vec_base, perip_base, perip_end);
if (cpu->extn.fpu_sp || cpu->extn.fpu_dp)
n += scnprintf(buf + n, len - n, "FPU\t\t: %s%s\n",

24
arch/arc/kernel/unwind.c
View File

@ -111,6 +111,8 @@ UNW_REGISTER_INFO};
#define DW_EH_PE_indirect 0x80
#define DW_EH_PE_omit 0xff
#define CIE_ID 0
typedef unsigned long uleb128_t;
typedef signed long sleb128_t;
@ -232,6 +234,7 @@ void __init arc_unwind_init(void)
static const u32 bad_cie, not_fde;
static const u32 *cie_for_fde(const u32 *fde, const struct unwind_table *);
static const u32 *__cie_for_fde(const u32 *fde);
static signed fde_pointer_type(const u32 *cie);
struct eh_frame_hdr_table_entry {
@ -338,10 +341,9 @@ static void init_unwind_hdr(struct unwind_table *table,
for (fde = table->address, tableSize = table->size, n = 0;
tableSize;
tableSize -= sizeof(*fde) + *fde, fde += 1 + *fde / sizeof(*fde)) {
/* const u32 *cie = fde + 1 - fde[1] / sizeof(*fde); */
const u32 *cie = (const u32 *)(fde[1]);
const u32 *cie = __cie_for_fde(fde);
if (fde[1] == 0xffffffff)
if (fde[1] == CIE_ID)
continue; /* this is a CIE */
ptr = (const u8 *)(fde + 2);
header->table[n].start = read_pointer(&ptr,
@ -504,6 +506,15 @@ static sleb128_t get_sleb128(const u8 **pcur, const u8 *end)
return value;
}
static const u32 *__cie_for_fde(const u32 *fde)
{
const u32 *cie;
cie = fde + 1 - fde[1] / sizeof(*fde);
return cie;
}
static const u32 *cie_for_fde(const u32 *fde, const struct unwind_table *table)
{
const u32 *cie;
@ -511,19 +522,18 @@ static const u32 *cie_for_fde(const u32 *fde, const struct unwind_table *table)
if (!*fde || (*fde & (sizeof(*fde) - 1)))
return &bad_cie;
if (fde[1] == 0xffffffff)
if (fde[1] == CIE_ID)
return &not_fde; /* this is a CIE */
if ((fde[1] & (sizeof(*fde) - 1)))
/* || fde[1] > (unsigned long)(fde + 1) - (unsigned long)table->address) */
return NULL; /* this is not a valid FDE */
/* cie = fde + 1 - fde[1] / sizeof(*fde); */
cie = (u32 *) fde[1];
cie = __cie_for_fde(fde);
if (*cie <= sizeof(*cie) + 4 || *cie >= fde[1] - sizeof(*fde)
|| (*cie & (sizeof(*cie) - 1))
|| (cie[1] != 0xffffffff))
|| (cie[1] != CIE_ID))
return NULL; /* this is not a (valid) CIE */
return cie;
}

21
arch/arc/kernel/vmlinux.lds.S
View File

@ -82,14 +82,6 @@ SECTIONS
PERCPU_SECTION(L1_CACHE_BYTES)
/*
* .exit.text is discard at runtime, not link time, to deal with
* references from .debug_frame
* It will be init freed, being inside [__init_start : __init_end]
*/
.exit.text : { EXIT_TEXT }
.exit.data : { EXIT_DATA }
. = ALIGN(PAGE_SIZE);
__init_end = .;
@ -120,18 +112,13 @@ SECTIONS
#ifdef CONFIG_ARC_DW2_UNWIND
. = ALIGN(PAGE_SIZE);
.debug_frame : {
.eh_frame : {
__start_unwind = .;
*(.debug_frame)
*(.eh_frame)
__end_unwind = .;
}
/*
* gcc 4.8 generates this for -fasynchonous-unwind-tables,
* while we still use the .debug_frame based unwinder
*/
/DISCARD/ : { *(.eh_frame) }
#else
/DISCARD/ : { *(.debug_frame) }
/DISCARD/ : { *(.eh_frame) }
#endif
NOTES
@ -148,7 +135,7 @@ SECTIONS
}
#ifndef CONFIG_DEBUG_INFO
/* open-coded because we need .debug_frame seperately for unwinding */
/DISCARD/ : { *(.debug_frame) }
/DISCARD/ : { *(.debug_aranges) }
/DISCARD/ : { *(.debug_pubnames) }
/DISCARD/ : { *(.debug_info) }

4
arch/arc/lib/memcmp.S
View File

@ -16,7 +16,7 @@
#define SHIFT r2
#endif
ENTRY(memcmp)
ENTRY_CFI(memcmp)
or r12,r0,r1
asl_s r12,r12,30
sub r3,r2,1
@ -149,4 +149,4 @@ ENTRY(memcmp)
.Lnil:
j_s.d [blink]
mov r0,0
END(memcmp)
END_CFI(memcmp)

4
arch/arc/lib/memcpy-700.S
View File

@ -8,7 +8,7 @@
#include <linux/linkage.h>
ENTRY(memcpy)
ENTRY_CFI(memcpy)
or r3,r0,r1
asl_s r3,r3,30
mov_s r5,r0
@ -63,4 +63,4 @@ ENTRY(memcpy)
.Lendbloop:
j_s.d [blink]
stb r12,[r5,0]
END(memcpy)
END_CFI(memcpy)

4
arch/arc/lib/memcpy-archs.S
View File

@ -40,7 +40,7 @@
# define ZOLAND 0xF
#endif
ENTRY(memcpy)
ENTRY_CFI(memcpy)
prefetch [r1] ; Prefetch the read location
prefetchw [r0] ; Prefetch the write location
mov.f 0, r2
@ -233,4 +233,4 @@ ENTRY(memcpy)
.Lcopybytewise_3:
j [blink]
END(memcpy)
END_CFI(memcpy)

8
arch/arc/lib/memset-archs.S
View File

@ -10,7 +10,7 @@
#undef PREALLOC_NOT_AVAIL
ENTRY(memset)
ENTRY_CFI(memset)
prefetchw [r0] ; Prefetch the write location
mov.f 0, r2
;;; if size is zero
@ -112,11 +112,11 @@ ENTRY(memset)
j [blink]
END(memset)
END_CFI(memset)
ENTRY(memzero)
ENTRY_CFI(memzero)
; adjust bzero args to memset args
mov r2, r1
b.d memset ;tail call so need to tinker with blink
mov r1, 0
END(memzero)
END_CFI(memzero)

8
arch/arc/lib/memset.S
View File

@ -10,7 +10,7 @@
#define SMALL 7 /* Must be at least 6 to deal with alignment/loop issues. */
ENTRY(memset)
ENTRY_CFI(memset)
mov_s r4,r0
or r12,r0,r2
bmsk.f r12,r12,1
@ -46,14 +46,14 @@ ENTRY(memset)
stb.ab r1,[r4,1]
.Ltiny_end:
j_s [blink]
END(memset)
END_CFI(memset)
; memzero: @r0 = mem, @r1 = size_t
; memset: @r0 = mem, @r1 = char, @r2 = size_t
ENTRY(memzero)
ENTRY_CFI(memzero)
; adjust bzero args to memset args
mov r2, r1
mov r1, 0
b memset ;tail call so need to tinker with blink
END(memzero)
END_CFI(memzero)

4
arch/arc/lib/strchr-700.S
View File

@ -13,7 +13,7 @@
#include <linux/linkage.h>
ENTRY(strchr)
ENTRY_CFI(strchr)
extb_s r1,r1
asl r5,r1,8
bmsk r2,r0,1
@ -130,4 +130,4 @@ ENTRY(strchr)
j_s.d [blink]
mov.mi r0,0
#endif /* ENDIAN */
END(strchr)
END_CFI(strchr)

4
arch/arc/lib/strcmp-archs.S
View File

@ -8,7 +8,7 @@
#include <linux/linkage.h>
ENTRY(strcmp)
ENTRY_CFI(strcmp)
or r2, r0, r1
bmsk_s r2, r2, 1
brne r2, 0, @.Lcharloop
@ -75,4 +75,4 @@ ENTRY(strcmp)
.Lcmpend:
j_s.d [blink]
sub r0, r2, r3
END(strcmp)
END_CFI(strcmp)

4
arch/arc/lib/strcmp.S
View File

@ -15,7 +15,7 @@
#include <linux/linkage.h>
ENTRY(strcmp)
ENTRY_CFI(strcmp)
or r2,r0,r1
bmsk_s r2,r2,1
brne r2,0,.Lcharloop
@ -93,4 +93,4 @@ ENTRY(strcmp)
.Lcmpend:
j_s.d [blink]
sub r0,r2,r3
END(strcmp)
END_CFI(strcmp)

4
arch/arc/lib/strcpy-700.S
View File

@ -18,7 +18,7 @@
#include <linux/linkage.h>
ENTRY(strcpy)
ENTRY_CFI(strcpy)
or r2,r0,r1
bmsk_s r2,r2,1
brne.d r2,0,charloop
@ -67,4 +67,4 @@ charloop:
brne.d r3,0,charloop
stb.ab r3,[r10,1]
j [blink]
END(strcpy)
END_CFI(strcpy)

4
arch/arc/lib/strlen.S
View File

@ -8,7 +8,7 @@
#include <linux/linkage.h>
ENTRY(strlen)
ENTRY_CFI(strlen)
or r3,r0,7
ld r2,[r3,-7]
ld.a r6,[r3,-3]
@ -80,4 +80,4 @@ ENTRY(strlen)
.Learly_end:
b.d .Lend
sub_s.ne r1,r1,r1
END(strlen)
END_CFI(strlen)

23
arch/arc/mm/cache.c
View File

@ -25,6 +25,7 @@ static int l2_line_sz;
int ioc_exists;
volatile int slc_enable = 1, ioc_enable = 1;
unsigned long perip_base = ARC_UNCACHED_ADDR_SPACE; /* legacy value for boot */
unsigned long perip_end = 0xFFFFFFFF; /* legacy value */
void (*_cache_line_loop_ic_fn)(phys_addr_t paddr, unsigned long vaddr,
unsigned long sz, const int cacheop);
@ -76,7 +77,6 @@ char *arc_cache_mumbojumbo(int c, char *buf, int len)
static void read_decode_cache_bcr_arcv2(int cpu)
{
struct cpuinfo_arc_cache *p_slc = &cpuinfo_arc700[cpu].slc;
struct bcr_generic uncached_space;
struct bcr_generic sbcr;
struct bcr_slc_cfg {
@ -95,6 +95,15 @@ static void read_decode_cache_bcr_arcv2(int cpu)
#endif
} cbcr;
struct bcr_volatile {
#ifdef CONFIG_CPU_BIG_ENDIAN
unsigned int start:4, limit:4, pad:22, order:1, disable:1;
#else
unsigned int disable:1, order:1, pad:22, limit:4, start:4;
#endif
} vol;
READ_BCR(ARC_REG_SLC_BCR, sbcr);
if (sbcr.ver) {
READ_BCR(ARC_REG_SLC_CFG, slc_cfg);
@ -107,10 +116,14 @@ static void read_decode_cache_bcr_arcv2(int cpu)
if (cbcr.c && ioc_enable)
ioc_exists = 1;
/* Legacy Data Uncached BCR is deprecated from v3 onwards */
READ_BCR(ARC_REG_D_UNCACH_BCR, uncached_space);
if (uncached_space.ver > 2)
perip_base = read_aux_reg(AUX_NON_VOL) & 0xF0000000;
/* HS 2.0 didn't have AUX_VOL */
if (cpuinfo_arc700[cpu].core.family > 0x51) {
READ_BCR(AUX_VOL, vol);
perip_base = vol.start << 28;
/* HS 3.0 has limit and strict-ordering fields */
if (cpuinfo_arc700[cpu].core.family > 0x52)
perip_end = (vol.limit << 28) - 1;
}
}
void read_decode_cache_bcr(void)

2
arch/arc/mm/ioremap.c
View File

@ -19,7 +19,7 @@ static inline bool arc_uncached_addr_space(phys_addr_t paddr)
if (is_isa_arcompact()) {
if (paddr >= ARC_UNCACHED_ADDR_SPACE)
return true;
} else if (paddr >= perip_base && paddr <= 0xFFFFFFFF) {
} else if (paddr >= perip_base && paddr <= perip_end) {
return true;
}

1
arch/arc/plat-sim/platform.c
View File

@ -24,6 +24,7 @@ static const char *simulation_compat[] __initconst = {
"snps,nsim_hs",
"snps,nsimosci",
"snps,nsimosci_hs",
"snps,zebu_hs",
NULL,
};