mfd: Add Rockchip rk817 audio CODEC support
Add rk817 codec support cell to rk808 mfd driver. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Tested-by: Maciej Matuszczyk <maccraft123mc@gmail.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
This commit is contained in:
Chris Morgan
Lee Jones
parent
6efb943b86
commit
4a1c456a57
@ -65,6 +65,7 @@ static bool rk817_is_volatile_reg(struct device *dev, unsigned int reg)
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switch (reg) {
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case RK817_SECONDS_REG ... RK817_WEEKS_REG:
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case RK817_RTC_STATUS_REG:
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case RK817_CODEC_DTOP_LPT_SRST:
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case RK817_INT_STS_REG0:
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case RK817_INT_STS_REG1:
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case RK817_INT_STS_REG2:
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@ -163,6 +164,7 @@ static const struct mfd_cell rk817s[] = {
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.num_resources = ARRAY_SIZE(rk817_rtc_resources),
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.resources = &rk817_rtc_resources[0],
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},
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{ .name = "rk817-codec",},
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};
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static const struct mfd_cell rk818s[] = {
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@ -201,6 +203,85 @@ static const struct rk808_reg_data rk808_pre_init_reg[] = {
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static const struct rk808_reg_data rk817_pre_init_reg[] = {
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{RK817_RTC_CTRL_REG, RTC_STOP, RTC_STOP},
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/* Codec specific registers */
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{ RK817_CODEC_DTOP_VUCTL, MASK_ALL, 0x03 },
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{ RK817_CODEC_DTOP_VUCTIME, MASK_ALL, 0x00 },
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{ RK817_CODEC_DTOP_LPT_SRST, MASK_ALL, 0x00 },
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{ RK817_CODEC_DTOP_DIGEN_CLKE, MASK_ALL, 0x00 },
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/* from vendor driver, CODEC_AREF_RTCFG0 not defined in data sheet */
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{ RK817_CODEC_AREF_RTCFG0, MASK_ALL, 0x00 },
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{ RK817_CODEC_AREF_RTCFG1, MASK_ALL, 0x06 },
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{ RK817_CODEC_AADC_CFG0, MASK_ALL, 0xc8 },
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/* from vendor driver, CODEC_AADC_CFG1 not defined in data sheet */
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{ RK817_CODEC_AADC_CFG1, MASK_ALL, 0x00 },
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{ RK817_CODEC_DADC_VOLL, MASK_ALL, 0x00 },
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{ RK817_CODEC_DADC_VOLR, MASK_ALL, 0x00 },
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{ RK817_CODEC_DADC_SR_ACL0, MASK_ALL, 0x00 },
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{ RK817_CODEC_DADC_ALC1, MASK_ALL, 0x00 },
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{ RK817_CODEC_DADC_ALC2, MASK_ALL, 0x00 },
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{ RK817_CODEC_DADC_NG, MASK_ALL, 0x00 },
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{ RK817_CODEC_DADC_HPF, MASK_ALL, 0x00 },
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{ RK817_CODEC_DADC_RVOLL, MASK_ALL, 0xff },
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{ RK817_CODEC_DADC_RVOLR, MASK_ALL, 0xff },
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{ RK817_CODEC_AMIC_CFG0, MASK_ALL, 0x70 },
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{ RK817_CODEC_AMIC_CFG1, MASK_ALL, 0x00 },
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{ RK817_CODEC_DMIC_PGA_GAIN, MASK_ALL, 0x66 },
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{ RK817_CODEC_DMIC_LMT1, MASK_ALL, 0x00 },
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{ RK817_CODEC_DMIC_LMT2, MASK_ALL, 0x00 },
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{ RK817_CODEC_DMIC_NG1, MASK_ALL, 0x00 },
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{ RK817_CODEC_DMIC_NG2, MASK_ALL, 0x00 },
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/* from vendor driver, CODEC_ADAC_CFG0 not defined in data sheet */
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{ RK817_CODEC_ADAC_CFG0, MASK_ALL, 0x00 },
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{ RK817_CODEC_ADAC_CFG1, MASK_ALL, 0x07 },
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{ RK817_CODEC_DDAC_POPD_DACST, MASK_ALL, 0x82 },
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{ RK817_CODEC_DDAC_VOLL, MASK_ALL, 0x00 },
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{ RK817_CODEC_DDAC_VOLR, MASK_ALL, 0x00 },
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{ RK817_CODEC_DDAC_SR_LMT0, MASK_ALL, 0x00 },
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{ RK817_CODEC_DDAC_LMT1, MASK_ALL, 0x00 },
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{ RK817_CODEC_DDAC_LMT2, MASK_ALL, 0x00 },
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{ RK817_CODEC_DDAC_MUTE_MIXCTL, MASK_ALL, 0xa0 },
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{ RK817_CODEC_DDAC_RVOLL, MASK_ALL, 0xff },
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{ RK817_CODEC_DADC_RVOLR, MASK_ALL, 0xff },
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{ RK817_CODEC_AMIC_CFG0, MASK_ALL, 0x70 },
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{ RK817_CODEC_AMIC_CFG1, MASK_ALL, 0x00 },
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{ RK817_CODEC_DMIC_PGA_GAIN, MASK_ALL, 0x66 },
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{ RK817_CODEC_DMIC_LMT1, MASK_ALL, 0x00 },
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{ RK817_CODEC_DMIC_LMT2, MASK_ALL, 0x00 },
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{ RK817_CODEC_DMIC_NG1, MASK_ALL, 0x00 },
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{ RK817_CODEC_DMIC_NG2, MASK_ALL, 0x00 },
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/* from vendor driver, CODEC_ADAC_CFG0 not defined in data sheet */
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{ RK817_CODEC_ADAC_CFG0, MASK_ALL, 0x00 },
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{ RK817_CODEC_ADAC_CFG1, MASK_ALL, 0x07 },
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{ RK817_CODEC_DDAC_POPD_DACST, MASK_ALL, 0x82 },
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{ RK817_CODEC_DDAC_VOLL, MASK_ALL, 0x00 },
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{ RK817_CODEC_DDAC_VOLR, MASK_ALL, 0x00 },
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{ RK817_CODEC_DDAC_SR_LMT0, MASK_ALL, 0x00 },
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{ RK817_CODEC_DDAC_LMT1, MASK_ALL, 0x00 },
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{ RK817_CODEC_DDAC_LMT2, MASK_ALL, 0x00 },
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{ RK817_CODEC_DDAC_MUTE_MIXCTL, MASK_ALL, 0xa0 },
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{ RK817_CODEC_DDAC_RVOLL, MASK_ALL, 0xff },
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{ RK817_CODEC_DDAC_RVOLR, MASK_ALL, 0xff },
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{ RK817_CODEC_AHP_ANTI0, MASK_ALL, 0x00 },
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{ RK817_CODEC_AHP_ANTI1, MASK_ALL, 0x00 },
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{ RK817_CODEC_AHP_CFG0, MASK_ALL, 0xe0 },
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{ RK817_CODEC_AHP_CFG1, MASK_ALL, 0x1f },
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{ RK817_CODEC_AHP_CP, MASK_ALL, 0x09 },
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{ RK817_CODEC_ACLASSD_CFG1, MASK_ALL, 0x69 },
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{ RK817_CODEC_ACLASSD_CFG2, MASK_ALL, 0x44 },
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{ RK817_CODEC_APLL_CFG0, MASK_ALL, 0x04 },
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{ RK817_CODEC_APLL_CFG1, MASK_ALL, 0x00 },
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{ RK817_CODEC_APLL_CFG2, MASK_ALL, 0x30 },
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{ RK817_CODEC_APLL_CFG3, MASK_ALL, 0x19 },
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{ RK817_CODEC_APLL_CFG4, MASK_ALL, 0x65 },
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{ RK817_CODEC_APLL_CFG5, MASK_ALL, 0x01 },
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{ RK817_CODEC_DI2S_CKM, MASK_ALL, 0x01 },
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{ RK817_CODEC_DI2S_RSD, MASK_ALL, 0x00 },
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{ RK817_CODEC_DI2S_RXCR1, MASK_ALL, 0x00 },
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{ RK817_CODEC_DI2S_RXCR2, MASK_ALL, 0x17 },
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{ RK817_CODEC_DI2S_RXCMD_TSD, MASK_ALL, 0x00 },
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{ RK817_CODEC_DI2S_TXCR1, MASK_ALL, 0x00 },
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{ RK817_CODEC_DI2S_TXCR2, MASK_ALL, 0x17 },
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{ RK817_CODEC_DI2S_TXCR3_TXCMD, MASK_ALL, 0x00 },
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{RK817_GPIO_INT_CFG, RK817_INT_POL_MSK, RK817_INT_POL_L},
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{RK817_SYS_CFG(1), RK817_HOTDIE_TEMP_MSK | RK817_TSD_TEMP_MSK,
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RK817_HOTDIE_105 | RK817_TSD_140},
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@ -437,6 +437,87 @@ enum rk809_reg_id {
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#define RK817_RTC_COMP_LSB_REG 0x10
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#define RK817_RTC_COMP_MSB_REG 0x11
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/* RK817 Codec Registers */
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#define RK817_CODEC_DTOP_VUCTL 0x12
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#define RK817_CODEC_DTOP_VUCTIME 0x13
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#define RK817_CODEC_DTOP_LPT_SRST 0x14
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#define RK817_CODEC_DTOP_DIGEN_CLKE 0x15
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#define RK817_CODEC_AREF_RTCFG0 0x16
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#define RK817_CODEC_AREF_RTCFG1 0x17
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#define RK817_CODEC_AADC_CFG0 0x18
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#define RK817_CODEC_AADC_CFG1 0x19
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#define RK817_CODEC_DADC_VOLL 0x1a
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#define RK817_CODEC_DADC_VOLR 0x1b
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#define RK817_CODEC_DADC_SR_ACL0 0x1e
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#define RK817_CODEC_DADC_ALC1 0x1f
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#define RK817_CODEC_DADC_ALC2 0x20
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#define RK817_CODEC_DADC_NG 0x21
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#define RK817_CODEC_DADC_HPF 0x22
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#define RK817_CODEC_DADC_RVOLL 0x23
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#define RK817_CODEC_DADC_RVOLR 0x24
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#define RK817_CODEC_AMIC_CFG0 0x27
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#define RK817_CODEC_AMIC_CFG1 0x28
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#define RK817_CODEC_DMIC_PGA_GAIN 0x29
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#define RK817_CODEC_DMIC_LMT1 0x2a
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#define RK817_CODEC_DMIC_LMT2 0x2b
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#define RK817_CODEC_DMIC_NG1 0x2c
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#define RK817_CODEC_DMIC_NG2 0x2d
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#define RK817_CODEC_ADAC_CFG0 0x2e
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#define RK817_CODEC_ADAC_CFG1 0x2f
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#define RK817_CODEC_DDAC_POPD_DACST 0x30
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#define RK817_CODEC_DDAC_VOLL 0x31
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#define RK817_CODEC_DDAC_VOLR 0x32
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#define RK817_CODEC_DDAC_SR_LMT0 0x35
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#define RK817_CODEC_DDAC_LMT1 0x36
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#define RK817_CODEC_DDAC_LMT2 0x37
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#define RK817_CODEC_DDAC_MUTE_MIXCTL 0x38
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#define RK817_CODEC_DDAC_RVOLL 0x39
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#define RK817_CODEC_DDAC_RVOLR 0x3a
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#define RK817_CODEC_AHP_ANTI0 0x3b
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#define RK817_CODEC_AHP_ANTI1 0x3c
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#define RK817_CODEC_AHP_CFG0 0x3d
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#define RK817_CODEC_AHP_CFG1 0x3e
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#define RK817_CODEC_AHP_CP 0x3f
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#define RK817_CODEC_ACLASSD_CFG1 0x40
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#define RK817_CODEC_ACLASSD_CFG2 0x41
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#define RK817_CODEC_APLL_CFG0 0x42
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#define RK817_CODEC_APLL_CFG1 0x43
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#define RK817_CODEC_APLL_CFG2 0x44
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#define RK817_CODEC_APLL_CFG3 0x45
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#define RK817_CODEC_APLL_CFG4 0x46
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#define RK817_CODEC_APLL_CFG5 0x47
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#define RK817_CODEC_DI2S_CKM 0x48
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#define RK817_CODEC_DI2S_RSD 0x49
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#define RK817_CODEC_DI2S_RXCR1 0x4a
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#define RK817_CODEC_DI2S_RXCR2 0x4b
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#define RK817_CODEC_DI2S_RXCMD_TSD 0x4c
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#define RK817_CODEC_DI2S_TXCR1 0x4d
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#define RK817_CODEC_DI2S_TXCR2 0x4e
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#define RK817_CODEC_DI2S_TXCR3_TXCMD 0x4f
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/* RK817_CODEC_DI2S_CKM */
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#define RK817_I2S_MODE_MASK (0x1 << 0)
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#define RK817_I2S_MODE_MST (0x1 << 0)
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#define RK817_I2S_MODE_SLV (0x0 << 0)
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/* RK817_CODEC_DDAC_MUTE_MIXCTL */
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#define DACMT_MASK (0x1 << 0)
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#define DACMT_ENABLE (0x1 << 0)
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#define DACMT_DISABLE (0x0 << 0)
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/* RK817_CODEC_DI2S_RXCR2 */
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#define VDW_RX_24BITS (0x17)
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#define VDW_RX_16BITS (0x0f)
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/* RK817_CODEC_DI2S_TXCR2 */
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#define VDW_TX_24BITS (0x17)
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#define VDW_TX_16BITS (0x0f)
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/* RK817_CODEC_AMIC_CFG0 */
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#define MIC_DIFF_MASK (0x1 << 7)
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#define MIC_DIFF_DIS (0x0 << 7)
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#define MIC_DIFF_EN (0x1 << 7)
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#define RK817_POWER_EN_REG(i) (0xb1 + (i))
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#define RK817_POWER_SLP_EN_REG(i) (0xb5 + (i))
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