MIPS: OCTEON: octeon-usb: Consolidate error messages
Console output currently looks like USB clocks initialized succesfully even in case of error. Fix that and use consistently dev_err for fatal errors otherwise dev_warn. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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@ -245,7 +245,7 @@ static int dwc3_octeon_config_power(struct device *dev, u64 base)
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power_active_low = 0;
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gpio = gpio_pwr[1];
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} else {
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dev_err(dev, "dwc3 controller clock init failure.\n");
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dev_err(dev, "invalid power configuration\n");
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return -EINVAL;
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}
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if ((OCTEON_IS_MODEL(OCTEON_CN73XX) ||
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@ -278,7 +278,7 @@ static int dwc3_octeon_config_power(struct device *dev, u64 base)
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uctl_host_cfg.s.ppc_en = 0;
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uctl_host_cfg.s.ppc_active_high_en = 0;
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cvmx_write_csr(base + UCTL_HOST_CFG, uctl_host_cfg.u64);
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dev_warn(dev, "dwc3 controller clock init failure.\n");
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dev_info(dev, "power control disabled\n");
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}
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return 0;
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}
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@ -301,19 +301,19 @@ static int dwc3_octeon_clocks_start(struct device *dev, u64 base)
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i = of_property_read_u32(dev->of_node,
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"refclk-frequency", &clock_rate);
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if (i) {
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pr_err("No UCTL \"refclk-frequency\"\n");
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dev_err(dev, "No UCTL \"refclk-frequency\"\n");
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return -EINVAL;
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}
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i = of_property_read_string(dev->of_node,
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"refclk-type-ss", &ss_clock_type);
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if (i) {
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pr_err("No UCTL \"refclk-type-ss\"\n");
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dev_err(dev, "No UCTL \"refclk-type-ss\"\n");
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return -EINVAL;
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}
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i = of_property_read_string(dev->of_node,
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"refclk-type-hs", &hs_clock_type);
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if (i) {
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pr_err("No UCTL \"refclk-type-hs\"\n");
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dev_err(dev, "No UCTL \"refclk-type-hs\"\n");
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return -EINVAL;
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}
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if (strcmp("dlmc_ref_clk0", ss_clock_type) == 0) {
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@ -322,29 +322,29 @@ static int dwc3_octeon_clocks_start(struct device *dev, u64 base)
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else if (strcmp(hs_clock_type, "pll_ref_clk") == 0)
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ref_clk_sel = 2;
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else
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pr_err("Invalid HS clock type %s, using pll_ref_clk instead\n",
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hs_clock_type);
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dev_warn(dev, "Invalid HS clock type %s, using pll_ref_clk instead\n",
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hs_clock_type);
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} else if (strcmp(ss_clock_type, "dlmc_ref_clk1") == 0) {
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if (strcmp(hs_clock_type, "dlmc_ref_clk1") == 0)
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ref_clk_sel = 1;
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else if (strcmp(hs_clock_type, "pll_ref_clk") == 0)
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ref_clk_sel = 3;
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else {
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pr_err("Invalid HS clock type %s, using pll_ref_clk instead\n",
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hs_clock_type);
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dev_warn(dev, "Invalid HS clock type %s, using pll_ref_clk instead\n",
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hs_clock_type);
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ref_clk_sel = 3;
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}
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} else
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pr_err("Invalid SS clock type %s, using dlmc_ref_clk0 instead\n",
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ss_clock_type);
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dev_warn(dev, "Invalid SS clock type %s, using dlmc_ref_clk0 instead\n",
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ss_clock_type);
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if ((ref_clk_sel == 0 || ref_clk_sel == 1) &&
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(clock_rate != 100000000))
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pr_err("Invalid UCTL clock rate of %u, using 100000000 instead\n",
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clock_rate);
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(clock_rate != 100000000))
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dev_warn(dev, "Invalid UCTL clock rate of %u, using 100000000 instead\n",
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clock_rate);
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} else {
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pr_err("No USB UCTL device node\n");
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dev_err(dev, "No USB UCTL device node\n");
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return -EINVAL;
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}
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@ -396,8 +396,8 @@ static int dwc3_octeon_clocks_start(struct device *dev, u64 base)
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uctl_ctl.s.ref_clk_div2 = 0;
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switch (clock_rate) {
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default:
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dev_err(dev, "Invalid ref_clk %u, using 100000000 instead\n",
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clock_rate);
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dev_warn(dev, "Invalid ref_clk %u, using 100000000 instead\n",
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clock_rate);
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fallthrough;
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case 100000000:
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mpll_mul = 0x19;
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@ -438,10 +438,8 @@ static int dwc3_octeon_clocks_start(struct device *dev, u64 base)
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udelay(10);
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/* Steo 8c: Setup power-power control. */
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if (dwc3_octeon_config_power(dev, base)) {
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dev_err(dev, "Error configuring power.\n");
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if (dwc3_octeon_config_power(dev, base))
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return -EINVAL;
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}
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/* Step 8d: Deassert UAHC reset signal. */
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uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
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@ -529,10 +527,10 @@ static int __init dwc3_octeon_device_init(void)
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}
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mutex_lock(&dwc3_octeon_clocks_mutex);
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dwc3_octeon_clocks_start(&pdev->dev, (u64)base);
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if (dwc3_octeon_clocks_start(&pdev->dev, (u64)base) == 0)
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dev_info(&pdev->dev, "clocks initialized.\n");
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dwc3_octeon_set_endian_mode((u64)base);
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dwc3_octeon_phy_reset((u64)base);
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dev_info(&pdev->dev, "clocks initialized.\n");
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mutex_unlock(&dwc3_octeon_clocks_mutex);
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devm_iounmap(&pdev->dev, base);
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devm_release_mem_region(&pdev->dev, res->start,
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