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Merge branches 'clk-counted', 'clk-imx', 'clk-amlogic', 'clk-binding' and 'clk-rockchip' into clk-next

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* clk-counted:
  clk: bcm: rpi: Assign ->num before accessing ->hws
  clk: bcm: dvp: Assign ->num before accessing ->hws

* clk-imx:
  clk: imx: imx8mp: Convert to platform remove callback returning void
  clk: imx: imx8mp: Switch to RUNTIME_PM_OPS()
  clk: imx: add i.MX95 BLK CTL clk driver
  dt-bindings: clock: support i.MX95 Display Master CSR module
  dt-bindings: clock: support i.MX95 BLK CTL module
  dt-bindings: clock: add i.MX95 clock header
  clk: imx: imx8mp: Add pm_runtime support for power saving

* clk-amlogic:
  clk: meson: s4: fix module autoloading
  clk: meson: fix module license to GPL only
  clk: meson: g12a: make VCLK2 and ENCL clock path configurable by CCF
  clk: meson: add vclk driver
  clk: meson: pll: print out pll name when unable to lock it
  clk: meson: s4: pll: determine maximum register in regmap config
  clk: meson: s4: peripherals: determine maximum register in regmap config
  clk: meson: a1: pll: determine maximum register in regmap config
  clk: meson: a1: peripherals: determine maximum register in regmap config

* clk-binding:
  dt-bindings: clock: fixed: Define a preferred node name

* clk-rockchip:
  clk: rockchip: rk3568: Add PLL rate for 724 MHz
  clk: rockchip: Remove an unused field in struct rockchip_mmc_clock
  clk: rockchip: rk3588: Add reset line for HDMI Receiver
  clk: rockchip: rk3568: Add missing USB480M_PHY mux
  dt-bindings: reset: Define reset id used for HDMI Receiver
  dt-bindings: clock: rockchip: add USB480M_PHY mux
This commit is contained in:
Stephen Boyd 2024-05-16 18:09:08 -07:00
commit 4a35e6fc41
41 changed files with 1037 additions and 63 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
Documentation/devicetree/bindings/clock/fixed-clock.yaml
View File

@ -11,6 +11,15 @@ maintainers:
- Stephen Boyd <sboyd@kernel.org>
properties:
$nodename:
anyOf:
- description:
Preferred name is 'clock-<freq>' with <freq> being the output
frequency as defined in the 'clock-frequency' property.
pattern: "^clock-([0-9]+|[a-z0-9-]+)$"
- description: Any name allowed
deprecated: true
compatible:
const: fixed-clock

9
Documentation/devicetree/bindings/clock/fixed-factor-clock.yaml
View File

@ -11,6 +11,15 @@ maintainers:
- Stephen Boyd <sboyd@kernel.org>
properties:
$nodename:
anyOf:
- description:
If the frequency is fixed, the preferred name is 'clock-<freq>' with
<freq> being the output frequency.
pattern: "^clock-([0-9]+|[0-9a-z-]+)$"
- description: Any name allowed
deprecated: true
compatible:
enum:
- fixed-factor-clock

56
Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml Normal file
View File

@ -0,0 +1,56 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/nxp,imx95-blk-ctl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP i.MX95 Block Control
maintainers:
- Peng Fan <peng.fan@nxp.com>
properties:
compatible:
items:
- enum:
- nxp,imx95-lvds-csr
- nxp,imx95-display-csr
- nxp,imx95-camera-csr
- nxp,imx95-vpu-csr
- const: syscon
reg:
maxItems: 1
power-domains:
maxItems: 1
clocks:
maxItems: 1
'#clock-cells':
const: 1
description:
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See
include/dt-bindings/clock/nxp,imx95-clock.h
required:
- compatible
- reg
- '#clock-cells'
- power-domains
- clocks
additionalProperties: false
examples:
- |
syscon@4c410000 {
compatible = "nxp,imx95-vpu-csr", "syscon";
reg = <0x4c410000 0x10000>;
#clock-cells = <1>;
clocks = <&scmi_clk 114>;
power-domains = <&scmi_devpd 21>;
};
...

64
Documentation/devicetree/bindings/clock/nxp,imx95-display-master-csr.yaml Normal file
View File

@ -0,0 +1,64 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/nxp,imx95-display-master-csr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP i.MX95 Display Master Block Control
maintainers:
- Peng Fan <peng.fan@nxp.com>
properties:
compatible:
items:
- const: nxp,imx95-display-master-csr
- const: syscon
reg:
maxItems: 1
power-domains:
maxItems: 1
clocks:
maxItems: 1
'#clock-cells':
const: 1
description:
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See
include/dt-bindings/clock/nxp,imx95-clock.h
mux-controller:
type: object
$ref: /schemas/mux/reg-mux.yaml
required:
- compatible
- reg
- '#clock-cells'
- mux-controller
- power-domains
- clocks
additionalProperties: false
examples:
- |
syscon@4c410000 {
compatible = "nxp,imx95-display-master-csr", "syscon";
reg = <0x4c410000 0x10000>;
#clock-cells = <1>;
clocks = <&scmi_clk 62>;
power-domains = <&scmi_devpd 3>;
mux: mux-controller {
compatible = "mmio-mux";
#mux-control-cells = <1>;
mux-reg-masks = <0x4 0x00000001>; /* Pixel_link_sel */
idle-states = <0>;
};
};
...

3
drivers/clk/bcm/clk-bcm2711-dvp.c
View File

@ -56,6 +56,8 @@ static int clk_dvp_probe(struct platform_device *pdev)
if (ret)
return ret;
data->num = NR_CLOCKS;
data->hws[0] = clk_hw_register_gate_parent_data(&pdev->dev,
"hdmi0-108MHz",
&clk_dvp_parent, 0,
@ -76,7 +78,6 @@ static int clk_dvp_probe(struct platform_device *pdev)
goto unregister_clk0;
}
data->num = NR_CLOCKS;
ret = of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_onecell_get,
data);
if (ret)

2
drivers/clk/bcm/clk-raspberrypi.c
View File

@ -371,8 +371,8 @@ static int raspberrypi_discover_clocks(struct raspberrypi_clk *rpi,
if (IS_ERR(hw))
return PTR_ERR(hw);
data->hws[clks->id] = hw;
data->num = clks->id + 1;
data->hws[clks->id] = hw;
}
clks++;

7
drivers/clk/imx/Kconfig
View File

@ -114,6 +114,13 @@ config CLK_IMX93
help
Build the driver for i.MX93 CCM Clock Driver
config CLK_IMX95_BLK_CTL
tristate "IMX95 Clock Driver for BLK CTL"
depends on ARCH_MXC || COMPILE_TEST
select MXC_CLK
help
Build the clock driver for i.MX95 BLK CTL
config CLK_IMXRT1050
tristate "IMXRT1050 CCM Clock Driver"
depends on SOC_IMXRT || COMPILE_TEST

1
drivers/clk/imx/Makefile
View File

@ -31,6 +31,7 @@ obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o clk-imx8mp-audiomix.o
obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o
obj-$(CONFIG_CLK_IMX93) += clk-imx93.o
obj-$(CONFIG_CLK_IMX95_BLK_CTL) += clk-imx95-blk-ctl.o
obj-$(CONFIG_MXC_CLK_SCU) += clk-imx-scu.o clk-imx-lpcg-scu.o clk-imx-acm.o
clk-imx-scu-$(CONFIG_CLK_IMX8QXP) += clk-scu.o clk-imx8qxp.o \

155
drivers/clk/imx/clk-imx8mp-audiomix.c
View File

@ -7,10 +7,12 @@
#include <linux/clk-provider.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <dt-bindings/clock/imx8mp-clock.h>
@ -18,6 +20,7 @@
#define CLKEN0 0x000
#define CLKEN1 0x004
#define EARC 0x200
#define SAI1_MCLK_SEL 0x300
#define SAI2_MCLK_SEL 0x304
#define SAI3_MCLK_SEL 0x308
@ -26,6 +29,11 @@
#define SAI7_MCLK_SEL 0x314
#define PDM_SEL 0x318
#define SAI_PLL_GNRL_CTL 0x400
#define SAI_PLL_FDIVL_CTL0 0x404
#define SAI_PLL_FDIVL_CTL1 0x408
#define SAI_PLL_SSCG_CTL 0x40C
#define SAI_PLL_MNIT_CTL 0x410
#define IPG_LP_CTRL 0x504
#define SAIn_MCLK1_PARENT(n) \
static const struct clk_parent_data \
@ -182,26 +190,82 @@ static struct clk_imx8mp_audiomix_sel sels[] = {
CLK_SAIn(7)
};
static const u16 audiomix_regs[] = {
CLKEN0,
CLKEN1,
EARC,
SAI1_MCLK_SEL,
SAI2_MCLK_SEL,
SAI3_MCLK_SEL,
SAI5_MCLK_SEL,
SAI6_MCLK_SEL,
SAI7_MCLK_SEL,
PDM_SEL,
SAI_PLL_GNRL_CTL,
SAI_PLL_FDIVL_CTL0,
SAI_PLL_FDIVL_CTL1,
SAI_PLL_SSCG_CTL,
SAI_PLL_MNIT_CTL,
IPG_LP_CTRL,
};
struct clk_imx8mp_audiomix_priv {
void __iomem *base;
u32 regs_save[ARRAY_SIZE(audiomix_regs)];
/* Must be last */
struct clk_hw_onecell_data clk_data;
};
static void clk_imx8mp_audiomix_save_restore(struct device *dev, bool save)
{
struct clk_imx8mp_audiomix_priv *priv = dev_get_drvdata(dev);
void __iomem *base = priv->base;
int i;
if (save) {
for (i = 0; i < ARRAY_SIZE(audiomix_regs); i++)
priv->regs_save[i] = readl(base + audiomix_regs[i]);
} else {
for (i = 0; i < ARRAY_SIZE(audiomix_regs); i++)
writel(priv->regs_save[i], base + audiomix_regs[i]);
}
}
static int clk_imx8mp_audiomix_probe(struct platform_device *pdev)
{
struct clk_hw_onecell_data *priv;
struct clk_imx8mp_audiomix_priv *priv;
struct clk_hw_onecell_data *clk_hw_data;
struct device *dev = &pdev->dev;
void __iomem *base;
struct clk_hw *hw;
int i;
int i, ret;
priv = devm_kzalloc(dev,
struct_size(priv, hws, IMX8MP_CLK_AUDIOMIX_END),
struct_size(priv, clk_data.hws, IMX8MP_CLK_AUDIOMIX_END),
GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->num = IMX8MP_CLK_AUDIOMIX_END;
clk_hw_data = &priv->clk_data;
clk_hw_data->num = IMX8MP_CLK_AUDIOMIX_END;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
priv->base = base;
dev_set_drvdata(dev, priv);
/*
* pm_runtime_enable needs to be called before clk register.
* That is to make core->rpm_enabled to be true for clock
* usage.
*/
pm_runtime_get_noresume(dev);
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
for (i = 0; i < ARRAY_SIZE(sels); i++) {
if (sels[i].num_parents == 1) {
hw = devm_clk_hw_register_gate_parent_data(dev,
@ -216,10 +280,12 @@ static int clk_imx8mp_audiomix_probe(struct platform_device *pdev)
0, NULL, NULL);
}
if (IS_ERR(hw))
return PTR_ERR(hw);
if (IS_ERR(hw)) {
ret = PTR_ERR(hw);
goto err_clk_register;
}
priv->hws[sels[i].clkid] = hw;
clk_hw_data->hws[sels[i].clkid] = hw;
}
/* SAI PLL */
@ -228,39 +294,84 @@ static int clk_imx8mp_audiomix_probe(struct platform_device *pdev)
ARRAY_SIZE(clk_imx8mp_audiomix_pll_parents),
CLK_SET_RATE_NO_REPARENT, base + SAI_PLL_GNRL_CTL,
0, 2, 0, NULL, NULL);
priv->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_REF_SEL] = hw;
clk_hw_data->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_REF_SEL] = hw;
hw = imx_dev_clk_hw_pll14xx(dev, "sai_pll", "sai_pll_ref_sel",
base + 0x400, &imx_1443x_pll);
if (IS_ERR(hw))
return PTR_ERR(hw);
priv->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL] = hw;
if (IS_ERR(hw)) {
ret = PTR_ERR(hw);
goto err_clk_register;
}
clk_hw_data->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL] = hw;
hw = devm_clk_hw_register_mux_parent_data_table(dev,
"sai_pll_bypass", clk_imx8mp_audiomix_pll_bypass_sels,
ARRAY_SIZE(clk_imx8mp_audiomix_pll_bypass_sels),
CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
base + SAI_PLL_GNRL_CTL, 16, 1, 0, NULL, NULL);
if (IS_ERR(hw))
return PTR_ERR(hw);
priv->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_BYPASS] = hw;
if (IS_ERR(hw)) {
ret = PTR_ERR(hw);
goto err_clk_register;
}
clk_hw_data->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_BYPASS] = hw;
hw = devm_clk_hw_register_gate(dev, "sai_pll_out", "sai_pll_bypass",
0, base + SAI_PLL_GNRL_CTL, 13,
0, NULL);
if (IS_ERR(hw))
return PTR_ERR(hw);
priv->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_OUT] = hw;
if (IS_ERR(hw)) {
ret = PTR_ERR(hw);
goto err_clk_register;
}
clk_hw_data->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_OUT] = hw;
hw = devm_clk_hw_register_fixed_factor(dev, "sai_pll_out_div2",
"sai_pll_out", 0, 1, 2);
if (IS_ERR(hw))
return PTR_ERR(hw);
if (IS_ERR(hw)) {
ret = PTR_ERR(hw);
goto err_clk_register;
}
return devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get,
priv);
ret = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get,
clk_hw_data);
if (ret)
goto err_clk_register;
pm_runtime_put_sync(dev);
return 0;
err_clk_register:
pm_runtime_put_sync(dev);
pm_runtime_disable(dev);
return ret;
}
static void clk_imx8mp_audiomix_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
}
static int clk_imx8mp_audiomix_runtime_suspend(struct device *dev)
{
clk_imx8mp_audiomix_save_restore(dev, true);
return 0;
}
static int clk_imx8mp_audiomix_runtime_resume(struct device *dev)
{
clk_imx8mp_audiomix_save_restore(dev, false);
return 0;
}
static const struct dev_pm_ops clk_imx8mp_audiomix_pm_ops = {
RUNTIME_PM_OPS(clk_imx8mp_audiomix_runtime_suspend,
clk_imx8mp_audiomix_runtime_resume, NULL)
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
};
static const struct of_device_id clk_imx8mp_audiomix_of_match[] = {
{ .compatible = "fsl,imx8mp-audio-blk-ctrl" },
{ /* sentinel */ }
@ -269,9 +380,11 @@ MODULE_DEVICE_TABLE(of, clk_imx8mp_audiomix_of_match);
static struct platform_driver clk_imx8mp_audiomix_driver = {
.probe = clk_imx8mp_audiomix_probe,
.remove_new = clk_imx8mp_audiomix_remove,
.driver = {
.name = "imx8mp-audio-blk-ctrl",
.of_match_table = clk_imx8mp_audiomix_of_match,
.pm = pm_ptr(&clk_imx8mp_audiomix_pm_ops),
},
};

438
drivers/clk/imx/clk-imx95-blk-ctl.c Normal file
View File

@ -0,0 +1,438 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2024 NXP
*/
#include <dt-bindings/clock/nxp,imx95-clock.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/pm_runtime.h>
#include <linux/debugfs.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/types.h>
enum {
CLK_GATE,
CLK_DIVIDER,
CLK_MUX,
};
struct imx95_blk_ctl {
struct device *dev;
spinlock_t lock;
struct clk *clk_apb;
void __iomem *base;
/* clock gate register */
u32 clk_reg_restore;
};
struct imx95_blk_ctl_clk_dev_data {
const char *name;
const char * const *parent_names;
u32 num_parents;
u32 reg;
u32 bit_idx;
u32 bit_width;
u32 clk_type;
u32 flags;
u32 flags2;
u32 type;
};
struct imx95_blk_ctl_dev_data {
const struct imx95_blk_ctl_clk_dev_data *clk_dev_data;
u32 num_clks;
bool rpm_enabled;
u32 clk_reg_offset;
};
static const struct imx95_blk_ctl_clk_dev_data vpublk_clk_dev_data[] = {
[IMX95_CLK_VPUBLK_WAVE] = {
.name = "vpublk_wave_vpu",
.parent_names = (const char *[]){ "vpu", },
.num_parents = 1,
.reg = 8,
.bit_idx = 0,
.type = CLK_GATE,
.flags = CLK_SET_RATE_PARENT,
.flags2 = CLK_GATE_SET_TO_DISABLE,
},
[IMX95_CLK_VPUBLK_JPEG_ENC] = {
.name = "vpublk_jpeg_enc",
.parent_names = (const char *[]){ "vpujpeg", },
.num_parents = 1,
.reg = 8,
.bit_idx = 1,
.type = CLK_GATE,
.flags = CLK_SET_RATE_PARENT,
.flags2 = CLK_GATE_SET_TO_DISABLE,
},
[IMX95_CLK_VPUBLK_JPEG_DEC] = {
.name = "vpublk_jpeg_dec",
.parent_names = (const char *[]){ "vpujpeg", },
.num_parents = 1,
.reg = 8,
.bit_idx = 2,
.type = CLK_GATE,
.flags = CLK_SET_RATE_PARENT,
.flags2 = CLK_GATE_SET_TO_DISABLE,
}
};
static const struct imx95_blk_ctl_dev_data vpublk_dev_data = {
.num_clks = ARRAY_SIZE(vpublk_clk_dev_data),
.clk_dev_data = vpublk_clk_dev_data,
.rpm_enabled = true,
.clk_reg_offset = 8,
};
static const struct imx95_blk_ctl_clk_dev_data camblk_clk_dev_data[] = {
[IMX95_CLK_CAMBLK_CSI2_FOR0] = {
.name = "camblk_csi2_for0",
.parent_names = (const char *[]){ "camisi", },
.num_parents = 1,
.reg = 0,
.bit_idx = 0,
.type = CLK_GATE,
.flags = CLK_SET_RATE_PARENT,
.flags2 = CLK_GATE_SET_TO_DISABLE,
},
[IMX95_CLK_CAMBLK_CSI2_FOR1] = {
.name = "camblk_csi2_for1",
.parent_names = (const char *[]){ "camisi", },
.num_parents = 1,
.reg = 0,
.bit_idx = 1,
.type = CLK_GATE,
.flags = CLK_SET_RATE_PARENT,
.flags2 = CLK_GATE_SET_TO_DISABLE,
},
[IMX95_CLK_CAMBLK_ISP_AXI] = {
.name = "camblk_isp_axi",
.parent_names = (const char *[]){ "camaxi", },
.num_parents = 1,
.reg = 0,
.bit_idx = 4,
.type = CLK_GATE,
.flags = CLK_SET_RATE_PARENT,
.flags2 = CLK_GATE_SET_TO_DISABLE,
},
[IMX95_CLK_CAMBLK_ISP_PIXEL] = {
.name = "camblk_isp_pixel",
.parent_names = (const char *[]){ "camisi", },
.num_parents = 1,
.reg = 0,
.bit_idx = 5,
.type = CLK_GATE,
.flags = CLK_SET_RATE_PARENT,
.flags2 = CLK_GATE_SET_TO_DISABLE,
},
[IMX95_CLK_CAMBLK_ISP] = {
.name = "camblk_isp",
.parent_names = (const char *[]){ "camisi", },
.num_parents = 1,
.reg = 0,
.bit_idx = 6,
.type = CLK_GATE,
.flags = CLK_SET_RATE_PARENT,
.flags2 = CLK_GATE_SET_TO_DISABLE,
}
};
static const struct imx95_blk_ctl_dev_data camblk_dev_data = {
.num_clks = ARRAY_SIZE(camblk_clk_dev_data),
.clk_dev_data = camblk_clk_dev_data,
.clk_reg_offset = 0,
};
static const struct imx95_blk_ctl_clk_dev_data lvds_clk_dev_data[] = {
[IMX95_CLK_DISPMIX_LVDS_PHY_DIV] = {
.name = "ldb_phy_div",
.parent_names = (const char *[]){ "ldbpll", },
.num_parents = 1,
.reg = 0,
.bit_idx = 0,
.bit_width = 1,
.type = CLK_DIVIDER,
.flags2 = CLK_DIVIDER_POWER_OF_TWO,
},
[IMX95_CLK_DISPMIX_LVDS_CH0_GATE] = {
.name = "lvds_ch0_gate",
.parent_names = (const char *[]){ "ldb_phy_div", },
.num_parents = 1,
.reg = 0,
.bit_idx = 1,
.bit_width = 1,
.type = CLK_GATE,
.flags = CLK_SET_RATE_PARENT,
.flags2 = CLK_GATE_SET_TO_DISABLE,
},
[IMX95_CLK_DISPMIX_LVDS_CH1_GATE] = {
.name = "lvds_ch1_gate",
.parent_names = (const char *[]){ "ldb_phy_div", },
.num_parents = 1,
.reg = 0,
.bit_idx = 2,
.bit_width = 1,
.type = CLK_GATE,
.flags = CLK_SET_RATE_PARENT,
.flags2 = CLK_GATE_SET_TO_DISABLE,
},
[IMX95_CLK_DISPMIX_PIX_DI0_GATE] = {
.name = "lvds_di0_gate",
.parent_names = (const char *[]){ "ldb_pll_div7", },
.num_parents = 1,
.reg = 0,
.bit_idx = 3,
.bit_width = 1,
.type = CLK_GATE,
.flags = CLK_SET_RATE_PARENT,
.flags2 = CLK_GATE_SET_TO_DISABLE,
},
[IMX95_CLK_DISPMIX_PIX_DI1_GATE] = {
.name = "lvds_di1_gate",
.parent_names = (const char *[]){ "ldb_pll_div7", },
.num_parents = 1,
.reg = 0,
.bit_idx = 4,
.bit_width = 1,
.type = CLK_GATE,
.flags = CLK_SET_RATE_PARENT,
.flags2 = CLK_GATE_SET_TO_DISABLE,
},
};
static const struct imx95_blk_ctl_dev_data lvds_csr_dev_data = {
.num_clks = ARRAY_SIZE(lvds_clk_dev_data),
.clk_dev_data = lvds_clk_dev_data,
.clk_reg_offset = 0,
};
static const struct imx95_blk_ctl_clk_dev_data dispmix_csr_clk_dev_data[] = {
[IMX95_CLK_DISPMIX_ENG0_SEL] = {
.name = "disp_engine0_sel",
.parent_names = (const char *[]){"videopll1", "dsi_pll", "ldb_pll_div7", },
.num_parents = 4,
.reg = 0,
.bit_idx = 0,
.bit_width = 2,
.type = CLK_MUX,
.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
},
[IMX95_CLK_DISPMIX_ENG1_SEL] = {
.name = "disp_engine1_sel",
.parent_names = (const char *[]){"videopll1", "dsi_pll", "ldb_pll_div7", },
.num_parents = 4,
.reg = 0,
.bit_idx = 2,
.bit_width = 2,
.type = CLK_MUX,
.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
}
};
static const struct imx95_blk_ctl_dev_data dispmix_csr_dev_data = {
.num_clks = ARRAY_SIZE(dispmix_csr_clk_dev_data),
.clk_dev_data = dispmix_csr_clk_dev_data,
.clk_reg_offset = 0,
};
static int imx95_bc_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
const struct imx95_blk_ctl_dev_data *bc_data;
struct imx95_blk_ctl *bc;
struct clk_hw_onecell_data *clk_hw_data;
struct clk_hw **hws;
void __iomem *base;
int i, ret;
bc = devm_kzalloc(dev, sizeof(*bc), GFP_KERNEL);
if (!bc)
return -ENOMEM;
bc->dev = dev;
dev_set_drvdata(&pdev->dev, bc);
spin_lock_init(&bc->lock);
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
bc->base = base;
bc->clk_apb = devm_clk_get(dev, NULL);
if (IS_ERR(bc->clk_apb))
return dev_err_probe(dev, PTR_ERR(bc->clk_apb), "failed to get APB clock\n");
ret = clk_prepare_enable(bc->clk_apb);
if (ret) {
dev_err(dev, "failed to enable apb clock: %d\n", ret);
return ret;
}
bc_data = of_device_get_match_data(dev);
if (!bc_data)
return devm_of_platform_populate(dev);
clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, bc_data->num_clks),
GFP_KERNEL);
if (!clk_hw_data)
return -ENOMEM;
if (bc_data->rpm_enabled)
pm_runtime_enable(&pdev->dev);
clk_hw_data->num = bc_data->num_clks;
hws = clk_hw_data->hws;
for (i = 0; i < bc_data->num_clks; i++) {
const struct imx95_blk_ctl_clk_dev_data *data = &bc_data->clk_dev_data[i];
void __iomem *reg = base + data->reg;
if (data->type == CLK_MUX) {
hws[i] = clk_hw_register_mux(dev, data->name, data->parent_names,
data->num_parents, data->flags, reg,
data->bit_idx, data->bit_width,
data->flags2, &bc->lock);
} else if (data->type == CLK_DIVIDER) {
hws[i] = clk_hw_register_divider(dev, data->name, data->parent_names[0],
data->flags, reg, data->bit_idx,
data->bit_width, data->flags2, &bc->lock);
} else {
hws[i] = clk_hw_register_gate(dev, data->name, data->parent_names[0],
data->flags, reg, data->bit_idx,
data->flags2, &bc->lock);
}
if (IS_ERR(hws[i])) {
ret = PTR_ERR(hws[i]);
dev_err(dev, "failed to register: %s:%d\n", data->name, ret);
goto cleanup;
}
}
ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, clk_hw_data);
if (ret)
goto cleanup;
ret = devm_of_platform_populate(dev);
if (ret) {
of_clk_del_provider(dev->of_node);
goto cleanup;
}
if (pm_runtime_enabled(bc->dev))
clk_disable_unprepare(bc->clk_apb);
return 0;
cleanup:
for (i = 0; i < bc_data->num_clks; i++) {
if (IS_ERR_OR_NULL(hws[i]))
continue;
clk_hw_unregister(hws[i]);
}
if (bc_data->rpm_enabled)
pm_runtime_disable(&pdev->dev);
return ret;
}
#ifdef CONFIG_PM
static int imx95_bc_runtime_suspend(struct device *dev)
{
struct imx95_blk_ctl *bc = dev_get_drvdata(dev);
clk_disable_unprepare(bc->clk_apb);
return 0;
}
static int imx95_bc_runtime_resume(struct device *dev)
{
struct imx95_blk_ctl *bc = dev_get_drvdata(dev);
return clk_prepare_enable(bc->clk_apb);
}
#endif
#ifdef CONFIG_PM_SLEEP
static int imx95_bc_suspend(struct device *dev)
{
struct imx95_blk_ctl *bc = dev_get_drvdata(dev);
const struct imx95_blk_ctl_dev_data *bc_data;
int ret;
bc_data = of_device_get_match_data(dev);
if (!bc_data)
return 0;
if (bc_data->rpm_enabled) {
ret = pm_runtime_get_sync(bc->dev);
if (ret < 0) {
pm_runtime_put_noidle(bc->dev);
return ret;
}
}
bc->clk_reg_restore = readl(bc->base + bc_data->clk_reg_offset);
return 0;
}
static int imx95_bc_resume(struct device *dev)
{
struct imx95_blk_ctl *bc = dev_get_drvdata(dev);
const struct imx95_blk_ctl_dev_data *bc_data;
bc_data = of_device_get_match_data(dev);
if (!bc_data)
return 0;
writel(bc->clk_reg_restore, bc->base + bc_data->clk_reg_offset);
if (bc_data->rpm_enabled)
pm_runtime_put(bc->dev);
return 0;
}
#endif
static const struct dev_pm_ops imx95_bc_pm_ops = {
SET_RUNTIME_PM_OPS(imx95_bc_runtime_suspend, imx95_bc_runtime_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(imx95_bc_suspend, imx95_bc_resume)
};
static const struct of_device_id imx95_bc_of_match[] = {
{ .compatible = "nxp,imx95-camera-csr", .data = &camblk_dev_data },
{ .compatible = "nxp,imx95-display-master-csr", },
{ .compatible = "nxp,imx95-lvds-csr", .data = &lvds_csr_dev_data },
{ .compatible = "nxp,imx95-display-csr", .data = &dispmix_csr_dev_data },
{ .compatible = "nxp,imx95-vpu-csr", .data = &vpublk_dev_data },
{ /* Sentinel */ },
};
MODULE_DEVICE_TABLE(of, imx95_bc_of_match);
static struct platform_driver imx95_bc_driver = {
.probe = imx95_bc_probe,
.driver = {
.name = "imx95-blk-ctl",
.of_match_table = imx95_bc_of_match,
.pm = &imx95_bc_pm_ops,
},
};
module_platform_driver(imx95_bc_driver);
MODULE_DESCRIPTION("NXP i.MX95 blk ctl driver");
MODULE_AUTHOR("Peng Fan <peng.fan@nxp.com>");
MODULE_LICENSE("GPL");

5
drivers/clk/meson/Kconfig
View File

@ -30,6 +30,10 @@ config COMMON_CLK_MESON_VID_PLL_DIV
tristate
select COMMON_CLK_MESON_REGMAP
config COMMON_CLK_MESON_VCLK
tristate
select COMMON_CLK_MESON_REGMAP
config COMMON_CLK_MESON_CLKC_UTILS
tristate
@ -140,6 +144,7 @@ config COMMON_CLK_G12A
select COMMON_CLK_MESON_EE_CLKC
select COMMON_CLK_MESON_CPU_DYNDIV
select COMMON_CLK_MESON_VID_PLL_DIV
select COMMON_CLK_MESON_VCLK
select MFD_SYSCON
help
Support for the clock controller on Amlogic S905D2, S905X2 and S905Y2

1
drivers/clk/meson/Makefile
View File

@ -12,6 +12,7 @@ obj-$(CONFIG_COMMON_CLK_MESON_PLL) += clk-pll.o
obj-$(CONFIG_COMMON_CLK_MESON_REGMAP) += clk-regmap.o
obj-$(CONFIG_COMMON_CLK_MESON_SCLK_DIV) += sclk-div.o
obj-$(CONFIG_COMMON_CLK_MESON_VID_PLL_DIV) += vid-pll-div.o
obj-$(CONFIG_COMMON_CLK_MESON_VCLK) += vclk.o
# Amlogic Clock controllers

1
drivers/clk/meson/a1-peripherals.c
View File

@ -2187,6 +2187,7 @@ static struct regmap_config a1_periphs_regmap_cfg = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.max_register = DMC_CLK_CTRL,
};
static struct meson_clk_hw_data a1_periphs_clks = {

1
drivers/clk/meson/a1-pll.c
View File

@ -299,6 +299,7 @@ static struct regmap_config a1_pll_regmap_cfg = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.max_register = ANACTRL_HIFIPLL_STS,
};
static struct meson_clk_hw_data a1_pll_clks = {

2
drivers/clk/meson/axg-aoclk.c
View File

@ -340,4 +340,4 @@ static struct platform_driver axg_aoclkc_driver = {
};
module_platform_driver(axg_aoclkc_driver);
MODULE_LICENSE("GPL v2");
MODULE_LICENSE("GPL");

2
drivers/clk/meson/axg-audio.c
View File

@ -1877,4 +1877,4 @@ module_platform_driver(axg_audio_driver);
MODULE_DESCRIPTION("Amlogic AXG/G12A/SM1 Audio Clock driver");
MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
MODULE_LICENSE("GPL v2");
MODULE_LICENSE("GPL");

2
drivers/clk/meson/axg.c
View File

@ -2185,4 +2185,4 @@ static struct platform_driver axg_driver = {
};
module_platform_driver(axg_driver);
MODULE_LICENSE("GPL v2");
MODULE_LICENSE("GPL");

2
drivers/clk/meson/clk-cpu-dyndiv.c
View File

@ -69,4 +69,4 @@ EXPORT_SYMBOL_GPL(meson_clk_cpu_dyndiv_ops);
MODULE_DESCRIPTION("Amlogic CPU Dynamic Clock divider");
MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
MODULE_LICENSE("GPL v2");
MODULE_LICENSE("GPL");

2
drivers/clk/meson/clk-dualdiv.c
View File

@ -140,4 +140,4 @@ EXPORT_SYMBOL_GPL(meson_clk_dualdiv_ro_ops);
MODULE_DESCRIPTION("Amlogic dual divider driver");
MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
MODULE_LICENSE("GPL v2");
MODULE_LICENSE("GPL");

2
drivers/clk/meson/clk-mpll.c
View File

@ -177,4 +177,4 @@ EXPORT_SYMBOL_GPL(meson_clk_mpll_ops);
MODULE_DESCRIPTION("Amlogic MPLL driver");
MODULE_AUTHOR("Michael Turquette <mturquette@baylibre.com>");
MODULE_LICENSE("GPL v2");
MODULE_LICENSE("GPL");

2
drivers/clk/meson/clk-phase.c
View File

@ -183,4 +183,4 @@ EXPORT_SYMBOL_GPL(meson_sclk_ws_inv_ops);
MODULE_DESCRIPTION("Amlogic phase driver");
MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
MODULE_LICENSE("GPL v2");
MODULE_LICENSE("GPL");

6
drivers/clk/meson/clk-pll.c
View File

@ -436,8 +436,8 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
ret = meson_clk_pll_enable(hw);
if (ret) {
pr_warn("%s: pll did not lock, trying to restore old rate %lu\n",
__func__, old_rate);
pr_warn("%s: pll %s didn't lock, trying to set old rate %lu\n",
__func__, clk_hw_get_name(hw), old_rate);
/*
* FIXME: Do we really need/want this HACK ?
* It looks unsafe. what happens if the clock gets into a
@ -486,4 +486,4 @@ EXPORT_SYMBOL_GPL(meson_clk_pll_ro_ops);
MODULE_DESCRIPTION("Amlogic PLL driver");
MODULE_AUTHOR("Carlo Caione <carlo@endlessm.com>");
MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
MODULE_LICENSE("GPL v2");
MODULE_LICENSE("GPL");

2
drivers/clk/meson/clk-regmap.c
View File

@ -183,4 +183,4 @@ EXPORT_SYMBOL_GPL(clk_regmap_mux_ro_ops);
MODULE_DESCRIPTION("Amlogic regmap backed clock driver");
MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
MODULE_LICENSE("GPL v2");
MODULE_LICENSE("GPL");

2
drivers/clk/meson/g12a-aoclk.c
View File

@ -475,4 +475,4 @@ static struct platform_driver g12a_aoclkc_driver = {
};
module_platform_driver(g12a_aoclkc_driver);
MODULE_LICENSE("GPL v2");
MODULE_LICENSE("GPL");

74
drivers/clk/meson/g12a.c
View File

@ -22,6 +22,7 @@
#include "clk-regmap.h"
#include "clk-cpu-dyndiv.h"
#include "vid-pll-div.h"
#include "vclk.h"
#include "meson-eeclk.h"
#include "g12a.h"
@ -3165,7 +3166,7 @@ static struct clk_regmap g12a_vclk2_sel = {
.ops = &clk_regmap_mux_ops,
.parent_hws = g12a_vclk_parent_hws,
.num_parents = ARRAY_SIZE(g12a_vclk_parent_hws),
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
.flags = CLK_SET_RATE_NO_REPARENT,
},
};
@ -3193,7 +3194,6 @@ static struct clk_regmap g12a_vclk2_input = {
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_sel.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
},
};
@ -3215,19 +3215,32 @@ static struct clk_regmap g12a_vclk_div = {
};
static struct clk_regmap g12a_vclk2_div = {
.data = &(struct clk_regmap_div_data){
.offset = HHI_VIID_CLK_DIV,
.data = &(struct meson_vclk_div_data){
.div = {
.reg_off = HHI_VIID_CLK_DIV,
.shift = 0,
.width = 8,
},
.enable = {
.reg_off = HHI_VIID_CLK_DIV,
.shift = 16,
.width = 1,
},
.reset = {
.reg_off = HHI_VIID_CLK_DIV,
.shift = 17,
.width = 1,
},
.flags = CLK_DIVIDER_ROUND_CLOSEST,
},
.hw.init = &(struct clk_init_data){
.name = "vclk2_div",
.ops = &clk_regmap_divider_ops,
.ops = &meson_vclk_div_ops,
.parent_hws = (const struct clk_hw *[]) {
&g12a_vclk2_input.hw
},
.num_parents = 1,
.flags = CLK_GET_RATE_NOCACHE,
.flags = CLK_SET_RATE_GATE,
},
};
@ -3246,16 +3259,24 @@ static struct clk_regmap g12a_vclk = {
};
static struct clk_regmap g12a_vclk2 = {
.data = &(struct clk_regmap_gate_data){
.offset = HHI_VIID_CLK_CNTL,
.bit_idx = 19,
.data = &(struct meson_vclk_gate_data){
.enable = {
.reg_off = HHI_VIID_CLK_CNTL,
.shift = 19,
.width = 1,
},
.reset = {
.reg_off = HHI_VIID_CLK_CNTL,
.shift = 15,
.width = 1,
},
},
.hw.init = &(struct clk_init_data) {
.name = "vclk2",
.ops = &clk_regmap_gate_ops,
.ops = &meson_vclk_gate_ops,
.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_div.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
.flags = CLK_SET_RATE_PARENT,
},
};
@ -3339,7 +3360,7 @@ static struct clk_regmap g12a_vclk2_div1 = {
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
.flags = CLK_SET_RATE_PARENT,
},
};
@ -3353,7 +3374,7 @@ static struct clk_regmap g12a_vclk2_div2_en = {
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
.flags = CLK_SET_RATE_PARENT,
},
};
@ -3367,7 +3388,7 @@ static struct clk_regmap g12a_vclk2_div4_en = {
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
.flags = CLK_SET_RATE_PARENT,
},
};
@ -3381,7 +3402,7 @@ static struct clk_regmap g12a_vclk2_div6_en = {
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
.flags = CLK_SET_RATE_PARENT,
},
};
@ -3395,7 +3416,7 @@ static struct clk_regmap g12a_vclk2_div12_en = {
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
.flags = CLK_SET_RATE_PARENT,
},
};
@ -3461,6 +3482,7 @@ static struct clk_fixed_factor g12a_vclk2_div2 = {
&g12a_vclk2_div2_en.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
@ -3474,6 +3496,7 @@ static struct clk_fixed_factor g12a_vclk2_div4 = {
&g12a_vclk2_div4_en.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
@ -3487,6 +3510,7 @@ static struct clk_fixed_factor g12a_vclk2_div6 = {
&g12a_vclk2_div6_en.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
@ -3500,6 +3524,7 @@ static struct clk_fixed_factor g12a_vclk2_div12 = {
&g12a_vclk2_div12_en.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
@ -3561,7 +3586,7 @@ static struct clk_regmap g12a_cts_encl_sel = {
.ops = &clk_regmap_mux_ops,
.parent_hws = g12a_cts_parent_hws,
.num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
},
};
@ -3717,15 +3742,26 @@ static struct clk_regmap g12a_mipi_dsi_pxclk_sel = {
.ops = &clk_regmap_mux_ops,
.parent_hws = g12a_mipi_dsi_pxclk_parent_hws,
.num_parents = ARRAY_SIZE(g12a_mipi_dsi_pxclk_parent_hws),
.flags = CLK_SET_RATE_NO_REPARENT,
.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
},
};
/*
* FIXME: Force as bypass by forcing a single /1 table entry, and doensn't on boot value
* when setting a clock whith this node in the clock path, but doesn't garantee the divider
* is at /1 at boot until a rate is set.
*/
static const struct clk_div_table g12a_mipi_dsi_pxclk_div_table[] = {
{ .val = 0, .div = 1 },
{ /* sentinel */ },
};
static struct clk_regmap g12a_mipi_dsi_pxclk_div = {
.data = &(struct clk_regmap_div_data){
.offset = HHI_MIPIDSI_PHY_CLK_CNTL,
.shift = 0,
.width = 7,
.table = g12a_mipi_dsi_pxclk_div_table,
},
.hw.init = &(struct clk_init_data){
.name = "mipi_dsi_pxclk_div",
@ -5578,4 +5614,4 @@ static struct platform_driver g12a_driver = {
};
module_platform_driver(g12a_driver);
MODULE_LICENSE("GPL v2");
MODULE_LICENSE("GPL");

2
drivers/clk/meson/gxbb-aoclk.c
View File

@ -300,4 +300,4 @@ static struct platform_driver gxbb_aoclkc_driver = {
},
};
module_platform_driver(gxbb_aoclkc_driver);
MODULE_LICENSE("GPL v2");
MODULE_LICENSE("GPL");

2
drivers/clk/meson/gxbb.c
View File

@ -3569,4 +3569,4 @@ static struct platform_driver gxbb_driver = {
};
module_platform_driver(gxbb_driver);
MODULE_LICENSE("GPL v2");
MODULE_LICENSE("GPL");

2
drivers/clk/meson/meson-aoclk.c
View File

@ -89,4 +89,4 @@ int meson_aoclkc_probe(struct platform_device *pdev)
return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, (void *)&data->hw_clks);
}
EXPORT_SYMBOL_GPL(meson_aoclkc_probe);
MODULE_LICENSE("GPL v2");
MODULE_LICENSE("GPL");

2
drivers/clk/meson/meson-eeclk.c
View File

@ -58,4 +58,4 @@ int meson_eeclkc_probe(struct platform_device *pdev)
return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, (void *)&data->hw_clks);
}
EXPORT_SYMBOL_GPL(meson_eeclkc_probe);
MODULE_LICENSE("GPL v2");
MODULE_LICENSE("GPL");

2
drivers/clk/meson/s4-peripherals.c
View File

@ -3751,6 +3751,7 @@ static struct regmap_config clkc_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.max_register = CLKCTRL_DEMOD_CLK_CTRL,
};
static struct meson_clk_hw_data s4_periphs_clks = {
@ -3799,6 +3800,7 @@ static const struct of_device_id clkc_match_table[] = {
},
{}
};
MODULE_DEVICE_TABLE(of, clkc_match_table);
static struct platform_driver s4_driver = {
.probe = meson_s4_periphs_probe,

2
drivers/clk/meson/s4-pll.c
View File

@ -798,6 +798,7 @@ static struct regmap_config clkc_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.max_register = ANACTRL_HDMIPLL_CTRL0,
};
static struct meson_clk_hw_data s4_pll_clks = {
@ -853,6 +854,7 @@ static const struct of_device_id clkc_match_table[] = {
},
{}
};
MODULE_DEVICE_TABLE(of, clkc_match_table);
static struct platform_driver s4_driver = {
.probe = meson_s4_pll_probe,

2
drivers/clk/meson/sclk-div.c
View File

@ -251,4 +251,4 @@ EXPORT_SYMBOL_GPL(meson_sclk_div_ops);
MODULE_DESCRIPTION("Amlogic Sample divider driver");
MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
MODULE_LICENSE("GPL v2");
MODULE_LICENSE("GPL");

141
drivers/clk/meson/vclk.c Normal file
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@ -0,0 +1,141 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2024 Neil Armstrong <neil.armstrong@linaro.org>
*/
#include <linux/module.h>
#include "vclk.h"
/* The VCLK gate has a supplementary reset bit to pulse after ungating */
static inline struct meson_vclk_gate_data *
clk_get_meson_vclk_gate_data(struct clk_regmap *clk)
{
return (struct meson_vclk_gate_data *)clk->data;
}
static int meson_vclk_gate_enable(struct clk_hw *hw)
{
struct clk_regmap *clk = to_clk_regmap(hw);
struct meson_vclk_gate_data *vclk = clk_get_meson_vclk_gate_data(clk);
meson_parm_write(clk->map, &vclk->enable, 1);
/* Do a reset pulse */
meson_parm_write(clk->map, &vclk->reset, 1);
meson_parm_write(clk->map, &vclk->reset, 0);
return 0;
}
static void meson_vclk_gate_disable(struct clk_hw *hw)
{
struct clk_regmap *clk = to_clk_regmap(hw);
struct meson_vclk_gate_data *vclk = clk_get_meson_vclk_gate_data(clk);
meson_parm_write(clk->map, &vclk->enable, 0);
}
static int meson_vclk_gate_is_enabled(struct clk_hw *hw)
{
struct clk_regmap *clk = to_clk_regmap(hw);
struct meson_vclk_gate_data *vclk = clk_get_meson_vclk_gate_data(clk);
return meson_parm_read(clk->map, &vclk->enable);
}
const struct clk_ops meson_vclk_gate_ops = {
.enable = meson_vclk_gate_enable,
.disable = meson_vclk_gate_disable,
.is_enabled = meson_vclk_gate_is_enabled,
};
EXPORT_SYMBOL_GPL(meson_vclk_gate_ops);
/* The VCLK Divider has supplementary reset & enable bits */
static inline struct meson_vclk_div_data *
clk_get_meson_vclk_div_data(struct clk_regmap *clk)
{
return (struct meson_vclk_div_data *)clk->data;
}
static unsigned long meson_vclk_div_recalc_rate(struct clk_hw *hw,
unsigned long prate)
{
struct clk_regmap *clk = to_clk_regmap(hw);
struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);
return divider_recalc_rate(hw, prate, meson_parm_read(clk->map, &vclk->div),
vclk->table, vclk->flags, vclk->div.width);
}
static int meson_vclk_div_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct clk_regmap *clk = to_clk_regmap(hw);
struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);
return divider_determine_rate(hw, req, vclk->table, vclk->div.width,
vclk->flags);
}
static int meson_vclk_div_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_regmap *clk = to_clk_regmap(hw);
struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);
int ret;
ret = divider_get_val(rate, parent_rate, vclk->table, vclk->div.width,
vclk->flags);
if (ret < 0)
return ret;
meson_parm_write(clk->map, &vclk->div, ret);
return 0;
};
static int meson_vclk_div_enable(struct clk_hw *hw)
{
struct clk_regmap *clk = to_clk_regmap(hw);
struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);
/* Unreset the divider when ungating */
meson_parm_write(clk->map, &vclk->reset, 0);
meson_parm_write(clk->map, &vclk->enable, 1);
return 0;
}
static void meson_vclk_div_disable(struct clk_hw *hw)
{
struct clk_regmap *clk = to_clk_regmap(hw);
struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);
/* Reset the divider when gating */
meson_parm_write(clk->map, &vclk->enable, 0);
meson_parm_write(clk->map, &vclk->reset, 1);
}
static int meson_vclk_div_is_enabled(struct clk_hw *hw)
{
struct clk_regmap *clk = to_clk_regmap(hw);
struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);
return meson_parm_read(clk->map, &vclk->enable);
}
const struct clk_ops meson_vclk_div_ops = {
.recalc_rate = meson_vclk_div_recalc_rate,
.determine_rate = meson_vclk_div_determine_rate,
.set_rate = meson_vclk_div_set_rate,
.enable = meson_vclk_div_enable,
.disable = meson_vclk_div_disable,
.is_enabled = meson_vclk_div_is_enabled,
};
EXPORT_SYMBOL_GPL(meson_vclk_div_ops);
MODULE_DESCRIPTION("Amlogic vclk clock driver");
MODULE_AUTHOR("Neil Armstrong <neil.armstrong@linaro.org>");
MODULE_LICENSE("GPL");

51
drivers/clk/meson/vclk.h Normal file
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@ -0,0 +1,51 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2024 Neil Armstrong <neil.armstrong@linaro.org>
*/
#ifndef __VCLK_H
#define __VCLK_H
#include "clk-regmap.h"
#include "parm.h"
/**
* struct meson_vclk_gate_data - vclk_gate regmap backed specific data
*
* @enable: vclk enable field
* @reset: vclk reset field
* @flags: hardware-specific flags
*
* Flags:
* Same as clk_gate except CLK_GATE_HIWORD_MASK which is ignored
*/
struct meson_vclk_gate_data {
struct parm enable;
struct parm reset;
u8 flags;
};
extern const struct clk_ops meson_vclk_gate_ops;
/**
* struct meson_vclk_div_data - vclk_div regmap back specific data
*
* @div: divider field
* @enable: vclk divider enable field
* @reset: vclk divider reset field
* @table: array of value/divider pairs, last entry should have div = 0
*
* Flags:
* Same as clk_divider except CLK_DIVIDER_HIWORD_MASK which is ignored
*/
struct meson_vclk_div_data {
struct parm div;
struct parm enable;
struct parm reset;
const struct clk_div_table *table;
u8 flags;
};
extern const struct clk_ops meson_vclk_div_ops;
#endif /* __VCLK_H */

2
drivers/clk/meson/vid-pll-div.c
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@ -96,4 +96,4 @@ EXPORT_SYMBOL_GPL(meson_vid_pll_div_ro_ops);
MODULE_DESCRIPTION("Amlogic video pll divider driver");
MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
MODULE_LICENSE("GPL v2");
MODULE_LICENSE("GPL");

1
drivers/clk/rockchip/clk-mmc-phase.c
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@ -14,7 +14,6 @@
struct rockchip_mmc_clock {
struct clk_hw hw;
void __iomem *reg;
int id;
int shift;
int cached_phase;
struct notifier_block clk_rate_change_nb;

5
drivers/clk/rockchip/clk-rk3568.c
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@ -64,6 +64,7 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0),
RK3036_PLL_RATE(724000000, 3, 181, 2, 1, 1, 0),
RK3036_PLL_RATE(700000000, 3, 350, 4, 1, 1, 0),
RK3036_PLL_RATE(696000000, 1, 116, 4, 1, 1, 0),
RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0),
@ -215,6 +216,7 @@ static const struct rockchip_cpuclk_reg_data rk3568_cpuclk_data = {
PNAME(mux_pll_p) = { "xin24m" };
PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc_32k" };
PNAME(mux_usb480m_phy_p) = { "clk_usbphy0_480m", "clk_usbphy1_480m"};
PNAME(mux_armclk_p) = { "apll", "gpll" };
PNAME(clk_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "i2s0_mclkin", "xin_osc0_half" };
PNAME(clk_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "i2s0_mclkin", "xin_osc0_half" };
@ -485,6 +487,9 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = {
MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
RK3568_MODE_CON0, 14, 2, MFLAGS),
MUX(USB480M_PHY, "usb480m_phy", mux_usb480m_phy_p, CLK_SET_RATE_PARENT,
RK3568_MISC_CON2, 15, 1, MFLAGS),
/* PD_CORE */
COMPOSITE(0, "sclk_core_src", apll_gpll_npll_p, CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(2), 8, 2, MFLAGS, 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,

1
drivers/clk/rockchip/rst-rk3588.c
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@ -577,6 +577,7 @@ static const int rk3588_register_offset[] = {
/* SOFTRST_CON59 */
RK3588_CRU_RESET_OFFSET(SRST_A_HDCP1_BIU, 59, 6),
RK3588_CRU_RESET_OFFSET(SRST_A_HDMIRX_BIU, 59, 7),
RK3588_CRU_RESET_OFFSET(SRST_A_VO1_BIU, 59, 8),
RK3588_CRU_RESET_OFFSET(SRST_H_VOP1_BIU, 59, 9),
RK3588_CRU_RESET_OFFSET(SRST_H_VOP1_S_BIU, 59, 10),

28
include/dt-bindings/clock/nxp,imx95-clock.h Normal file
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@ -0,0 +1,28 @@
/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
/*
* Copyright 2024 NXP
*/
#ifndef __DT_BINDINGS_CLOCK_IMX95_H
#define __DT_BINDINGS_CLOCK_IMX95_H
#define IMX95_CLK_VPUBLK_WAVE 0
#define IMX95_CLK_VPUBLK_JPEG_ENC 1
#define IMX95_CLK_VPUBLK_JPEG_DEC 2
#define IMX95_CLK_CAMBLK_CSI2_FOR0 0
#define IMX95_CLK_CAMBLK_CSI2_FOR1 1
#define IMX95_CLK_CAMBLK_ISP_AXI 2
#define IMX95_CLK_CAMBLK_ISP_PIXEL 3
#define IMX95_CLK_CAMBLK_ISP 4
#define IMX95_CLK_DISPMIX_LVDS_PHY_DIV 0
#define IMX95_CLK_DISPMIX_LVDS_CH0_GATE 1
#define IMX95_CLK_DISPMIX_LVDS_CH1_GATE 2
#define IMX95_CLK_DISPMIX_PIX_DI0_GATE 3
#define IMX95_CLK_DISPMIX_PIX_DI1_GATE 4
#define IMX95_CLK_DISPMIX_ENG0_SEL 0
#define IMX95_CLK_DISPMIX_ENG1_SEL 1
#endif /* __DT_BINDINGS_CLOCK_IMX95_H */

1
include/dt-bindings/clock/rk3568-cru.h
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@ -78,6 +78,7 @@
#define CPLL_333M 9
#define ARMCLK 10
#define USB480M 11
#define USB480M_PHY 12
#define ACLK_CORE_NIU2BUS 18
#define CLK_CORE_PVTM 19
#define CLK_CORE_PVTM_CORE 20

2
include/dt-bindings/reset/rockchip,rk3588-cru.h
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@ -751,4 +751,6 @@
#define SRST_P_TRNG_CHK 658
#define SRST_TRNG_S 659
#define SRST_A_HDMIRX_BIU 660
#endif