iv/linux
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

drm/amd/display: Add green_sardine support to DC

Browse Source 
Display Core support for green_sardine

Signed-off-by: Roman Li <Roman.Li@amd.com>
Acked-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Roman Li 2020-10-08 13:28:41 -04:00 committed by Alex Deucher
parent d83d3ad61c
commit 4a5346df6a
4 changed files with 25 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/gpu/drm/amd/display/Kconfig
View File

@ -17,6 +17,14 @@ config DRM_AMD_DC_DCN
help
Raven, Navi and Renoir family support for display engine
config DRM_AMD_DC_GREEN_SARDINE
bool "Green Sardine support"
default y
depends on DRM_AMD_DC_DCN
help
Choose this option if you want to have
Green Sardine support for display engine
config DRM_AMD_DC_DCN3_0
bool "DCN 3.0 family"
depends on DRM_AMD_DC && X86

7
drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
View File

@ -166,6 +166,13 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p
rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
break;
}
#if defined(CONFIG_DRM_AMD_DC_GREEN_SARDINE)
if (ASICREV_IS_GREEN_SARDINE(asic_id.hw_internal_rev)) {
rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
break;
}
#endif
if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev)) {
rv2_clk_mgr_construct(ctx, clk_mgr, pp_smu);
break;

4
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
View File

@ -120,6 +120,10 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
dc_version = DCN_VERSION_1_01;
if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev))
dc_version = DCN_VERSION_2_1;
#if defined(CONFIG_DRM_AMD_DC_GREEN_SARDINE)
if (ASICREV_IS_GREEN_SARDINE(asic_id.hw_internal_rev))
dc_version = DCN_VERSION_2_1;
#endif
break;
#endif

6
drivers/gpu/drm/amd/display/include/dal_asic_id.h
View File

@ -205,6 +205,12 @@ enum {
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
#define ASICREV_IS_SIENNA_CICHLID_P(eChipRev) ((eChipRev >= NV_SIENNA_CICHLID_P_A0))
#endif
#if defined(CONFIG_DRM_AMD_DC_GREEN_SARDINE)
#define GREEN_SARDINE_A0 0xA1
#ifndef ASICREV_IS_GREEN_SARDINE
#define ASICREV_IS_GREEN_SARDINE(eChipRev) ((eChipRev >= GREEN_SARDINE_A0) && (eChipRev < 0xFF))
#endif
#endif
/*
* ASIC chip ID