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drm/amdgpu/umsch: power on/off UMSCH by DLDO

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VCN 4.0.5 uses DLDO.

Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Reviewed-by: Veerabadhran Gopalakrishnan <Veerabadhran.Gopalakrishnan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Lang Yu 2023-09-30 14:39:26 +08:00 committed by Alex Deucher
parent 617b472431
commit 4acf679f86
1 changed files with 26 additions and 0 deletions
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26
drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
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@ -34,6 +34,16 @@
#include "umsch_mm_4_0_api_def.h"
#include "umsch_mm_v4_0.h"
#define regUVD_IPX_DLDO_CONFIG 0x0064
#define regUVD_IPX_DLDO_CONFIG_BASE_IDX 1
#define regUVD_IPX_DLDO_STATUS 0x0065
#define regUVD_IPX_DLDO_STATUS_BASE_IDX 1
#define UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG__SHIFT 0x00000002
#define UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG_MASK 0x0000000cUL
#define UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS__SHIFT 0x00000001
#define UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS_MASK 0x00000002UL
static int umsch_mm_v4_0_load_microcode(struct amdgpu_umsch_mm *umsch)
{
struct amdgpu_device *adev = umsch->ring.adev;
@ -50,6 +60,14 @@ static int umsch_mm_v4_0_load_microcode(struct amdgpu_umsch_mm *umsch)
umsch->cmd_buf_curr_ptr = umsch->cmd_buf_ptr;
if (amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(4, 0, 5)) {
WREG32_SOC15(VCN, 0, regUVD_IPX_DLDO_CONFIG,
1 << UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG__SHIFT);
SOC15_WAIT_ON_RREG(VCN, 0, regUVD_IPX_DLDO_STATUS,
0 << UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS__SHIFT,
UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS_MASK);
}
data = RREG32_SOC15(VCN, 0, regUMSCH_MES_RESET_CTRL);
data = REG_SET_FIELD(data, UMSCH_MES_RESET_CTRL, MES_CORE_SOFT_RESET, 0);
WREG32_SOC15_UMSCH(regUMSCH_MES_RESET_CTRL, data);
@ -229,6 +247,14 @@ static int umsch_mm_v4_0_ring_stop(struct amdgpu_umsch_mm *umsch)
data = REG_SET_FIELD(data, VCN_UMSCH_RB_DB_CTRL, EN, 0);
WREG32_SOC15(VCN, 0, regVCN_UMSCH_RB_DB_CTRL, data);
if (amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(4, 0, 5)) {
WREG32_SOC15(VCN, 0, regUVD_IPX_DLDO_CONFIG,
2 << UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG__SHIFT);
SOC15_WAIT_ON_RREG(VCN, 0, regUVD_IPX_DLDO_STATUS,
1 << UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS__SHIFT,
UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS_MASK);
}
return 0;
}