iv/linux
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge branch 'drm-fixes-3.8' of git://people.freedesktop.org/~agd5f/linux into drm-next

Browse Source 
Alex writes:
Just some small misc fixes.

* 'drm-fixes-3.8' of git://people.freedesktop.org/~agd5f/linux:
  drm/radeon: Enable DMA_IB_SWAP_ENABLE on big endian hosts.
  drm/radeon: fix a rare case of double kfree
  radeon_display: Use pointer return error codes
  drm/radeon: fix cursor corruption on DCE6 and newer
This commit is contained in:
Dave Airlie 2013-01-25 14:18:32 +10:00
commit 4af6924b8a
5 changed files with 17 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/gpu/drm/radeon/ni.c
View File

@ -1216,7 +1216,7 @@ void cayman_dma_stop(struct radeon_device *rdev)
int cayman_dma_resume(struct radeon_device *rdev) int cayman_dma_resume(struct radeon_device *rdev)
{ {
struct radeon_ring *ring; struct radeon_ring *ring;
u32 rb_cntl, dma_cntl; u32 rb_cntl, dma_cntl, ib_cntl;
u32 rb_bufsz; u32 rb_bufsz;
u32 reg_offset, wb_offset; u32 reg_offset, wb_offset;
int i, r; int i, r;
@ -1265,7 +1265,11 @@ int cayman_dma_resume(struct radeon_device *rdev)
WREG32(DMA_RB_BASE + reg_offset, ring->gpu_addr >> 8); WREG32(DMA_RB_BASE + reg_offset, ring->gpu_addr >> 8);
/* enable DMA IBs */ /* enable DMA IBs */
WREG32(DMA_IB_CNTL + reg_offset, DMA_IB_ENABLE | CMD_VMID_FORCE); ib_cntl = DMA_IB_ENABLE | CMD_VMID_FORCE;
#ifdef __BIG_ENDIAN
ib_cntl |= DMA_IB_SWAP_ENABLE;
#endif
WREG32(DMA_IB_CNTL + reg_offset, ib_cntl);
dma_cntl = RREG32(DMA_CNTL + reg_offset); dma_cntl = RREG32(DMA_CNTL + reg_offset);
dma_cntl &= ~CTXEMPTY_INT_ENABLE; dma_cntl &= ~CTXEMPTY_INT_ENABLE;

8
drivers/gpu/drm/radeon/r600.c
View File

@ -2313,7 +2313,7 @@ void r600_dma_stop(struct radeon_device *rdev)
int r600_dma_resume(struct radeon_device *rdev) int r600_dma_resume(struct radeon_device *rdev)
{ {
struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
u32 rb_cntl, dma_cntl; u32 rb_cntl, dma_cntl, ib_cntl;
u32 rb_bufsz; u32 rb_bufsz;
int r; int r;
@ -2353,7 +2353,11 @@ int r600_dma_resume(struct radeon_device *rdev)
WREG32(DMA_RB_BASE, ring->gpu_addr >> 8); WREG32(DMA_RB_BASE, ring->gpu_addr >> 8);
/* enable DMA IBs */ /* enable DMA IBs */
WREG32(DMA_IB_CNTL, DMA_IB_ENABLE); ib_cntl = DMA_IB_ENABLE;
#ifdef __BIG_ENDIAN
ib_cntl |= DMA_IB_SWAP_ENABLE;
#endif
WREG32(DMA_IB_CNTL, ib_cntl);
dma_cntl = RREG32(DMA_CNTL); dma_cntl = RREG32(DMA_CNTL);
dma_cntl &= ~CTXEMPTY_INT_ENABLE; dma_cntl &= ~CTXEMPTY_INT_ENABLE;

2
drivers/gpu/drm/radeon/radeon_cs.c
View File

@ -286,6 +286,8 @@ int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
p->chunks[p->chunk_ib_idx].kpage[1] == NULL) { p->chunks[p->chunk_ib_idx].kpage[1] == NULL) {
kfree(p->chunks[p->chunk_ib_idx].kpage[0]); kfree(p->chunks[p->chunk_ib_idx].kpage[0]);
kfree(p->chunks[p->chunk_ib_idx].kpage[1]); kfree(p->chunks[p->chunk_ib_idx].kpage[1]);
p->chunks[p->chunk_ib_idx].kpage[0] = NULL;
p->chunks[p->chunk_ib_idx].kpage[1] = NULL;
return -ENOMEM; return -ENOMEM;
} }
} }

3
drivers/gpu/drm/radeon/radeon_cursor.c
View File

@ -241,7 +241,8 @@ int radeon_crtc_cursor_move(struct drm_crtc *crtc,
y = 0; y = 0;
} }
if (ASIC_IS_AVIVO(rdev)) { /* fixed on DCE6 and newer */
if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE6(rdev)) {
int i = 0; int i = 0;
struct drm_crtc *crtc_p; struct drm_crtc *crtc_p;

2
drivers/gpu/drm/radeon/radeon_display.c
View File

@ -1122,7 +1122,7 @@ radeon_user_framebuffer_create(struct drm_device *dev,
if (ret) { if (ret) {
kfree(radeon_fb); kfree(radeon_fb);
drm_gem_object_unreference_unlocked(obj); drm_gem_object_unreference_unlocked(obj);
return NULL; return ERR_PTR(ret);
} }
return &radeon_fb->base; return &radeon_fb->base;