drm/amdgpu/gfx10: convert to IP version checking
Use IP versions rather than asic_type to differentiate IP version specific features. v2: rebase, squash in navi10 fixes (Alex) Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
parent
8f4bb1e784
commit
4b0ad84254
@ -1537,7 +1537,7 @@ static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32
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scratch_reg3 = adev->rmmio +
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(adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3) * 4;
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if (adev->asic_type >= CHIP_SIENNA_CICHLID) {
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if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0)) {
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spare_int = adev->rmmio +
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(adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX]
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+ mmRLC_SPARE_INT_0_Sienna_Cichlid) * 4;
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@ -3727,18 +3727,18 @@ static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
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static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
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{
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switch (adev->asic_type) {
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case CHIP_NAVI10:
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switch (adev->ip_versions[GC_HWIP]) {
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case IP_VERSION(10, 1, 10):
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soc15_program_register_sequence(adev,
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golden_settings_gc_rlc_spm_10_0_nv10,
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(const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
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break;
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case CHIP_NAVI14:
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case IP_VERSION(10, 1, 1):
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soc15_program_register_sequence(adev,
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golden_settings_gc_rlc_spm_10_1_nv14,
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(const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
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break;
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case CHIP_NAVI12:
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case IP_VERSION(10, 1, 2):
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soc15_program_register_sequence(adev,
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golden_settings_gc_rlc_spm_10_1_2_nv12,
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(const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
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@ -3750,8 +3750,8 @@ static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
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static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
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{
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switch (adev->asic_type) {
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case CHIP_NAVI10:
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switch (adev->ip_versions[GC_HWIP]) {
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case IP_VERSION(10, 1, 10):
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soc15_program_register_sequence(adev,
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golden_settings_gc_10_1,
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(const u32)ARRAY_SIZE(golden_settings_gc_10_1));
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@ -3759,7 +3759,7 @@ static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
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golden_settings_gc_10_0_nv10,
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(const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
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break;
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case CHIP_NAVI14:
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case IP_VERSION(10, 1, 1):
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soc15_program_register_sequence(adev,
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golden_settings_gc_10_1_1,
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(const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
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@ -3767,7 +3767,7 @@ static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
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golden_settings_gc_10_1_nv14,
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(const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
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break;
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case CHIP_NAVI12:
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case IP_VERSION(10, 1, 2):
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soc15_program_register_sequence(adev,
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golden_settings_gc_10_1_2,
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(const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
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@ -3775,7 +3775,7 @@ static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
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golden_settings_gc_10_1_2_nv12,
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(const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
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break;
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case CHIP_SIENNA_CICHLID:
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case IP_VERSION(10, 3, 0):
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soc15_program_register_sequence(adev,
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golden_settings_gc_10_3,
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(const u32)ARRAY_SIZE(golden_settings_gc_10_3));
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@ -3783,32 +3783,32 @@ static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
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golden_settings_gc_10_3_sienna_cichlid,
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(const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));
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break;
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case CHIP_NAVY_FLOUNDER:
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case IP_VERSION(10, 3, 2):
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soc15_program_register_sequence(adev,
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golden_settings_gc_10_3_2,
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(const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
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break;
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case CHIP_VANGOGH:
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case IP_VERSION(10, 3, 1):
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soc15_program_register_sequence(adev,
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golden_settings_gc_10_3_vangogh,
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(const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh));
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break;
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case CHIP_YELLOW_CARP:
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case IP_VERSION(10, 3, 3):
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soc15_program_register_sequence(adev,
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golden_settings_gc_10_3_3,
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(const u32)ARRAY_SIZE(golden_settings_gc_10_3_3));
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break;
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case CHIP_DIMGREY_CAVEFISH:
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case IP_VERSION(10, 3, 4):
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soc15_program_register_sequence(adev,
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golden_settings_gc_10_3_4,
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(const u32)ARRAY_SIZE(golden_settings_gc_10_3_4));
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break;
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case CHIP_BEIGE_GOBY:
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case IP_VERSION(10, 3, 5):
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soc15_program_register_sequence(adev,
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golden_settings_gc_10_3_5,
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(const u32)ARRAY_SIZE(golden_settings_gc_10_3_5));
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break;
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case CHIP_CYAN_SKILLFISH:
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case IP_VERSION(10, 1, 3):
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soc15_program_register_sequence(adev,
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golden_settings_gc_10_0,
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(const u32)ARRAY_SIZE(golden_settings_gc_10_0));
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@ -3985,11 +3985,11 @@ static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
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{
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adev->gfx.cp_fw_write_wait = false;
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switch (adev->asic_type) {
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case CHIP_NAVI10:
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case CHIP_NAVI12:
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case CHIP_NAVI14:
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case CHIP_CYAN_SKILLFISH:
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switch (adev->ip_versions[GC_HWIP]) {
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case IP_VERSION(10, 1, 10):
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case IP_VERSION(10, 1, 2):
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case IP_VERSION(10, 1, 1):
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case IP_VERSION(10, 1, 3):
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if ((adev->gfx.me_fw_version >= 0x00000046) &&
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(adev->gfx.me_feature_version >= 27) &&
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(adev->gfx.pfp_fw_version >= 0x00000068) &&
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@ -3998,12 +3998,12 @@ static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
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(adev->gfx.mec_feature_version >= 27))
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adev->gfx.cp_fw_write_wait = true;
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break;
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case CHIP_SIENNA_CICHLID:
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case CHIP_NAVY_FLOUNDER:
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case CHIP_VANGOGH:
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case CHIP_DIMGREY_CAVEFISH:
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case CHIP_BEIGE_GOBY:
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case CHIP_YELLOW_CARP:
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case IP_VERSION(10, 3, 0):
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case IP_VERSION(10, 3, 2):
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case IP_VERSION(10, 3, 1):
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case IP_VERSION(10, 3, 4):
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case IP_VERSION(10, 3, 5):
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case IP_VERSION(10, 3, 3):
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adev->gfx.cp_fw_write_wait = true;
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break;
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default:
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@ -4066,8 +4066,8 @@ static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
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static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
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{
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switch (adev->asic_type) {
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case CHIP_NAVI10:
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switch (adev->ip_versions[GC_HWIP]) {
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case IP_VERSION(10, 1, 10):
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if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
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adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
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break;
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@ -4093,38 +4093,38 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
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DRM_DEBUG("\n");
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switch (adev->asic_type) {
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case CHIP_NAVI10:
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switch (adev->ip_versions[GC_HWIP]) {
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case IP_VERSION(10, 1, 10):
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chip_name = "navi10";
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break;
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case CHIP_NAVI14:
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case IP_VERSION(10, 1, 1):
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chip_name = "navi14";
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if (!(adev->pdev->device == 0x7340 &&
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adev->pdev->revision != 0x00))
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wks = "_wks";
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break;
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case CHIP_NAVI12:
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case IP_VERSION(10, 1, 2):
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chip_name = "navi12";
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break;
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case CHIP_SIENNA_CICHLID:
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case IP_VERSION(10, 3, 0):
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chip_name = "sienna_cichlid";
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break;
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case CHIP_NAVY_FLOUNDER:
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case IP_VERSION(10, 3, 2):
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chip_name = "navy_flounder";
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break;
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case CHIP_VANGOGH:
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case IP_VERSION(10, 3, 1):
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chip_name = "vangogh";
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break;
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case CHIP_DIMGREY_CAVEFISH:
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case IP_VERSION(10, 3, 4):
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chip_name = "dimgrey_cavefish";
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break;
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case CHIP_BEIGE_GOBY:
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case IP_VERSION(10, 3, 5):
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chip_name = "beige_goby";
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break;
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case CHIP_YELLOW_CARP:
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case IP_VERSION(10, 3, 3):
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chip_name = "yellow_carp";
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break;
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case CHIP_CYAN_SKILLFISH:
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case IP_VERSION(10, 1, 3):
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if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2)
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chip_name = "cyan_skillfish2";
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else
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@ -4684,10 +4684,10 @@ static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
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adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
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switch (adev->asic_type) {
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case CHIP_NAVI10:
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case CHIP_NAVI14:
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case CHIP_NAVI12:
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switch (adev->ip_versions[GC_HWIP]) {
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case IP_VERSION(10, 1, 10):
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case IP_VERSION(10, 1, 1):
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case IP_VERSION(10, 1, 2):
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adev->gfx.config.max_hw_contexts = 8;
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adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
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adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
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@ -4695,12 +4695,12 @@ static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
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adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
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gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
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break;
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case CHIP_SIENNA_CICHLID:
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case CHIP_NAVY_FLOUNDER:
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case CHIP_VANGOGH:
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case CHIP_DIMGREY_CAVEFISH:
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case CHIP_BEIGE_GOBY:
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case CHIP_YELLOW_CARP:
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case IP_VERSION(10, 3, 0):
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case IP_VERSION(10, 3, 2):
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case IP_VERSION(10, 3, 1):
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case IP_VERSION(10, 3, 4):
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case IP_VERSION(10, 3, 5):
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case IP_VERSION(10, 3, 3):
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adev->gfx.config.max_hw_contexts = 8;
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adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
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adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
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@ -4710,7 +4710,7 @@ static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
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adev->gfx.config.gb_addr_config_fields.num_pkrs =
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1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
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break;
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case CHIP_CYAN_SKILLFISH:
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case IP_VERSION(10, 1, 3):
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adev->gfx.config.max_hw_contexts = 8;
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adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
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adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
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@ -4818,11 +4818,11 @@ static int gfx_v10_0_sw_init(void *handle)
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struct amdgpu_kiq *kiq;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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switch (adev->asic_type) {
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case CHIP_NAVI10:
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case CHIP_NAVI14:
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case CHIP_NAVI12:
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case CHIP_CYAN_SKILLFISH:
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switch (adev->ip_versions[GC_HWIP]) {
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case IP_VERSION(10, 1, 10):
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case IP_VERSION(10, 1, 1):
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case IP_VERSION(10, 1, 2):
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case IP_VERSION(10, 1, 3):
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adev->gfx.me.num_me = 1;
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adev->gfx.me.num_pipe_per_me = 1;
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adev->gfx.me.num_queue_per_pipe = 1;
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@ -4830,12 +4830,12 @@ static int gfx_v10_0_sw_init(void *handle)
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adev->gfx.mec.num_pipe_per_mec = 4;
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adev->gfx.mec.num_queue_per_pipe = 8;
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break;
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case CHIP_SIENNA_CICHLID:
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case CHIP_NAVY_FLOUNDER:
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case CHIP_VANGOGH:
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case CHIP_DIMGREY_CAVEFISH:
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case CHIP_BEIGE_GOBY:
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case CHIP_YELLOW_CARP:
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case IP_VERSION(10, 3, 0):
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case IP_VERSION(10, 3, 2):
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case IP_VERSION(10, 3, 1):
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case IP_VERSION(10, 3, 4):
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case IP_VERSION(10, 3, 5):
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case IP_VERSION(10, 3, 3):
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adev->gfx.me.num_me = 1;
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adev->gfx.me.num_pipe_per_me = 1;
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adev->gfx.me.num_queue_per_pipe = 1;
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@ -5068,8 +5068,8 @@ static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
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for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
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for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
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bitmap = i * adev->gfx.config.max_sh_per_se + j;
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if (((adev->asic_type == CHIP_SIENNA_CICHLID) ||
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(adev->asic_type == CHIP_YELLOW_CARP)) &&
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if (((adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 0)) ||
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(adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 3))) &&
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((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
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continue;
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gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
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@ -5096,7 +5096,7 @@ static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *ade
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/* for ASICs that integrates GFX v10.3
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* pa_sc_tile_steering_override should be set to 0 */
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if (adev->asic_type >= CHIP_SIENNA_CICHLID)
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if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0))
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return 0;
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/* init num_sc */
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@ -5249,7 +5249,7 @@ static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
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/* TCCs are global (not instanced). */
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uint32_t tcc_disable;
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if (adev->asic_type >= CHIP_SIENNA_CICHLID) {
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if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0)) {
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tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) |
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RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3);
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} else {
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@ -5326,7 +5326,7 @@ static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
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adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
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/* csib */
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if (adev->asic_type == CHIP_NAVI12) {
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if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 1, 2)) {
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WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
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adev->gfx.rlc.clear_state_gpu_addr >> 32);
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WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
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@ -5948,7 +5948,7 @@ static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
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tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
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tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
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if (adev->asic_type == CHIP_NAVI12) {
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if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 1, 2)) {
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WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
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} else {
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WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
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@ -6337,13 +6337,13 @@ static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
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}
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WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
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}
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switch (adev->asic_type) {
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case CHIP_SIENNA_CICHLID:
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case CHIP_NAVY_FLOUNDER:
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case CHIP_VANGOGH:
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case CHIP_DIMGREY_CAVEFISH:
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case CHIP_BEIGE_GOBY:
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case CHIP_YELLOW_CARP:
|
||||
switch (adev->ip_versions[GC_HWIP]) {
|
||||
case IP_VERSION(10, 3, 0):
|
||||
case IP_VERSION(10, 3, 2):
|
||||
case IP_VERSION(10, 3, 1):
|
||||
case IP_VERSION(10, 3, 4):
|
||||
case IP_VERSION(10, 3, 5):
|
||||
case IP_VERSION(10, 3, 3):
|
||||
tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
|
||||
DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
|
||||
WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
|
||||
@ -6474,13 +6474,13 @@ static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
|
||||
static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
|
||||
{
|
||||
if (enable) {
|
||||
switch (adev->asic_type) {
|
||||
case CHIP_SIENNA_CICHLID:
|
||||
case CHIP_NAVY_FLOUNDER:
|
||||
case CHIP_VANGOGH:
|
||||
case CHIP_DIMGREY_CAVEFISH:
|
||||
case CHIP_BEIGE_GOBY:
|
||||
case CHIP_YELLOW_CARP:
|
||||
switch (adev->ip_versions[GC_HWIP]) {
|
||||
case IP_VERSION(10, 3, 0):
|
||||
case IP_VERSION(10, 3, 2):
|
||||
case IP_VERSION(10, 3, 1):
|
||||
case IP_VERSION(10, 3, 4):
|
||||
case IP_VERSION(10, 3, 5):
|
||||
case IP_VERSION(10, 3, 3):
|
||||
WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
|
||||
break;
|
||||
default:
|
||||
@ -6488,13 +6488,13 @@ static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
switch (adev->asic_type) {
|
||||
case CHIP_SIENNA_CICHLID:
|
||||
case CHIP_NAVY_FLOUNDER:
|
||||
case CHIP_VANGOGH:
|
||||
case CHIP_DIMGREY_CAVEFISH:
|
||||
case CHIP_BEIGE_GOBY:
|
||||
case CHIP_YELLOW_CARP:
|
||||
switch (adev->ip_versions[GC_HWIP]) {
|
||||
case IP_VERSION(10, 3, 0):
|
||||
case IP_VERSION(10, 3, 2):
|
||||
case IP_VERSION(10, 3, 1):
|
||||
case IP_VERSION(10, 3, 4):
|
||||
case IP_VERSION(10, 3, 5):
|
||||
case IP_VERSION(10, 3, 3):
|
||||
WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
|
||||
(CP_MEC_CNTL__MEC_ME1_HALT_MASK |
|
||||
CP_MEC_CNTL__MEC_ME2_HALT_MASK));
|
||||
@ -6586,13 +6586,13 @@ static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
|
||||
struct amdgpu_device *adev = ring->adev;
|
||||
|
||||
/* tell RLC which is KIQ queue */
|
||||
switch (adev->asic_type) {
|
||||
case CHIP_SIENNA_CICHLID:
|
||||
case CHIP_NAVY_FLOUNDER:
|
||||
case CHIP_VANGOGH:
|
||||
case CHIP_DIMGREY_CAVEFISH:
|
||||
case CHIP_BEIGE_GOBY:
|
||||
case CHIP_YELLOW_CARP:
|
||||
switch (adev->ip_versions[GC_HWIP]) {
|
||||
case IP_VERSION(10, 3, 0):
|
||||
case IP_VERSION(10, 3, 2):
|
||||
case IP_VERSION(10, 3, 1):
|
||||
case IP_VERSION(10, 3, 4):
|
||||
case IP_VERSION(10, 3, 5):
|
||||
case IP_VERSION(10, 3, 3):
|
||||
tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
|
||||
tmp &= 0xffffff00;
|
||||
tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
|
||||
@ -7303,11 +7303,11 @@ static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
|
||||
|
||||
/* check if mmVGT_ESGS_RING_SIZE_UMD
|
||||
* has been remapped to mmVGT_ESGS_RING_SIZE */
|
||||
switch (adev->asic_type) {
|
||||
case CHIP_SIENNA_CICHLID:
|
||||
case CHIP_NAVY_FLOUNDER:
|
||||
case CHIP_DIMGREY_CAVEFISH:
|
||||
case CHIP_BEIGE_GOBY:
|
||||
switch (adev->ip_versions[GC_HWIP]) {
|
||||
case IP_VERSION(10, 3, 0):
|
||||
case IP_VERSION(10, 3, 2):
|
||||
case IP_VERSION(10, 3, 4):
|
||||
case IP_VERSION(10, 3, 5):
|
||||
data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
|
||||
WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
|
||||
WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
|
||||
@ -7320,8 +7320,8 @@ static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case CHIP_VANGOGH:
|
||||
case CHIP_YELLOW_CARP:
|
||||
case IP_VERSION(10, 3, 1):
|
||||
case IP_VERSION(10, 3, 3):
|
||||
return true;
|
||||
default:
|
||||
data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
|
||||
@ -7350,13 +7350,13 @@ static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
|
||||
* index will auto-inc after each data writting */
|
||||
WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
|
||||
|
||||
switch (adev->asic_type) {
|
||||
case CHIP_SIENNA_CICHLID:
|
||||
case CHIP_NAVY_FLOUNDER:
|
||||
case CHIP_VANGOGH:
|
||||
case CHIP_DIMGREY_CAVEFISH:
|
||||
case CHIP_BEIGE_GOBY:
|
||||
case CHIP_YELLOW_CARP:
|
||||
switch (adev->ip_versions[GC_HWIP]) {
|
||||
case IP_VERSION(10, 3, 0):
|
||||
case IP_VERSION(10, 3, 2):
|
||||
case IP_VERSION(10, 3, 1):
|
||||
case IP_VERSION(10, 3, 4):
|
||||
case IP_VERSION(10, 3, 5):
|
||||
case IP_VERSION(10, 3, 3):
|
||||
/* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
|
||||
data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
|
||||
GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
|
||||
@ -7520,19 +7520,19 @@ static int gfx_v10_0_hw_init(void *handle)
|
||||
* init golden registers and rlc resume may override some registers,
|
||||
* reconfig them here
|
||||
*/
|
||||
if (adev->asic_type == CHIP_NAVI10 ||
|
||||
adev->asic_type == CHIP_NAVI14 ||
|
||||
adev->asic_type == CHIP_NAVI12)
|
||||
if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 1, 10) ||
|
||||
adev->ip_versions[GC_HWIP] == IP_VERSION(10, 1, 1) ||
|
||||
adev->ip_versions[GC_HWIP] == IP_VERSION(10, 1, 2))
|
||||
gfx_v10_0_tcp_harvest(adev);
|
||||
|
||||
r = gfx_v10_0_cp_resume(adev);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
if (adev->asic_type == CHIP_SIENNA_CICHLID)
|
||||
if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 0))
|
||||
gfx_v10_3_program_pbb_mode(adev);
|
||||
|
||||
if (adev->asic_type >= CHIP_SIENNA_CICHLID)
|
||||
if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0))
|
||||
gfx_v10_3_set_power_brake_sequence(adev);
|
||||
|
||||
return r;
|
||||
@ -7584,7 +7584,7 @@ static int gfx_v10_0_hw_fini(void *handle)
|
||||
if (amdgpu_sriov_vf(adev)) {
|
||||
gfx_v10_0_cp_gfx_enable(adev, false);
|
||||
/* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
|
||||
if (adev->asic_type >= CHIP_SIENNA_CICHLID) {
|
||||
if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0)) {
|
||||
tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
|
||||
tmp &= 0xffffff00;
|
||||
WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
|
||||
@ -7670,13 +7670,13 @@ static int gfx_v10_0_soft_reset(void *handle)
|
||||
|
||||
/* GRBM_STATUS2 */
|
||||
tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
|
||||
switch (adev->asic_type) {
|
||||
case CHIP_SIENNA_CICHLID:
|
||||
case CHIP_NAVY_FLOUNDER:
|
||||
case CHIP_VANGOGH:
|
||||
case CHIP_DIMGREY_CAVEFISH:
|
||||
case CHIP_BEIGE_GOBY:
|
||||
case CHIP_YELLOW_CARP:
|
||||
switch (adev->ip_versions[GC_HWIP]) {
|
||||
case IP_VERSION(10, 3, 0):
|
||||
case IP_VERSION(10, 3, 2):
|
||||
case IP_VERSION(10, 3, 1):
|
||||
case IP_VERSION(10, 3, 4):
|
||||
case IP_VERSION(10, 3, 5):
|
||||
case IP_VERSION(10, 3, 3):
|
||||
if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
|
||||
grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
|
||||
GRBM_SOFT_RESET,
|
||||
@ -7726,9 +7726,9 @@ static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
|
||||
{
|
||||
uint64_t clock, clock_lo, clock_hi, hi_check;
|
||||
|
||||
switch (adev->asic_type) {
|
||||
case CHIP_VANGOGH:
|
||||
case CHIP_YELLOW_CARP:
|
||||
switch (adev->ip_versions[GC_HWIP]) {
|
||||
case IP_VERSION(10, 3, 1):
|
||||
case IP_VERSION(10, 3, 3):
|
||||
clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh) |
|
||||
((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh) << 32ULL);
|
||||
break;
|
||||
@ -7784,19 +7784,19 @@ static int gfx_v10_0_early_init(void *handle)
|
||||
{
|
||||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||
|
||||
switch (adev->asic_type) {
|
||||
case CHIP_NAVI10:
|
||||
case CHIP_NAVI14:
|
||||
case CHIP_NAVI12:
|
||||
case CHIP_CYAN_SKILLFISH:
|
||||
switch (adev->ip_versions[GC_HWIP]) {
|
||||
case IP_VERSION(10, 1, 10):
|
||||
case IP_VERSION(10, 1, 1):
|
||||
case IP_VERSION(10, 1, 2):
|
||||
case IP_VERSION(10, 1, 3):
|
||||
adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
|
||||
break;
|
||||
case CHIP_SIENNA_CICHLID:
|
||||
case CHIP_NAVY_FLOUNDER:
|
||||
case CHIP_VANGOGH:
|
||||
case CHIP_DIMGREY_CAVEFISH:
|
||||
case CHIP_BEIGE_GOBY:
|
||||
case CHIP_YELLOW_CARP:
|
||||
case IP_VERSION(10, 3, 0):
|
||||
case IP_VERSION(10, 3, 2):
|
||||
case IP_VERSION(10, 3, 1):
|
||||
case IP_VERSION(10, 3, 4):
|
||||
case IP_VERSION(10, 3, 5):
|
||||
case IP_VERSION(10, 3, 3):
|
||||
adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
|
||||
break;
|
||||
default:
|
||||
@ -7848,13 +7848,13 @@ static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
|
||||
data = RLC_SAFE_MODE__CMD_MASK;
|
||||
data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
|
||||
|
||||
switch (adev->asic_type) {
|
||||
case CHIP_SIENNA_CICHLID:
|
||||
case CHIP_NAVY_FLOUNDER:
|
||||
case CHIP_VANGOGH:
|
||||
case CHIP_DIMGREY_CAVEFISH:
|
||||
case CHIP_BEIGE_GOBY:
|
||||
case CHIP_YELLOW_CARP:
|
||||
switch (adev->ip_versions[GC_HWIP]) {
|
||||
case IP_VERSION(10, 3, 0):
|
||||
case IP_VERSION(10, 3, 2):
|
||||
case IP_VERSION(10, 3, 1):
|
||||
case IP_VERSION(10, 3, 4):
|
||||
case IP_VERSION(10, 3, 5):
|
||||
case IP_VERSION(10, 3, 3):
|
||||
WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
|
||||
|
||||
/* wait for RLC_SAFE_MODE */
|
||||
@ -7884,13 +7884,13 @@ static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
|
||||
uint32_t data;
|
||||
|
||||
data = RLC_SAFE_MODE__CMD_MASK;
|
||||
switch (adev->asic_type) {
|
||||
case CHIP_SIENNA_CICHLID:
|
||||
case CHIP_NAVY_FLOUNDER:
|
||||
case CHIP_VANGOGH:
|
||||
case CHIP_DIMGREY_CAVEFISH:
|
||||
case CHIP_BEIGE_GOBY:
|
||||
case CHIP_YELLOW_CARP:
|
||||
switch (adev->ip_versions[GC_HWIP]) {
|
||||
case IP_VERSION(10, 3, 0):
|
||||
case IP_VERSION(10, 3, 2):
|
||||
case IP_VERSION(10, 3, 1):
|
||||
case IP_VERSION(10, 3, 4):
|
||||
case IP_VERSION(10, 3, 5):
|
||||
case IP_VERSION(10, 3, 3):
|
||||
WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
|
||||
break;
|
||||
default:
|
||||
@ -8193,7 +8193,7 @@ static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_d
|
||||
mmCGTS_SA1_QUAD1_SM_CTRL_REG
|
||||
};
|
||||
|
||||
if (adev->asic_type == CHIP_NAVI12) {
|
||||
if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 1, 2)) {
|
||||
for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) {
|
||||
reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
|
||||
tcp_ctrl_regs_nv12[i];
|
||||
@ -8238,8 +8238,8 @@ static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
|
||||
/* === CGCG + CGLS === */
|
||||
gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
|
||||
|
||||
if ((adev->asic_type >= CHIP_NAVI10) &&
|
||||
(adev->asic_type <= CHIP_NAVI12))
|
||||
if ((adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 1, 10)) &&
|
||||
(adev->ip_versions[GC_HWIP] <= IP_VERSION(10, 1, 2)))
|
||||
gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev);
|
||||
} else {
|
||||
/* CGCG/CGLS should be disabled before MGCG/MGLS
|
||||
@ -8335,12 +8335,12 @@ static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
|
||||
* Power/performance team will optimize it and might give a new value later.
|
||||
*/
|
||||
if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
|
||||
switch (adev->asic_type) {
|
||||
case CHIP_VANGOGH:
|
||||
switch (adev->ip_versions[GC_HWIP]) {
|
||||
case IP_VERSION(10, 3, 1):
|
||||
data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
|
||||
WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
|
||||
break;
|
||||
case CHIP_YELLOW_CARP:
|
||||
case IP_VERSION(10, 3, 3):
|
||||
data = 0x1388 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
|
||||
WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
|
||||
break;
|
||||
@ -8399,18 +8399,18 @@ static int gfx_v10_0_set_powergating_state(void *handle,
|
||||
if (amdgpu_sriov_vf(adev))
|
||||
return 0;
|
||||
|
||||
switch (adev->asic_type) {
|
||||
case CHIP_NAVI10:
|
||||
case CHIP_NAVI14:
|
||||
case CHIP_NAVI12:
|
||||
case CHIP_SIENNA_CICHLID:
|
||||
case CHIP_NAVY_FLOUNDER:
|
||||
case CHIP_DIMGREY_CAVEFISH:
|
||||
case CHIP_BEIGE_GOBY:
|
||||
switch (adev->ip_versions[GC_HWIP]) {
|
||||
case IP_VERSION(10, 1, 10):
|
||||
case IP_VERSION(10, 1, 1):
|
||||
case IP_VERSION(10, 1, 2):
|
||||
case IP_VERSION(10, 3, 0):
|
||||
case IP_VERSION(10, 3, 2):
|
||||
case IP_VERSION(10, 3, 4):
|
||||
case IP_VERSION(10, 3, 5):
|
||||
amdgpu_gfx_off_ctrl(adev, enable);
|
||||
break;
|
||||
case CHIP_VANGOGH:
|
||||
case CHIP_YELLOW_CARP:
|
||||
case IP_VERSION(10, 3, 1):
|
||||
case IP_VERSION(10, 3, 3):
|
||||
gfx_v10_cntl_pg(adev, enable);
|
||||
amdgpu_gfx_off_ctrl(adev, enable);
|
||||
break;
|
||||
@ -8428,16 +8428,16 @@ static int gfx_v10_0_set_clockgating_state(void *handle,
|
||||
if (amdgpu_sriov_vf(adev))
|
||||
return 0;
|
||||
|
||||
switch (adev->asic_type) {
|
||||
case CHIP_NAVI10:
|
||||
case CHIP_NAVI14:
|
||||
case CHIP_NAVI12:
|
||||
case CHIP_SIENNA_CICHLID:
|
||||
case CHIP_NAVY_FLOUNDER:
|
||||
case CHIP_VANGOGH:
|
||||
case CHIP_DIMGREY_CAVEFISH:
|
||||
case CHIP_BEIGE_GOBY:
|
||||
case CHIP_YELLOW_CARP:
|
||||
switch (adev->ip_versions[GC_HWIP]) {
|
||||
case IP_VERSION(10, 1, 10):
|
||||
case IP_VERSION(10, 1, 1):
|
||||
case IP_VERSION(10, 1, 2):
|
||||
case IP_VERSION(10, 3, 0):
|
||||
case IP_VERSION(10, 3, 2):
|
||||
case IP_VERSION(10, 3, 1):
|
||||
case IP_VERSION(10, 3, 4):
|
||||
case IP_VERSION(10, 3, 5):
|
||||
case IP_VERSION(10, 3, 3):
|
||||
gfx_v10_0_update_gfx_clock_gating(adev,
|
||||
state == AMD_CG_STATE_GATE);
|
||||
break;
|
||||
@ -9541,19 +9541,19 @@ static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
|
||||
|
||||
static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
|
||||
{
|
||||
switch (adev->asic_type) {
|
||||
case CHIP_NAVI10:
|
||||
case CHIP_NAVI14:
|
||||
case CHIP_NAVY_FLOUNDER:
|
||||
case CHIP_VANGOGH:
|
||||
case CHIP_DIMGREY_CAVEFISH:
|
||||
case CHIP_BEIGE_GOBY:
|
||||
case CHIP_YELLOW_CARP:
|
||||
case CHIP_CYAN_SKILLFISH:
|
||||
switch (adev->ip_versions[GC_HWIP]) {
|
||||
case IP_VERSION(10, 1, 10):
|
||||
case IP_VERSION(10, 1, 1):
|
||||
case IP_VERSION(10, 1, 3):
|
||||
case IP_VERSION(10, 3, 2):
|
||||
case IP_VERSION(10, 3, 1):
|
||||
case IP_VERSION(10, 3, 4):
|
||||
case IP_VERSION(10, 3, 5):
|
||||
case IP_VERSION(10, 3, 3):
|
||||
adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
|
||||
break;
|
||||
case CHIP_NAVI12:
|
||||
case CHIP_SIENNA_CICHLID:
|
||||
case IP_VERSION(10, 1, 2):
|
||||
case IP_VERSION(10, 3, 0):
|
||||
adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
|
||||
break;
|
||||
default:
|
||||
@ -9641,8 +9641,8 @@ static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
|
||||
for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
|
||||
for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
|
||||
bitmap = i * adev->gfx.config.max_sh_per_se + j;
|
||||
if (((adev->asic_type == CHIP_SIENNA_CICHLID) ||
|
||||
(adev->asic_type == CHIP_YELLOW_CARP)) &&
|
||||
if (((adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 0)) ||
|
||||
(adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 3))) &&
|
||||
((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
|
||||
continue;
|
||||
mask = 1;
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user