KVM: x86: Add Corrected Machine Check Interrupt (CMCI) emulation to lapic.
This patch calculates the number of lvt entries as part of KVM_X86_MCE_SETUP conditioned on the presence of MCG_CMCI_P bit in MCG_CAP and stores result in kvm_lapic. It translats from APIC_LVTx register to index in lapic_lvt_entry enum. It extends the APIC_LVTx macro as well as other lapic write/reset handling etc to support Corrected Machine Check Interrupt. Signed-off-by: Jue Wang <juew@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20220610171134.772566-5-juew@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -27,6 +27,7 @@
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#include <linux/math64.h>
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#include <linux/slab.h>
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#include <asm/processor.h>
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#include <asm/mce.h>
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#include <asm/msr.h>
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#include <asm/page.h>
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#include <asm/current.h>
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@ -399,14 +400,21 @@ static inline int apic_lvt_nmi_mode(u32 lvt_val)
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return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
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}
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static inline bool kvm_lapic_lvt_supported(struct kvm_lapic *apic, int lvt_index)
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{
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return apic->nr_lvt_entries > lvt_index;
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}
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void kvm_apic_set_version(struct kvm_vcpu *vcpu)
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{
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struct kvm_lapic *apic = vcpu->arch.apic;
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u32 v = APIC_VERSION | ((KVM_APIC_MAX_NR_LVT_ENTRIES - 1) << 16);
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u32 v = 0;
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if (!lapic_in_kernel(vcpu))
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return;
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v = APIC_VERSION | ((apic->nr_lvt_entries - 1) << 16);
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/*
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* KVM emulates 82093AA datasheet (with in-kernel IOAPIC implementation)
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* which doesn't have EOI register; Some buggy OSes (e.g. Windows with
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@ -426,7 +434,8 @@ static const unsigned int apic_lvt_mask[KVM_APIC_MAX_NR_LVT_ENTRIES] = {
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[LVT_PERFORMANCE_COUNTER] = LVT_MASK | APIC_MODE_MASK,
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[LVT_LINT0] = LINT_MASK,
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[LVT_LINT1] = LINT_MASK,
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[LVT_ERROR] = LVT_MASK
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[LVT_ERROR] = LVT_MASK,
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[LVT_CMCI] = LVT_MASK | APIC_MODE_MASK
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};
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static int find_highest_vector(void *bitmap)
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@ -1436,6 +1445,9 @@ static int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
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APIC_REG_MASK(APIC_TMCCT) |
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APIC_REG_MASK(APIC_TDCR);
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if (kvm_lapic_lvt_supported(apic, LVT_CMCI))
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valid_reg_mask |= APIC_REG_MASK(APIC_LVTCMCI);
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/*
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* ARBPRI and ICR2 are not valid in x2APIC mode. WARN if KVM reads ICR
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* in x2APIC mode as it's an 8-byte register in x2APIC and needs to be
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@ -2044,6 +2056,16 @@ static void kvm_lapic_xapic_id_updated(struct kvm_lapic *apic)
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kvm_set_apicv_inhibit(apic->vcpu->kvm, APICV_INHIBIT_REASON_APIC_ID_MODIFIED);
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}
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static int get_lvt_index(u32 reg)
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{
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if (reg == APIC_LVTCMCI)
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return LVT_CMCI;
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if (reg < APIC_LVTT || reg > APIC_LVTERR)
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return -1;
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return array_index_nospec(
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(reg - APIC_LVTT) >> 4, KVM_APIC_MAX_NR_LVT_ENTRIES);
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}
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static int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
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{
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int ret = 0;
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@ -2090,12 +2112,10 @@ static int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
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apic_set_spiv(apic, val & mask);
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if (!(val & APIC_SPIV_APIC_ENABLED)) {
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int i;
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u32 lvt_val;
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for (i = 0; i < KVM_APIC_MAX_NR_LVT_ENTRIES; i++) {
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lvt_val = kvm_lapic_get_reg(apic, APIC_LVTx(i));
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for (i = 0; i < apic->nr_lvt_entries; i++) {
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kvm_lapic_set_reg(apic, APIC_LVTx(i),
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lvt_val | APIC_LVT_MASKED);
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kvm_lapic_get_reg(apic, APIC_LVTx(i)) | APIC_LVT_MASKED);
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}
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apic_update_lvtt(apic);
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atomic_set(&apic->lapic_timer.pending, 0);
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@ -2124,16 +2144,15 @@ static int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
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case APIC_LVTTHMR:
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case APIC_LVTPC:
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case APIC_LVT1:
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case APIC_LVTERR: {
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/* TODO: Check vector */
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size_t size;
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u32 index;
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case APIC_LVTERR:
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case APIC_LVTCMCI: {
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u32 index = get_lvt_index(reg);
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if (!kvm_lapic_lvt_supported(apic, index)) {
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ret = 1;
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break;
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}
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if (!kvm_apic_sw_enabled(apic))
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val |= APIC_LVT_MASKED;
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size = ARRAY_SIZE(apic_lvt_mask);
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index = array_index_nospec(
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(reg - APIC_LVTT) >> 4, size);
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val &= apic_lvt_mask[index];
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kvm_lapic_set_reg(apic, reg, val);
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break;
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@ -2409,7 +2428,7 @@ void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
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kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
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kvm_apic_set_version(apic->vcpu);
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for (i = 0; i < KVM_APIC_MAX_NR_LVT_ENTRIES; i++)
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for (i = 0; i < apic->nr_lvt_entries; i++)
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kvm_lapic_set_reg(apic, APIC_LVTx(i), APIC_LVT_MASKED);
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apic_update_lvtt(apic);
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if (kvm_vcpu_is_reset_bsp(vcpu) &&
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@ -35,11 +35,12 @@ enum lapic_lvt_entry {
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LVT_LINT0,
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LVT_LINT1,
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LVT_ERROR,
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LVT_CMCI,
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KVM_APIC_MAX_NR_LVT_ENTRIES,
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};
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#define APIC_LVTx(x) (APIC_LVTT + 0x10 * (x))
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#define APIC_LVTx(x) ((x) == LVT_CMCI ? APIC_LVTCMCI : APIC_LVTT + 0x10 * (x))
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struct kvm_timer {
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struct hrtimer timer;
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@ -78,6 +79,7 @@ struct kvm_lapic {
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struct gfn_to_hva_cache vapic_cache;
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unsigned long pending_events;
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unsigned int sipi_vector;
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int nr_lvt_entries;
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};
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struct dest_map;
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@ -4845,6 +4845,8 @@ static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
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/* Init IA32_MCi_CTL to all 1s */
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for (bank = 0; bank < bank_num; bank++)
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vcpu->arch.mce_banks[bank*4] = ~(u64)0;
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vcpu->arch.apic->nr_lvt_entries =
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KVM_APIC_MAX_NR_LVT_ENTRIES - !(mcg_cap & MCG_CMCI_P);
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static_call(kvm_x86_setup_mce)(vcpu);
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out:
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