Amlogic ARM64 DT updates for v4.20, round 2
- new SoC support: basic support for G12A family - new board: Amlogic U200 board, using G12A SoC - fix SPI bus warnings from new dtc updates -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEe4dGDhaSf6n1v/EMWTcYmtP7xmUFAlurUJkACgkQWTcYmtP7 xmW/vw//b31pLYbW7LkgVLnc6iG/FcLitYGSNi/vLLnZn7yQYEWiw014sbjrPfkS I8MufeoEGKml0l9JaWEKAX1MzEiFWKwBHzdDZZRAjperbYfLfa5YlY/JaO8RWyHH 9QplBHf1tFCsUK2XKFC85BZ2iu//y3i6bI1lCjf9Vr/dgfoV+Qu7Qu9TMe7bZsec a/WhnIoQJbeNyUNL+HDagu9YgN7EGBaH42xrIEOPMyYTROCAg2IBVexjLF1nLNT6 BDrfMIkuH63DTXmTUTh5ntGJ50OAAuDhMALS4nyn0uGxFuEKBIiogp/v9gXzF9QT 2sP/1JQwcrVgrKRlyKhtUsLVhv1w5dqP3ym+OCT7gc6Bar17fE3n9T71oeW5G7h+ 0ceW728EzUKTAYKrv9rJ11j7Pjw9m/IrEpdkoqMLRkB5XveFePSxsdNho6QTpuPy RLWhJUW2y1kzE5grK2cY1Y+mZqrzkbkiNeoeqYj1yVDU7wTFiWoL6bscFsIOsx9r J2+exSf9xgbqll1i1WiZqJmyVpB/kD/iHQiz3ijsUlwy+To4pQMy/yAQqSitfJ7q a6SKWZ+U5aFbUbbYxG7+T9QS2exHf4MGanLorYuHC3Vy+Ga7H0dRHFj6rAMQ6vmw W0m0ptiIAzB14oET8HMqUvM+sx1GvB2qGqarPRzCMOJVsbxgDO0= =TU0T -----END PGP SIGNATURE----- Merge tag 'amlogic-dt64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt Amlogic ARM64 DT updates for v4.20, round 2 - new SoC support: basic support for G12A family - new board: Amlogic U200 board, using G12A SoC - fix SPI bus warnings from new dtc updates * tag 'amlogic-dt64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: arm64: dts: meson-g12a: add initial g12a s905d2 SoC DT support dt-bindings: arm: amlogic: Add Meson G12A binding arm64: dts: meson: Fix erroneous SPI bus warnings Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
4bef2317b4
@ -57,6 +57,10 @@ Boards with the Amlogic Meson AXG A113D SoC shall have the following properties:
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Required root node property:
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compatible: "amlogic,a113d", "amlogic,meson-axg";
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Boards with the Amlogic Meson G12A S905D2 SoC shall have the following properties:
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Required root node property:
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compatible: "amlogic,g12a";
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Board compatible values (alphabetically, grouped by SoC):
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- "geniatech,atv1200" (Meson6)
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@ -102,6 +106,8 @@ Board compatible values (alphabetically, grouped by SoC):
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- "amlogic,s400" (Meson axg a113d)
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- "amlogic,u200" (Meson g12a s905d2)
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Amlogic Meson Firmware registers Interface
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------------------------------------------
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@ -1,5 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0
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dtb-$(CONFIG_ARCH_MESON) += meson-axg-s400.dtb
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dtb-$(CONFIG_ARCH_MESON) += meson-g12a-u200.dtb
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dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nanopi-k2.dtb
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dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nexbox-a95x.dtb
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dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-odroidc2.dtb
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29
arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
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29
arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
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@ -0,0 +1,29 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 Amlogic, Inc. All rights reserved.
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*/
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/dts-v1/;
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#include "meson-g12a.dtsi"
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/ {
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compatible = "amlogic,u200", "amlogic,g12a";
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model = "Amlogic Meson G12A U200 Development Board";
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aliases {
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serial0 = &uart_AO;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x40000000>;
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};
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};
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&uart_AO {
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status = "okay";
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};
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172
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
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172
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
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@ -0,0 +1,172 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 Amlogic, Inc. All rights reserved.
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "amlogic,g12a";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <0x2>;
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#size-cells = <0x0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x0>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x1>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x2>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x3>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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};
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l2: l2-cache0 {
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compatible = "cache";
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};
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* 3 MiB reserved for ARM Trusted Firmware (BL31) */
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secmon_reserved: secmon@5000000 {
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reg = <0x0 0x05000000 0x0 0x300000>;
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no-map;
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};
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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periphs: periphs@ff634000 {
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compatible = "simple-bus";
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reg = <0x0 0xff634000 0x0 0x2000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
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};
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hiubus: bus@ff63c000 {
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compatible = "simple-bus";
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reg = <0x0 0xff63c000 0x0 0x1c00>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
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};
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aobus: bus@ff800000 {
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compatible = "simple-bus";
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reg = <0x0 0xff800000 0x0 0x100000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
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uart_AO: serial@3000 {
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compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
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reg = <0x0 0x3000 0x0 0x18>;
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interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
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clocks = <&xtal>, <&xtal>, <&xtal>;
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clock-names = "xtal", "pclk", "baud";
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status = "disabled";
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};
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uart_AO_B: serial@4000 {
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compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
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reg = <0x0 0x4000 0x0 0x18>;
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interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
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clocks = <&xtal>, <&xtal>, <&xtal>;
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clock-names = "xtal", "pclk", "baud";
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status = "disabled";
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};
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};
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gic: interrupt-controller@ffc01000 {
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compatible = "arm,gic-400";
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reg = <0x0 0xffc01000 0 0x1000>,
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<0x0 0xffc02000 0 0x2000>,
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<0x0 0xffc04000 0 0x2000>,
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<0x0 0xffc06000 0 0x2000>;
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interrupt-controller;
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interrupts = <GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
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#interrupt-cells = <3>;
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#address-cells = <0>;
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};
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cbus: bus@ffd00000 {
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compatible = "simple-bus";
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reg = <0x0 0xffd00000 0x0 0x25000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
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};
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apb: apb@ffe00000 {
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compatible = "simple-bus";
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reg = <0x0 0xffe00000 0x0 0x200000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
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};
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xtal: xtal-clk {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "xtal";
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#clock-cells = <0>;
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};
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};
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@ -390,7 +390,7 @@
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};
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};
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spi_pins: spi {
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spi_pins: spi-pins {
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mux {
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groups = "spi_miso",
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"spi_mosi",
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@ -337,7 +337,7 @@
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};
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};
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spi_pins: spi {
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spi_pins: spi-pins {
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mux {
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groups = "spi_miso",
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"spi_mosi",
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