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ARM: at91: remove at91sam9g45/9m10 legacy board support

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Remove legacy support for at91sam9g45/9m10 boards.
This include board files removal plus all legacy code for non DT boards
support (i.e. at91sam9g45.c and at91sam9g45_devices.c).
Use the Device Tree for running this board with newer kernels.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
[nicolas.ferre@atmel.com: Add sentence about DT, removed defconfig]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
This commit is contained in:
Nicolas Ferre 2014-10-21 14:55:46 +02:00
parent 7538ec7d1e
commit 4bf7753b8a
6 changed files with 0 additions and 3091 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

175
arch/arm/configs/at91sam9g45_defconfig
View File

@ -1,175 +0,0 @@
# CONFIG_LOCALVERSION_AUTO is not set
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED=y
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_EMBEDDED=y
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_LBDAF is not set
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_AT91=y
CONFIG_ARCH_AT91SAM9G45=y
CONFIG_MACH_AT91SAM9M10G45EK=y
CONFIG_MACH_AT91SAM9_DT=y
CONFIG_AT91_SLOW_CLOCK=y
CONFIG_AEABI=y
CONFIG_UACCESS_WITH_MEMCPY=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="mem=128M console=ttyS0,115200 initrd=0x71100000,25165824 root=/dev/ram0 rw"
CONFIG_AUTO_ZRELADDR=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_DIAG is not set
CONFIG_IPV6=y
# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
# CONFIG_INET6_XFRM_MODE_BEET is not set
CONFIG_IPV6_SIT_6RD=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_STANDALONE is not set
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_DATAFLASH=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_ATMEL=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_GLUEBI=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=4
CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_ATMEL_TCLIB=y
CONFIG_ATMEL_SSC=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
# CONFIG_SCSI_LOWLEVEL is not set
CONFIG_NETDEVICES=y
CONFIG_MACB=y
CONFIG_DAVICOM_PHY=y
# CONFIG_INPUT_MOUSEDEV is not set
CONFIG_INPUT_JOYDEV=y
CONFIG_INPUT_EVDEV=y
# CONFIG_KEYBOARD_ATKBD is not set
CONFIG_KEYBOARD_QT1070=y
CONFIG_KEYBOARD_QT2160=y
CONFIG_KEYBOARD_GPIO=y
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_ATMEL_MXT=m
# CONFIG_SERIO is not set
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_ATMEL=y
CONFIG_SERIAL_ATMEL_CONSOLE=y
CONFIG_HW_RANDOM=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_GPIO=y
CONFIG_SPI=y
CONFIG_SPI_ATMEL=y
CONFIG_POWER_SUPPLY=y
CONFIG_POWER_RESET=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_NOWAYOUT=y
CONFIG_AT91SAM9X_WATCHDOG=y
CONFIG_FB=y
CONFIG_FB_ATMEL=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_LCD_CLASS_DEVICE=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_ATMEL_LCDC=y
# CONFIG_BACKLIGHT_GENERIC is not set
CONFIG_BACKLIGHT_PWM=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
CONFIG_LOGO=y
CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_SEQUENCER=y
CONFIG_SND_MIXER_OSS=y
CONFIG_SND_PCM_OSS=y
# CONFIG_SND_SUPPORT_OLD_API is not set
# CONFIG_SND_VERBOSE_PROCFS is not set
# CONFIG_SND_DRIVERS is not set
# CONFIG_SND_ARM is not set
CONFIG_SND_ATMEL_AC97C=y
# CONFIG_SND_SPI is not set
# CONFIG_SND_USB is not set
# CONFIG_USB_HID is not set
CONFIG_USB=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_ACM=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_ATMEL_USBA=y
CONFIG_USB_G_MULTI=y
CONFIG_USB_G_MULTI_CDC=y
CONFIG_MMC=y
# CONFIG_MMC_BLOCK_BOUNCE is not set
CONFIG_MMC_ATMELMCI=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_PWM=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_GPIO=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_AT91RM9200=y
CONFIG_DMADEVICES=y
CONFIG_AT_HDMAC=y
CONFIG_DMATEST=m
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_IIO=y
CONFIG_AT91_ADC=y
CONFIG_PWM=y
CONFIG_PWM_ATMEL=y
CONFIG_EXT4_FS=y
CONFIG_FANOTIFY=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_UBIFS_FS=y
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
CONFIG_NFS_FS=y
CONFIG_ROOT_NFS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_850=y
CONFIG_NLS_ISO8859_1=y
CONFIG_STRIP_ASM_SYMS=y
CONFIG_DEBUG_MEMORY_INIT=y
# CONFIG_SCHED_DEBUG is not set
# CONFIG_FTRACE is not set
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_LL=y
CONFIG_EARLY_PRINTK=y
CONFIG_CRYPTO_ECB=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set
CONFIG_CRYPTO_USER_API_HASH=m
CONFIG_CRYPTO_USER_API_SKCIPHER=m
# CONFIG_CRYPTO_HW is not set
CONFIG_FONTS=y

22
arch/arm/mach-at91/Kconfig.non_dt
View File

@ -39,12 +39,6 @@ config ARCH_AT91SAM9RL
select AT91_USE_OLD_CLK
select OLD_IRQ_AT91
config ARCH_AT91SAM9G45
bool "AT91SAM9G45"
select SOC_AT91SAM9G45
select AT91_USE_OLD_CLK
select OLD_IRQ_AT91
endchoice
config ARCH_AT91SAM9G20
@ -300,22 +294,6 @@ endif
# ----------------------------------------------------------
if ARCH_AT91SAM9G45
comment "AT91SAM9G45 Board Type"
config MACH_AT91SAM9M10G45EK
bool "Atmel AT91SAM9M10G45-EK Evaluation Kits"
help
Select this if you are using Atmel's AT91SAM9M10G45-EK Evaluation Kit.
Those boards can be populated with any SoC of AT91SAM9G45 or AT91SAM9M10
families: AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11.
<http://www.atmel.com/tools/SAM9M10-G45-EK.aspx>
endif
# ----------------------------------------------------------
comment "AT91 Board Options"
config MTD_AT91_DATAFLASH_CARD

4
arch/arm/mach-at91/Makefile
View File

@ -25,7 +25,6 @@ obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260_devices.o
obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261_devices.o
obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263_devices.o
obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl_devices.o
obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45_devices.o
# AT91RM9200 board-specific support
obj-$(CONFIG_MACH_ONEARM) += board-1arm.o
@ -71,9 +70,6 @@ obj-$(CONFIG_MACH_GSIA18S) += board-gsia18s.o board-stamp9g20.o
# AT91SAM9260/AT91SAM9G20 board-specific support
obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o
# AT91SAM9G45 board-specific support
obj-$(CONFIG_MACH_AT91SAM9M10G45EK) += board-sam9m10g45ek.o
# AT91SAM board with device-tree
obj-$(CONFIG_MACH_AT91RM9200_DT) += board-dt-rm9200.o
obj-$(CONFIG_MACH_AT91SAM9_DT) += board-dt-sam9.o

448
arch/arm/mach-at91/at91sam9g45.c
View File

@ -10,356 +10,12 @@
*
*/
#include <linux/module.h>
#include <linux/dma-mapping.h>
#include <linux/clk/at91_pmc.h>
#include <linux/platform_device.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/system_misc.h>
#include <mach/at91sam9g45.h>
#include <mach/cpu.h>
#include <mach/hardware.h>
#include "at91_aic.h"
#include "soc.h"
#include "generic.h"
#include "sam9_smc.h"
#include "pm.h"
#if defined(CONFIG_OLD_CLK_AT91)
#include "clock.h"
/* --------------------------------------------------------------------
* Clocks
* -------------------------------------------------------------------- */
/*
* The peripheral clocks.
*/
static struct clk pioA_clk = {
.name = "pioA_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_PIOA,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk pioB_clk = {
.name = "pioB_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_PIOB,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk pioC_clk = {
.name = "pioC_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_PIOC,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk pioDE_clk = {
.name = "pioDE_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_PIODE,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk trng_clk = {
.name = "trng_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_TRNG,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart0_clk = {
.name = "usart0_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_US0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart1_clk = {
.name = "usart1_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_US1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart2_clk = {
.name = "usart2_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_US2,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart3_clk = {
.name = "usart3_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_US3,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk mmc0_clk = {
.name = "mci0_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_MCI0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk twi0_clk = {
.name = "twi0_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_TWI0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk twi1_clk = {
.name = "twi1_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_TWI1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk spi0_clk = {
.name = "spi0_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_SPI0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk spi1_clk = {
.name = "spi1_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_SPI1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk ssc0_clk = {
.name = "ssc0_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_SSC0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk ssc1_clk = {
.name = "ssc1_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_SSC1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tcb0_clk = {
.name = "tcb0_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_TCB,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk pwm_clk = {
.name = "pwm_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_PWMC,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tsc_clk = {
.name = "tsc_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_TSC,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk dma_clk = {
.name = "dma_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_DMA,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk uhphs_clk = {
.name = "uhphs_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_UHPHS,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk lcdc_clk = {
.name = "lcdc_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_LCDC,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk ac97_clk = {
.name = "ac97_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_AC97C,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk macb_clk = {
.name = "pclk",
.pmc_mask = 1 << AT91SAM9G45_ID_EMAC,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk isi_clk = {
.name = "isi_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_ISI,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk udphs_clk = {
.name = "udphs_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_UDPHS,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk mmc1_clk = {
.name = "mci1_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_MCI1,
.type = CLK_TYPE_PERIPHERAL,
};
/* Video decoder clock - Only for sam9m10/sam9m11 */
static struct clk vdec_clk = {
.name = "vdec_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_VDEC,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk adc_op_clk = {
.name = "adc_op_clk",
.type = CLK_TYPE_PERIPHERAL,
.rate_hz = 300000,
};
/* AES/TDES/SHA clock - Only for sam9m11/sam9g56 */
static struct clk aestdessha_clk = {
.name = "aestdessha_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_AESTDESSHA,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk *periph_clocks[] __initdata = {
&pioA_clk,
&pioB_clk,
&pioC_clk,
&pioDE_clk,
&trng_clk,
&usart0_clk,
&usart1_clk,
&usart2_clk,
&usart3_clk,
&mmc0_clk,
&twi0_clk,
&twi1_clk,
&spi0_clk,
&spi1_clk,
&ssc0_clk,
&ssc1_clk,
&tcb0_clk,
&pwm_clk,
&tsc_clk,
&dma_clk,
&uhphs_clk,
&lcdc_clk,
&ac97_clk,
&macb_clk,
&isi_clk,
&udphs_clk,
&mmc1_clk,
&adc_op_clk,
&aestdessha_clk,
// irq0
};
static struct clk_lookup periph_clocks_lookups[] = {
/* One additional fake clock for macb_hclk */
CLKDEV_CON_ID("hclk", &macb_clk),
/* One additional fake clock for ohci */
CLKDEV_CON_ID("ohci_clk", &uhphs_clk),
CLKDEV_CON_DEV_ID("hclk", "at91sam9g45-lcdfb.0", &lcdc_clk),
CLKDEV_CON_DEV_ID("hclk", "at91sam9g45es-lcdfb.0", &lcdc_clk),
CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk),
CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb0_clk),
CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk),
CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.0", &twi0_clk),
CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.1", &twi1_clk),
CLKDEV_CON_DEV_ID("pclk", "at91sam9g45_ssc.0", &ssc0_clk),
CLKDEV_CON_DEV_ID("pclk", "at91sam9g45_ssc.1", &ssc1_clk),
CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc0_clk),
CLKDEV_CON_DEV_ID("pclk", "fffa0000.ssc", &ssc1_clk),
CLKDEV_CON_DEV_ID(NULL, "atmel-trng", &trng_clk),
CLKDEV_CON_DEV_ID(NULL, "atmel_sha", &aestdessha_clk),
CLKDEV_CON_DEV_ID(NULL, "atmel_tdes", &aestdessha_clk),
CLKDEV_CON_DEV_ID(NULL, "atmel_aes", &aestdessha_clk),
CLKDEV_CON_DEV_ID(NULL, "at91sam9rl-pwm", &pwm_clk),
/* more usart lookup table for DT entries */
CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
CLKDEV_CON_DEV_ID("usart", "fff98000.serial", &usart3_clk),
/* more tc lookup table for DT entries */
CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb0_clk),
CLKDEV_CON_DEV_ID("t0_clk", "fffd4000.timer", &tcb0_clk),
CLKDEV_CON_DEV_ID("hclk", "700000.ohci", &uhphs_clk),
CLKDEV_CON_DEV_ID("ehci_clk", "800000.ehci", &uhphs_clk),
CLKDEV_CON_DEV_ID("mci_clk", "fff80000.mmc", &mmc0_clk),
CLKDEV_CON_DEV_ID("mci_clk", "fffd0000.mmc", &mmc1_clk),
CLKDEV_CON_DEV_ID(NULL, "fff84000.i2c", &twi0_clk),
CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi1_clk),
CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
CLKDEV_CON_DEV_ID("hclk", "600000.gadget", &utmi_clk),
CLKDEV_CON_DEV_ID("pclk", "600000.gadget", &udphs_clk),
/* fake hclk clock */
CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioC_clk),
CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioDE_clk),
CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioDE_clk),
CLKDEV_CON_ID("pioA", &pioA_clk),
CLKDEV_CON_ID("pioB", &pioB_clk),
CLKDEV_CON_ID("pioC", &pioC_clk),
CLKDEV_CON_ID("pioD", &pioDE_clk),
CLKDEV_CON_ID("pioE", &pioDE_clk),
/* Fake adc clock */
CLKDEV_CON_ID("adc_clk", &tsc_clk),
CLKDEV_CON_DEV_ID(NULL, "fffb8000.pwm", &pwm_clk),
};
static struct clk_lookup usart_clocks_lookups[] = {
CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
};
/*
* The two programmable clocks.
* You must configure pin multiplexing to bring these signals out.
*/
static struct clk pck0 = {
.name = "pck0",
.pmc_mask = AT91_PMC_PCK0,
.type = CLK_TYPE_PROGRAMMABLE,
.id = 0,
};
static struct clk pck1 = {
.name = "pck1",
.pmc_mask = AT91_PMC_PCK1,
.type = CLK_TYPE_PROGRAMMABLE,
.id = 1,
};
static void __init at91sam9g45_register_clocks(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
clk_register(periph_clocks[i]);
clkdev_add_table(periph_clocks_lookups,
ARRAY_SIZE(periph_clocks_lookups));
clkdev_add_table(usart_clocks_lookups,
ARRAY_SIZE(usart_clocks_lookups));
if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11())
clk_register(&vdec_clk);
clk_register(&pck0);
clk_register(&pck1);
}
#else
#define at91sam9g45_register_clocks NULL
#endif
/* --------------------------------------------------------------------
* GPIO
* -------------------------------------------------------------------- */
static struct at91_gpio_bank at91sam9g45_gpio[] __initdata = {
{
.id = AT91SAM9G45_ID_PIOA,
.regbase = AT91SAM9G45_BASE_PIOA,
}, {
.id = AT91SAM9G45_ID_PIOB,
.regbase = AT91SAM9G45_BASE_PIOB,
}, {
.id = AT91SAM9G45_ID_PIOC,
.regbase = AT91SAM9G45_BASE_PIOC,
}, {
.id = AT91SAM9G45_ID_PIODE,
.regbase = AT91SAM9G45_BASE_PIOD,
}, {
.id = AT91SAM9G45_ID_PIODE,
.regbase = AT91SAM9G45_BASE_PIOE,
}
};
/* --------------------------------------------------------------------
* AT91SAM9G45 processor initialization
@ -370,113 +26,14 @@ static void __init at91sam9g45_map_io(void)
at91_init_sram(0, AT91SAM9G45_SRAM_BASE, AT91SAM9G45_SRAM_SIZE);
}
static void __init at91sam9g45_ioremap_registers(void)
{
at91_ioremap_ramc(0, AT91SAM9G45_BASE_DDRSDRC1, 512);
at91_ioremap_ramc(1, AT91SAM9G45_BASE_DDRSDRC0, 512);
at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT);
at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC);
at91_ioremap_matrix(AT91SAM9G45_BASE_MATRIX);
at91_pm_set_standby(at91_ddr_standby);
}
static void __init at91sam9g45_initialize(void)
{
arm_pm_idle = at91sam9_idle;
at91_sysirq_mask_rtc(AT91SAM9G45_BASE_RTC);
at91_sysirq_mask_rtt(AT91SAM9G45_BASE_RTT);
/* Register GPIO subsystem */
at91_gpio_init(at91sam9g45_gpio, 5);
}
static struct resource rstc_resources[] = {
[0] = {
.start = AT91SAM9G45_BASE_RSTC,
.end = AT91SAM9G45_BASE_RSTC + SZ_16 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = AT91SAM9G45_BASE_DDRSDRC1,
.end = AT91SAM9G45_BASE_DDRSDRC1 + SZ_512 - 1,
.flags = IORESOURCE_MEM,
},
[2] = {
.start = AT91SAM9G45_BASE_DDRSDRC0,
.end = AT91SAM9G45_BASE_DDRSDRC0 + SZ_512 - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device rstc_device = {
.name = "at91-sam9g45-reset",
.resource = rstc_resources,
.num_resources = ARRAY_SIZE(rstc_resources),
};
static struct resource shdwc_resources[] = {
[0] = {
.start = AT91SAM9G45_BASE_SHDWC,
.end = AT91SAM9G45_BASE_SHDWC + SZ_16 - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device shdwc_device = {
.name = "at91-poweroff",
.resource = shdwc_resources,
.num_resources = ARRAY_SIZE(shdwc_resources),
};
static void __init at91sam9g45_register_devices(void)
{
platform_device_register(&rstc_device);
platform_device_register(&shdwc_device);
}
/* --------------------------------------------------------------------
* Interrupt initialization
* -------------------------------------------------------------------- */
/*
* The default interrupt priority levels (0 = lowest, 7 = highest).
*/
static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
7, /* Advanced Interrupt Controller (FIQ) */
7, /* System Peripherals */
1, /* Parallel IO Controller A */
1, /* Parallel IO Controller B */
1, /* Parallel IO Controller C */
1, /* Parallel IO Controller D and E */
0,
5, /* USART 0 */
5, /* USART 1 */
5, /* USART 2 */
5, /* USART 3 */
0, /* Multimedia Card Interface 0 */
6, /* Two-Wire Interface 0 */
6, /* Two-Wire Interface 1 */
5, /* Serial Peripheral Interface 0 */
5, /* Serial Peripheral Interface 1 */
4, /* Serial Synchronous Controller 0 */
4, /* Serial Synchronous Controller 1 */
0, /* Timer Counter 0, 1, 2, 3, 4 and 5 */
0, /* Pulse Width Modulation Controller */
0, /* Touch Screen Controller */
0, /* DMA Controller */
2, /* USB Host High Speed port */
3, /* LDC Controller */
5, /* AC97 Controller */
3, /* Ethernet */
0, /* Image Sensor Interface */
2, /* USB Device High speed port */
0, /* AESTDESSHA Crypto HW Accelerators */
0, /* Multimedia Card Interface 1 */
0,
0, /* Advanced Interrupt Controller (IRQ0) */
};
static void __init at91sam9g45_init_time(void)
{
at91sam926x_pit_init(NR_IRQS_LEGACY + AT91_ID_SYS);
@ -484,11 +41,6 @@ static void __init at91sam9g45_init_time(void)
AT91_SOC_START(at91sam9g45)
.map_io = at91sam9g45_map_io,
.default_irq_priority = at91sam9g45_default_irq_priority,
.extern_irq = (1 << AT91SAM9G45_ID_IRQ0),
.ioremap_registers = at91sam9g45_ioremap_registers,
.register_clocks = at91sam9g45_register_clocks,
.register_devices = at91sam9g45_register_devices,
.init = at91sam9g45_initialize,
.init_time = at91sam9g45_init_time,
AT91_SOC_END

1915
arch/arm/mach-at91/at91sam9g45_devices.c
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File diff suppressed because it is too large Load Diff

527
arch/arm/mach-at91/board-sam9m10g45ek.c
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@ -1,527 +0,0 @@
/*
* Board-specific setup code for the AT91SAM9M10G45 Evaluation Kit family
*
* Covers: * AT91SAM9G45-EKES board
* * AT91SAM9M10G45-EK board
*
* Copyright (C) 2009 Atmel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#include <linux/types.h>
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/fb.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <linux/leds.h>
#include <linux/atmel-mci.h>
#include <linux/delay.h>
#include <linux/pwm.h>
#include <linux/leds_pwm.h>
#include <linux/platform_data/at91_adc.h>
#include <mach/hardware.h>
#include <video/atmel_lcdc.h>
#include <media/soc_camera.h>
#include <media/atmel-isi.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <mach/at91sam9_smc.h>
#include <mach/system_rev.h>
#include "at91_aic.h"
#include "board.h"
#include "sam9_smc.h"
#include "generic.h"
#include "gpio.h"
static void __init ek_init_early(void)
{
/* Initialize processor: 12.000 MHz crystal */
at91_initialize(12000000);
}
/*
* USB HS Host port (common to OHCI & EHCI)
*/
static struct at91_usbh_data __initdata ek_usbh_hs_data = {
.ports = 2,
.vbus_pin = {AT91_PIN_PD1, AT91_PIN_PD3},
.vbus_pin_active_low = {1, 1},
.overcurrent_pin= {-EINVAL, -EINVAL},
};
/*
* USB HS Device port
*/
static struct usba_platform_data __initdata ek_usba_udc_data = {
.vbus_pin = AT91_PIN_PB19,
};
/*
* SPI devices.
*/
static struct spi_board_info ek_spi_devices[] = {
{ /* DataFlash chip */
.modalias = "mtd_dataflash",
.chip_select = 0,
.max_speed_hz = 15 * 1000 * 1000,
.bus_num = 0,
},
};
/*
* MCI (SD/MMC)
*/
static struct mci_platform_data __initdata mci0_data = {
.slot[0] = {
.bus_width = 4,
.detect_pin = AT91_PIN_PD10,
.wp_pin = -EINVAL,
},
};
static struct mci_platform_data __initdata mci1_data = {
.slot[0] = {
.bus_width = 4,
.detect_pin = AT91_PIN_PD11,
.wp_pin = AT91_PIN_PD29,
},
};
/*
* MACB Ethernet device
*/
static struct macb_platform_data __initdata ek_macb_data = {
.phy_irq_pin = AT91_PIN_PD5,
.is_rmii = 1,
};
/*
* NAND flash
*/
static struct mtd_partition __initdata ek_nand_partition[] = {
{
.name = "Partition 1",
.offset = 0,
.size = SZ_64M,
},
{
.name = "Partition 2",
.offset = MTDPART_OFS_NXTBLK,
.size = MTDPART_SIZ_FULL,
},
};
/* det_pin is not connected */
static struct atmel_nand_data __initdata ek_nand_data = {
.ale = 21,
.cle = 22,
.rdy_pin = AT91_PIN_PC8,
.enable_pin = AT91_PIN_PC14,
.det_pin = -EINVAL,
.ecc_mode = NAND_ECC_SOFT,
.on_flash_bbt = 1,
.parts = ek_nand_partition,
.num_parts = ARRAY_SIZE(ek_nand_partition),
};
static struct sam9_smc_config __initdata ek_nand_smc_config = {
.ncs_read_setup = 0,
.nrd_setup = 2,
.ncs_write_setup = 0,
.nwe_setup = 2,
.ncs_read_pulse = 4,
.nrd_pulse = 4,
.ncs_write_pulse = 4,
.nwe_pulse = 4,
.read_cycle = 7,
.write_cycle = 7,
.mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
.tdf_cycles = 3,
};
static void __init ek_add_device_nand(void)
{
ek_nand_data.bus_width_16 = board_have_nand_16bit();
/* setup bus-width (8 or 16) */
if (ek_nand_data.bus_width_16)
ek_nand_smc_config.mode |= AT91_SMC_DBW_16;
else
ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
/* configure chip-select 3 (NAND) */
sam9_smc_configure(0, 3, &ek_nand_smc_config);
at91_add_device_nand(&ek_nand_data);
}
/*
* ISI
*/
static struct isi_platform_data __initdata isi_data = {
.frate = ISI_CFG1_FRATE_CAPTURE_ALL,
/* to use codec and preview path simultaneously */
.full_mode = 1,
.data_width_flags = ISI_DATAWIDTH_8 | ISI_DATAWIDTH_10,
/* ISI_MCK is provided by programmable clock or external clock */
.mck_hz = 25000000,
};
/*
* soc-camera OV2640
*/
#if defined(CONFIG_SOC_CAMERA_OV2640) || \
defined(CONFIG_SOC_CAMERA_OV2640_MODULE)
static unsigned long isi_camera_query_bus_param(struct soc_camera_link *link)
{
/* ISI board for ek using default 8-bits connection */
return SOCAM_DATAWIDTH_8;
}
static int i2c_camera_power(struct device *dev, int on)
{
/* enable or disable the camera */
pr_debug("%s: %s the camera\n", __func__, on ? "ENABLE" : "DISABLE");
at91_set_gpio_output(AT91_PIN_PD13, !on);
if (!on)
goto out;
/* If enabled, give a reset impulse */
at91_set_gpio_output(AT91_PIN_PD12, 0);
msleep(20);
at91_set_gpio_output(AT91_PIN_PD12, 1);
msleep(100);
out:
return 0;
}
static struct i2c_board_info i2c_camera = {
I2C_BOARD_INFO("ov2640", 0x30),
};
static struct soc_camera_link iclink_ov2640 = {
.bus_id = 0,
.board_info = &i2c_camera,
.i2c_adapter_id = 0,
.power = i2c_camera_power,
.query_bus_param = isi_camera_query_bus_param,
};
static struct platform_device isi_ov2640 = {
.name = "soc-camera-pdrv",
.id = 0,
.dev = {
.platform_data = &iclink_ov2640,
},
};
#endif
/*
* LCD Controller
*/
#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
static struct fb_videomode at91_tft_vga_modes[] = {
{
.name = "LG",
.refresh = 60,
.xres = 480, .yres = 272,
.pixclock = KHZ2PICOS(9000),
.left_margin = 1, .right_margin = 1,
.upper_margin = 40, .lower_margin = 1,
.hsync_len = 45, .vsync_len = 1,
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED,
},
};
static struct fb_monspecs at91fb_default_monspecs = {
.manufacturer = "LG",
.monitor = "LB043WQ1",
.modedb = at91_tft_vga_modes,
.modedb_len = ARRAY_SIZE(at91_tft_vga_modes),
.hfmin = 15000,
.hfmax = 17640,
.vfmin = 57,
.vfmax = 67,
};
#define AT91SAM9G45_DEFAULT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \
| ATMEL_LCDC_DISTYPE_TFT \
| ATMEL_LCDC_CLKMOD_ALWAYSACTIVE)
/* Driver datas */
static struct atmel_lcdfb_pdata __initdata ek_lcdc_data = {
.lcdcon_is_backlight = true,
.default_bpp = 32,
.default_dmacon = ATMEL_LCDC_DMAEN,
.default_lcdcon2 = AT91SAM9G45_DEFAULT_LCDCON2,
.default_monspecs = &at91fb_default_monspecs,
.guard_time = 9,
.lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB,
};
#else
static struct atmel_lcdfb_pdata __initdata ek_lcdc_data;
#endif
/*
* ADCs and touchscreen
*/
static struct at91_adc_data ek_adc_data = {
.channels_used = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7),
.use_external_triggers = true,
.vref = 3300,
.touchscreen_type = ATMEL_ADC_TOUCHSCREEN_4WIRE,
};
/*
* GPIO Buttons
*/
#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
static struct gpio_keys_button ek_buttons[] = {
{ /* BP1, "leftclic" */
.code = BTN_LEFT,
.gpio = AT91_PIN_PB6,
.active_low = 1,
.desc = "left_click",
.wakeup = 1,
},
{ /* BP2, "rightclic" */
.code = BTN_RIGHT,
.gpio = AT91_PIN_PB7,
.active_low = 1,
.desc = "right_click",
.wakeup = 1,
},
/* BP3, "joystick" */
{
.code = KEY_LEFT,
.gpio = AT91_PIN_PB14,
.active_low = 1,
.desc = "Joystick Left",
},
{
.code = KEY_RIGHT,
.gpio = AT91_PIN_PB15,
.active_low = 1,
.desc = "Joystick Right",
},
{
.code = KEY_UP,
.gpio = AT91_PIN_PB16,
.active_low = 1,
.desc = "Joystick Up",
},
{
.code = KEY_DOWN,
.gpio = AT91_PIN_PB17,
.active_low = 1,
.desc = "Joystick Down",
},
{
.code = KEY_ENTER,
.gpio = AT91_PIN_PB18,
.active_low = 1,
.desc = "Joystick Press",
},
};
static struct gpio_keys_platform_data ek_button_data = {
.buttons = ek_buttons,
.nbuttons = ARRAY_SIZE(ek_buttons),
};
static struct platform_device ek_button_device = {
.name = "gpio-keys",
.id = -1,
.num_resources = 0,
.dev = {
.platform_data = &ek_button_data,
}
};
static void __init ek_add_device_buttons(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(ek_buttons); i++) {
at91_set_GPIO_periph(ek_buttons[i].gpio, 1);
at91_set_deglitch(ek_buttons[i].gpio, 1);
}
platform_device_register(&ek_button_device);
}
#else
static void __init ek_add_device_buttons(void) {}
#endif
/*
* AC97
* reset_pin is not connected: NRST
*/
static struct ac97c_platform_data ek_ac97_data = {
.reset_pin = -EINVAL,
};
/*
* LEDs ... these could all be PWM-driven, for variable brightness
*/
static struct gpio_led ek_leds[] = {
{ /* "top" led, red, powerled */
.name = "d8",
.gpio = AT91_PIN_PD30,
.default_trigger = "heartbeat",
},
{ /* "left" led, green, userled2, pwm3 */
.name = "d6",
.gpio = AT91_PIN_PD0,
.active_low = 1,
.default_trigger = "nand-disk",
},
#if !IS_ENABLED(CONFIG_LEDS_PWM)
{ /* "right" led, green, userled1, pwm1 */
.name = "d7",
.gpio = AT91_PIN_PD31,
.active_low = 1,
.default_trigger = "mmc0",
},
#endif
};
/*
* PWM Leds
*/
static struct pwm_lookup pwm_lookup[] = {
PWM_LOOKUP("at91sam9rl-pwm", 1, "leds_pwm", "d7",
5000, PWM_POLARITY_INVERSED),
};
#if IS_ENABLED(CONFIG_LEDS_PWM)
static struct led_pwm pwm_leds[] = {
{ /* "right" led, green, userled1, pwm1 */
.name = "d7",
.max_brightness = 255,
},
};
static struct led_pwm_platform_data pwm_data = {
.num_leds = ARRAY_SIZE(pwm_leds),
.leds = pwm_leds,
};
static struct platform_device leds_pwm = {
.name = "leds_pwm",
.id = -1,
.dev = {
.platform_data = &pwm_data,
},
};
#endif
static struct platform_device *devices[] __initdata = {
#if defined(CONFIG_SOC_CAMERA_OV2640) || \
defined(CONFIG_SOC_CAMERA_OV2640_MODULE)
&isi_ov2640,
#endif
#if IS_ENABLED(CONFIG_LEDS_PWM)
&leds_pwm,
#endif
};
static void __init ek_board_init(void)
{
at91_register_devices();
/* Serial */
/* DGBU on ttyS0. (Rx & Tx only) */
at91_register_uart(0, 0, 0);
/* USART0 not connected on the -EK board */
/* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
at91_register_uart(AT91SAM9G45_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
at91_add_device_serial();
/* USB HS Host */
at91_add_device_usbh_ohci(&ek_usbh_hs_data);
at91_add_device_usbh_ehci(&ek_usbh_hs_data);
/* USB HS Device */
at91_add_device_usba(&ek_usba_udc_data);
/* SPI */
at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
/* MMC */
at91_add_device_mci(0, &mci0_data);
at91_add_device_mci(1, &mci1_data);
/* Ethernet */
at91_add_device_eth(&ek_macb_data);
/* NAND */
ek_add_device_nand();
/* I2C */
at91_add_device_i2c(0, NULL, 0);
/* ISI, using programmable clock as ISI_MCK */
at91_add_device_isi(&isi_data, true);
/* LCD Controller */
at91_add_device_lcdc(&ek_lcdc_data);
/* ADC and touchscreen */
at91_add_device_adc(&ek_adc_data);
/* Push Buttons */
ek_add_device_buttons();
/* AC97 */
at91_add_device_ac97(&ek_ac97_data);
/* LEDs */
at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
pwm_add_table(pwm_lookup, ARRAY_SIZE(pwm_lookup));
#if IS_ENABLED(CONFIG_LEDS_PWM)
at91_add_device_pwm(1 << AT91_PWM1);
#endif
/* Other platform devices */
platform_add_devices(devices, ARRAY_SIZE(devices));
}
MACHINE_START(AT91SAM9M10G45EK, "Atmel AT91SAM9M10G45-EK")
/* Maintainer: Atmel */
.init_time = at91_init_time,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
.init_early = ek_init_early,
.init_irq = at91_init_irq_default,
.init_machine = ek_board_init,
MACHINE_END