drm/amd/amdgpu: add pipe1 hardware support
Enable pipe1 support starting from SIENNA CICHLID asic Signed-off-by: Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -4794,7 +4794,7 @@ static int gfx_v10_0_sw_init(void *handle)
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case IP_VERSION(10, 3, 3):
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case IP_VERSION(10, 3, 7):
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adev->gfx.me.num_me = 1;
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adev->gfx.me.num_pipe_per_me = 1;
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adev->gfx.me.num_pipe_per_me = 2;
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adev->gfx.me.num_queue_per_pipe = 1;
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adev->gfx.mec.num_mec = 2;
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adev->gfx.mec.num_pipe_per_mec = 4;
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