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Merge branch 'net-stmmac-dwmac-qcom-ethqos-add-support-for-emac4'

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Bartosz Golaszewski says:

====================
net: stmmac: dwmac-qcom-ethqos: add support for EMAC4

Extend the dwmac-qcom-ethqos driver to support EMAC4. While at it: rework the
code somewhat. The bindings have been reviewed by DT maintainers.

This is a sub-series of [1] with only the patches targetting the net subsystem
as they can go in independently.

[1] https://lore.kernel.org/lkml/20230617001644.4e093326@kernel.org/T/
====================

Link: https://lore.kernel.org/r/20230619092402.195578-1-brgl@bgdev.pl
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski 2023-06-20 20:44:39 -07:00
commit 4cb13ff143
5 changed files with 226 additions and 76 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
Documentation/devicetree/bindings/net/qcom,ethqos.yaml
View File

@ -20,6 +20,7 @@ properties:
compatible:
enum:
- qcom,qcs404-ethqos
- qcom,sa8775p-ethqos
- qcom,sc8280xp-ethqos
- qcom,sm8150-ethqos
@ -32,11 +33,13 @@ properties:
- const: rgmii
interrupts:
minItems: 1
items:
- description: Combined signal for various interrupt events
- description: The interrupt that occurs when Rx exits the LPI state
interrupt-names:
minItems: 1
items:
- const: macirq
- const: eth_lpi
@ -49,11 +52,18 @@ properties:
- const: stmmaceth
- const: pclk
- const: ptp_ref
- const: rgmii
- enum:
- rgmii
- phyaux
iommus:
maxItems: 1
phys: true
phy-names:
const: serdes
required:
- compatible
- clocks

3
Documentation/devicetree/bindings/net/snps,dwmac.yaml
View File

@ -67,6 +67,7 @@ properties:
- loongson,ls2k-dwmac
- loongson,ls7a-dwmac
- qcom,qcs404-ethqos
- qcom,sa8775p-ethqos
- qcom,sc8280xp-ethqos
- qcom,sm8150-ethqos
- renesas,r9a06g032-gmac
@ -582,6 +583,7 @@ allOf:
- ingenic,x1600-mac
- ingenic,x1830-mac
- ingenic,x2000-mac
- qcom,sa8775p-ethqos
- qcom,sc8280xp-ethqos
- snps,dwmac-3.50a
- snps,dwmac-4.10a
@ -638,6 +640,7 @@ allOf:
- ingenic,x1830-mac
- ingenic,x2000-mac
- qcom,qcs404-ethqos
- qcom,sa8775p-ethqos
- qcom,sc8280xp-ethqos
- qcom,sm8150-ethqos
- snps,dwmac-4.00

284
drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
View File

@ -6,6 +6,9 @@
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/phy.h>
#include <linux/phy/phy.h>
#include <linux/property.h>
#include "stmmac.h"
#include "stmmac_platform.h"
@ -72,6 +75,10 @@
#define RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL BIT(6)
#define RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN BIT(5)
/* MAC_CTRL_REG bits */
#define ETHQOS_MAC_CTRL_SPEED_MODE BIT(14)
#define ETHQOS_MAC_CTRL_PORT_SEL BIT(15)
struct ethqos_emac_por {
unsigned int offset;
unsigned int value;
@ -81,22 +88,28 @@ struct ethqos_emac_driver_data {
const struct ethqos_emac_por *por;
unsigned int num_por;
bool rgmii_config_loopback_en;
bool has_emac3;
bool has_emac_ge_3;
const char *link_clk_name;
bool has_integrated_pcs;
struct dwmac4_addrs dwmac4_addrs;
};
struct qcom_ethqos {
struct platform_device *pdev;
void __iomem *rgmii_base;
void __iomem *mac_base;
int (*configure_func)(struct qcom_ethqos *ethqos);
unsigned int rgmii_clk_rate;
struct clk *rgmii_clk;
unsigned int link_clk_rate;
struct clk *link_clk;
struct phy *serdes_phy;
unsigned int speed;
int phy_mode;
const struct ethqos_emac_por *por;
unsigned int num_por;
bool rgmii_config_loopback_en;
bool has_emac3;
bool has_emac_ge_3;
};
static int rgmii_readl(struct qcom_ethqos *ethqos, unsigned int offset)
@ -115,7 +128,7 @@ static void rgmii_updatel(struct qcom_ethqos *ethqos,
{
unsigned int temp;
temp = rgmii_readl(ethqos, offset);
temp = rgmii_readl(ethqos, offset);
temp = (temp & ~(mask)) | val;
rgmii_writel(ethqos, temp, offset);
}
@ -123,25 +136,26 @@ static void rgmii_updatel(struct qcom_ethqos *ethqos,
static void rgmii_dump(void *priv)
{
struct qcom_ethqos *ethqos = priv;
struct device *dev = &ethqos->pdev->dev;
dev_dbg(&ethqos->pdev->dev, "Rgmii register dump\n");
dev_dbg(&ethqos->pdev->dev, "RGMII_IO_MACRO_CONFIG: %x\n",
dev_dbg(dev, "Rgmii register dump\n");
dev_dbg(dev, "RGMII_IO_MACRO_CONFIG: %x\n",
rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG));
dev_dbg(&ethqos->pdev->dev, "SDCC_HC_REG_DLL_CONFIG: %x\n",
dev_dbg(dev, "SDCC_HC_REG_DLL_CONFIG: %x\n",
rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG));
dev_dbg(&ethqos->pdev->dev, "SDCC_HC_REG_DDR_CONFIG: %x\n",
dev_dbg(dev, "SDCC_HC_REG_DDR_CONFIG: %x\n",
rgmii_readl(ethqos, SDCC_HC_REG_DDR_CONFIG));
dev_dbg(&ethqos->pdev->dev, "SDCC_HC_REG_DLL_CONFIG2: %x\n",
dev_dbg(dev, "SDCC_HC_REG_DLL_CONFIG2: %x\n",
rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG2));
dev_dbg(&ethqos->pdev->dev, "SDC4_STATUS: %x\n",
dev_dbg(dev, "SDC4_STATUS: %x\n",
rgmii_readl(ethqos, SDC4_STATUS));
dev_dbg(&ethqos->pdev->dev, "SDCC_USR_CTL: %x\n",
dev_dbg(dev, "SDCC_USR_CTL: %x\n",
rgmii_readl(ethqos, SDCC_USR_CTL));
dev_dbg(&ethqos->pdev->dev, "RGMII_IO_MACRO_CONFIG2: %x\n",
dev_dbg(dev, "RGMII_IO_MACRO_CONFIG2: %x\n",
rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG2));
dev_dbg(&ethqos->pdev->dev, "RGMII_IO_MACRO_DEBUG1: %x\n",
dev_dbg(dev, "RGMII_IO_MACRO_DEBUG1: %x\n",
rgmii_readl(ethqos, RGMII_IO_MACRO_DEBUG1));
dev_dbg(&ethqos->pdev->dev, "EMAC_SYSTEM_LOW_POWER_DEBUG: %x\n",
dev_dbg(dev, "EMAC_SYSTEM_LOW_POWER_DEBUG: %x\n",
rgmii_readl(ethqos, EMAC_SYSTEM_LOW_POWER_DEBUG));
}
@ -151,23 +165,23 @@ static void rgmii_dump(void *priv)
#define RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ (5 * 1000 * 1000UL)
static void
ethqos_update_rgmii_clk(struct qcom_ethqos *ethqos, unsigned int speed)
ethqos_update_link_clk(struct qcom_ethqos *ethqos, unsigned int speed)
{
switch (speed) {
case SPEED_1000:
ethqos->rgmii_clk_rate = RGMII_1000_NOM_CLK_FREQ;
ethqos->link_clk_rate = RGMII_1000_NOM_CLK_FREQ;
break;
case SPEED_100:
ethqos->rgmii_clk_rate = RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ;
ethqos->link_clk_rate = RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ;
break;
case SPEED_10:
ethqos->rgmii_clk_rate = RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ;
ethqos->link_clk_rate = RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ;
break;
}
clk_set_rate(ethqos->rgmii_clk, ethqos->rgmii_clk_rate);
clk_set_rate(ethqos->link_clk, ethqos->link_clk_rate);
}
static void ethqos_set_func_clk_en(struct qcom_ethqos *ethqos)
@ -189,7 +203,7 @@ static const struct ethqos_emac_driver_data emac_v2_3_0_data = {
.por = emac_v2_3_0_por,
.num_por = ARRAY_SIZE(emac_v2_3_0_por),
.rgmii_config_loopback_en = true,
.has_emac3 = false,
.has_emac_ge_3 = false,
};
static const struct ethqos_emac_por emac_v2_1_0_por[] = {
@ -205,7 +219,7 @@ static const struct ethqos_emac_driver_data emac_v2_1_0_data = {
.por = emac_v2_1_0_por,
.num_por = ARRAY_SIZE(emac_v2_1_0_por),
.rgmii_config_loopback_en = false,
.has_emac3 = false,
.has_emac_ge_3 = false,
};
static const struct ethqos_emac_por emac_v3_0_0_por[] = {
@ -221,7 +235,41 @@ static const struct ethqos_emac_driver_data emac_v3_0_0_data = {
.por = emac_v3_0_0_por,
.num_por = ARRAY_SIZE(emac_v3_0_0_por),
.rgmii_config_loopback_en = false,
.has_emac3 = true,
.has_emac_ge_3 = true,
.dwmac4_addrs = {
.dma_chan = 0x00008100,
.dma_chan_offset = 0x1000,
.mtl_chan = 0x00008000,
.mtl_chan_offset = 0x1000,
.mtl_ets_ctrl = 0x00008010,
.mtl_ets_ctrl_offset = 0x1000,
.mtl_txq_weight = 0x00008018,
.mtl_txq_weight_offset = 0x1000,
.mtl_send_slp_cred = 0x0000801c,
.mtl_send_slp_cred_offset = 0x1000,
.mtl_high_cred = 0x00008020,
.mtl_high_cred_offset = 0x1000,
.mtl_low_cred = 0x00008024,
.mtl_low_cred_offset = 0x1000,
},
};
static const struct ethqos_emac_por emac_v4_0_0_por[] = {
{ .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40c01343 },
{ .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642c },
{ .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x80040800 },
{ .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 },
{ .offset = SDCC_USR_CTL, .value = 0x00010800 },
{ .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 },
};
static const struct ethqos_emac_driver_data emac_v4_0_0_data = {
.por = emac_v4_0_0_por,
.num_por = ARRAY_SIZE(emac_v3_0_0_por),
.rgmii_config_loopback_en = false,
.has_emac_ge_3 = true,
.link_clk_name = "phyaux",
.has_integrated_pcs = true,
.dwmac4_addrs = {
.dma_chan = 0x00008100,
.dma_chan_offset = 0x1000,
@ -242,6 +290,7 @@ static const struct ethqos_emac_driver_data emac_v3_0_0_data = {
static int ethqos_dll_configure(struct qcom_ethqos *ethqos)
{
struct device *dev = &ethqos->pdev->dev;
unsigned int val;
int retry = 1000;
@ -261,7 +310,7 @@ static int ethqos_dll_configure(struct qcom_ethqos *ethqos)
rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN,
SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG);
if (!ethqos->has_emac3) {
if (!ethqos->has_emac_ge_3) {
rgmii_updatel(ethqos, SDCC_DLL_MCLK_GATING_EN,
0, SDCC_HC_REG_DLL_CONFIG);
@ -279,7 +328,7 @@ static int ethqos_dll_configure(struct qcom_ethqos *ethqos)
retry--;
} while (retry > 0);
if (!retry)
dev_err(&ethqos->pdev->dev, "Clear CK_OUT_EN timedout\n");
dev_err(dev, "Clear CK_OUT_EN timedout\n");
/* Set CK_OUT_EN */
rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,
@ -296,13 +345,13 @@ static int ethqos_dll_configure(struct qcom_ethqos *ethqos)
retry--;
} while (retry > 0);
if (!retry)
dev_err(&ethqos->pdev->dev, "Set CK_OUT_EN timedout\n");
dev_err(dev, "Set CK_OUT_EN timedout\n");
/* Set DDR_CAL_EN */
rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_CAL_EN,
SDCC_DLL_CONFIG2_DDR_CAL_EN, SDCC_HC_REG_DLL_CONFIG2);
if (!ethqos->has_emac3) {
if (!ethqos->has_emac_ge_3) {
rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DLL_CLOCK_DIS,
0, SDCC_HC_REG_DLL_CONFIG2);
@ -322,14 +371,13 @@ static int ethqos_dll_configure(struct qcom_ethqos *ethqos)
static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos)
{
struct device *dev = &ethqos->pdev->dev;
int phase_shift;
int phy_mode;
int loopback;
/* Determine if the PHY adds a 2 ns TX delay or the MAC handles it */
phy_mode = device_get_phy_mode(&ethqos->pdev->dev);
if (phy_mode == PHY_INTERFACE_MODE_RGMII_ID ||
phy_mode == PHY_INTERFACE_MODE_RGMII_TXID)
if (ethqos->phy_mode == PHY_INTERFACE_MODE_RGMII_ID ||
ethqos->phy_mode == PHY_INTERFACE_MODE_RGMII_TXID)
phase_shift = 0;
else
phase_shift = RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN;
@ -373,7 +421,7 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos)
/* PRG_RCLK_DLY = TCXO period * TCXO_CYCLES_CNT / 2 * RX delay ns,
* in practice this becomes PRG_RCLK_DLY = 52 * 4 / 2 * RX delay ns
*/
if (ethqos->has_emac3) {
if (ethqos->has_emac_ge_3) {
/* 0.9 ns */
rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY,
115, SDCC_HC_REG_DDR_CONFIG);
@ -408,7 +456,7 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos)
rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
0, RGMII_IO_MACRO_CONFIG2);
if (ethqos->has_emac3)
if (ethqos->has_emac_ge_3)
rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
RGMII_CONFIG2_RX_PROG_SWAP,
RGMII_IO_MACRO_CONFIG2);
@ -448,7 +496,7 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos)
RGMII_IO_MACRO_CONFIG);
rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
0, RGMII_IO_MACRO_CONFIG2);
if (ethqos->has_emac3)
if (ethqos->has_emac_ge_3)
rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
RGMII_CONFIG2_RX_PROG_SWAP,
RGMII_IO_MACRO_CONFIG2);
@ -468,16 +516,16 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos)
loopback, RGMII_IO_MACRO_CONFIG);
break;
default:
dev_err(&ethqos->pdev->dev,
"Invalid speed %d\n", ethqos->speed);
dev_err(dev, "Invalid speed %d\n", ethqos->speed);
return -EINVAL;
}
return 0;
}
static int ethqos_configure(struct qcom_ethqos *ethqos)
static int ethqos_configure_rgmii(struct qcom_ethqos *ethqos)
{
struct device *dev = &ethqos->pdev->dev;
volatile unsigned int dll_lock;
unsigned int i, retry = 1000;
@ -497,7 +545,7 @@ static int ethqos_configure(struct qcom_ethqos *ethqos)
rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN,
SDCC_DLL_CONFIG_PDN, SDCC_HC_REG_DLL_CONFIG);
if (ethqos->has_emac3) {
if (ethqos->has_emac_ge_3) {
if (ethqos->speed == SPEED_1000) {
rgmii_writel(ethqos, 0x1800000, SDCC_TEST_CTL);
rgmii_writel(ethqos, 0x2C010800, SDCC_USR_CTL);
@ -527,7 +575,7 @@ static int ethqos_configure(struct qcom_ethqos *ethqos)
SDCC_HC_REG_DLL_CONFIG);
/* Set USR_CTL bit 26 with mask of 3 bits */
if (!ethqos->has_emac3)
if (!ethqos->has_emac_ge_3)
rgmii_updatel(ethqos, GENMASK(26, 24), BIT(26),
SDCC_USR_CTL);
@ -540,8 +588,7 @@ static int ethqos_configure(struct qcom_ethqos *ethqos)
retry--;
} while (retry > 0);
if (!retry)
dev_err(&ethqos->pdev->dev,
"Timeout while waiting for DLL lock\n");
dev_err(dev, "Timeout while waiting for DLL lock\n");
}
if (ethqos->speed == SPEED_1000)
@ -552,24 +599,80 @@ static int ethqos_configure(struct qcom_ethqos *ethqos)
return 0;
}
static int ethqos_configure_sgmii(struct qcom_ethqos *ethqos)
{
int val;
val = readl(ethqos->mac_base + MAC_CTRL_REG);
switch (ethqos->speed) {
case SPEED_1000:
val &= ~ETHQOS_MAC_CTRL_PORT_SEL;
rgmii_updatel(ethqos, RGMII_CONFIG2_RGMII_CLK_SEL_CFG,
RGMII_CONFIG2_RGMII_CLK_SEL_CFG,
RGMII_IO_MACRO_CONFIG2);
break;
case SPEED_100:
val |= ETHQOS_MAC_CTRL_PORT_SEL | ETHQOS_MAC_CTRL_SPEED_MODE;
break;
case SPEED_10:
val |= ETHQOS_MAC_CTRL_PORT_SEL;
val &= ~ETHQOS_MAC_CTRL_SPEED_MODE;
break;
}
writel(val, ethqos->mac_base + MAC_CTRL_REG);
return val;
}
static int ethqos_configure(struct qcom_ethqos *ethqos)
{
return ethqos->configure_func(ethqos);
}
static void ethqos_fix_mac_speed(void *priv, unsigned int speed)
{
struct qcom_ethqos *ethqos = priv;
ethqos->speed = speed;
ethqos_update_rgmii_clk(ethqos, speed);
ethqos_update_link_clk(ethqos, speed);
ethqos_configure(ethqos);
}
static int qcom_ethqos_serdes_powerup(struct net_device *ndev, void *priv)
{
struct qcom_ethqos *ethqos = priv;
int ret;
ret = phy_init(ethqos->serdes_phy);
if (ret)
return ret;
ret = phy_power_on(ethqos->serdes_phy);
if (ret)
return ret;
return phy_set_speed(ethqos->serdes_phy, ethqos->speed);
}
static void qcom_ethqos_serdes_powerdown(struct net_device *ndev, void *priv)
{
struct qcom_ethqos *ethqos = priv;
phy_power_off(ethqos->serdes_phy);
phy_exit(ethqos->serdes_phy);
}
static int ethqos_clks_config(void *priv, bool enabled)
{
struct qcom_ethqos *ethqos = priv;
int ret = 0;
if (enabled) {
ret = clk_prepare_enable(ethqos->rgmii_clk);
ret = clk_prepare_enable(ethqos->link_clk);
if (ret) {
dev_err(&ethqos->pdev->dev, "rgmii_clk enable failed\n");
dev_err(&ethqos->pdev->dev, "link_clk enable failed\n");
return ret;
}
@ -580,18 +683,24 @@ static int ethqos_clks_config(void *priv, bool enabled)
*/
ethqos_set_func_clk_en(ethqos);
} else {
clk_disable_unprepare(ethqos->rgmii_clk);
clk_disable_unprepare(ethqos->link_clk);
}
return ret;
}
static void ethqos_clks_disable(void *data)
{
ethqos_clks_config(data, false);
}
static int qcom_ethqos_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
const struct ethqos_emac_driver_data *data;
struct plat_stmmacenet_data *plat_dat;
struct stmmac_resources stmmac_res;
const struct ethqos_emac_driver_data *data;
struct device *dev = &pdev->dev;
struct qcom_ethqos *ethqos;
int ret;
@ -601,81 +710,108 @@ static int qcom_ethqos_probe(struct platform_device *pdev)
plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac);
if (IS_ERR(plat_dat)) {
dev_err(&pdev->dev, "dt configuration failed\n");
dev_err(dev, "dt configuration failed\n");
return PTR_ERR(plat_dat);
}
plat_dat->clks_config = ethqos_clks_config;
ethqos = devm_kzalloc(&pdev->dev, sizeof(*ethqos), GFP_KERNEL);
ethqos = devm_kzalloc(dev, sizeof(*ethqos), GFP_KERNEL);
if (!ethqos) {
ret = -ENOMEM;
goto err_mem;
goto out_config_dt;
}
ethqos->phy_mode = device_get_phy_mode(dev);
switch (ethqos->phy_mode) {
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_TXID:
ethqos->configure_func = ethqos_configure_rgmii;
break;
case PHY_INTERFACE_MODE_SGMII:
ethqos->configure_func = ethqos_configure_sgmii;
break;
case -ENODEV:
ret = -ENODEV;
goto out_config_dt;
default:
ret = -EINVAL;
goto out_config_dt;
}
ethqos->pdev = pdev;
ethqos->rgmii_base = devm_platform_ioremap_resource_byname(pdev, "rgmii");
if (IS_ERR(ethqos->rgmii_base)) {
ret = PTR_ERR(ethqos->rgmii_base);
goto err_mem;
goto out_config_dt;
}
data = of_device_get_match_data(&pdev->dev);
ethqos->mac_base = stmmac_res.addr;
data = of_device_get_match_data(dev);
ethqos->por = data->por;
ethqos->num_por = data->num_por;
ethqos->rgmii_config_loopback_en = data->rgmii_config_loopback_en;
ethqos->has_emac3 = data->has_emac3;
ethqos->has_emac_ge_3 = data->has_emac_ge_3;
ethqos->rgmii_clk = devm_clk_get(&pdev->dev, "rgmii");
if (IS_ERR(ethqos->rgmii_clk)) {
ret = PTR_ERR(ethqos->rgmii_clk);
goto err_mem;
ethqos->link_clk = devm_clk_get(dev, data->link_clk_name ?: "rgmii");
if (IS_ERR(ethqos->link_clk)) {
ret = PTR_ERR(ethqos->link_clk);
goto out_config_dt;
}
ret = ethqos_clks_config(ethqos, true);
if (ret)
goto err_mem;
goto out_config_dt;
ret = devm_add_action_or_reset(dev, ethqos_clks_disable, ethqos);
if (ret)
goto out_config_dt;
ethqos->serdes_phy = devm_phy_optional_get(dev, "serdes");
if (IS_ERR(ethqos->serdes_phy)) {
ret = PTR_ERR(ethqos->serdes_phy);
goto out_config_dt;
}
ethqos->speed = SPEED_1000;
ethqos_update_rgmii_clk(ethqos, SPEED_1000);
ethqos_update_link_clk(ethqos, SPEED_1000);
ethqos_set_func_clk_en(ethqos);
plat_dat->bsp_priv = ethqos;
plat_dat->fix_mac_speed = ethqos_fix_mac_speed;
plat_dat->dump_debug_regs = rgmii_dump;
plat_dat->has_gmac4 = 1;
if (ethqos->has_emac3)
if (ethqos->has_emac_ge_3)
plat_dat->dwmac4_addrs = &data->dwmac4_addrs;
plat_dat->pmt = 1;
plat_dat->tso_en = of_property_read_bool(np, "snps,tso");
if (of_device_is_compatible(np, "qcom,qcs404-ethqos"))
plat_dat->rx_clk_runs_in_lpi = 1;
plat_dat->has_integrated_pcs = data->has_integrated_pcs;
ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
if (ethqos->serdes_phy) {
plat_dat->serdes_powerup = qcom_ethqos_serdes_powerup;
plat_dat->serdes_powerdown = qcom_ethqos_serdes_powerdown;
}
ret = stmmac_dvr_probe(dev, plat_dat, &stmmac_res);
if (ret)
goto err_clk;
goto out_config_dt;
return ret;
err_clk:
ethqos_clks_config(ethqos, false);
err_mem:
out_config_dt:
stmmac_remove_config_dt(pdev, plat_dat);
return ret;
}
static void qcom_ethqos_remove(struct platform_device *pdev)
{
struct qcom_ethqos *ethqos = get_stmmac_bsp_priv(&pdev->dev);
stmmac_pltfr_remove(pdev);
ethqos_clks_config(ethqos, false);
}
static const struct of_device_id qcom_ethqos_match[] = {
{ .compatible = "qcom,qcs404-ethqos", .data = &emac_v2_3_0_data},
{ .compatible = "qcom,sa8775p-ethqos", .data = &emac_v4_0_0_data},
{ .compatible = "qcom,sc8280xp-ethqos", .data = &emac_v3_0_0_data},
{ .compatible = "qcom,sm8150-ethqos", .data = &emac_v2_1_0_data},
{ }
@ -684,7 +820,7 @@ MODULE_DEVICE_TABLE(of, qcom_ethqos_match);
static struct platform_driver qcom_ethqos_driver = {
.probe = qcom_ethqos_probe,
.remove_new = qcom_ethqos_remove,
.remove_new = stmmac_pltfr_remove,
.driver = {
.name = "qcom-ethqos",
.pm = &stmmac_pltfr_pm_ops,

2
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
View File

@ -5798,7 +5798,7 @@ static void stmmac_common_interrupt(struct stmmac_priv *priv)
}
/* PCS link status */
if (priv->hw->pcs) {
if (priv->hw->pcs && !priv->plat->has_integrated_pcs) {
if (priv->xstats.pcs_link)
netif_carrier_on(priv->dev);
else

1
include/linux/stmmac.h
View File

@ -293,5 +293,6 @@ struct plat_stmmacenet_data {
bool sph_disable;
bool serdes_up_after_phy_linkup;
const struct dwmac4_addrs *dwmac4_addrs;
bool has_integrated_pcs;
};
#endif