From e7a12b6406a478b5c9085091b5015cb3e1683958 Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Thu, 24 Feb 2011 09:02:28 +0200 Subject: [PATCH 001/140] OMAP: 3430SDP: Remove unused vdda_dac supply Remove extra vdda_dac supply definition. It was a leftover from conflict resolution. Signed-off-by: Tomi Valkeinen --- arch/arm/mach-omap2/board-3430sdp.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index 5464bec156ad..e018472861e6 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c @@ -307,9 +307,6 @@ static struct omap_dss_board_info sdp3430_dss_data = { .default_device = &sdp3430_lcd_device, }; -static struct regulator_consumer_supply sdp3430_vdda_dac_supply = - REGULATOR_SUPPLY("vdda_dac", "omapdss"); - static struct omap_board_config_kernel sdp3430_config[] __initdata = { }; From 8ba775ca0d375ab42404ffd7a1a38326a7b21321 Mon Sep 17 00:00:00 2001 From: Sumit Semwal Date: Mon, 24 Jan 2011 06:21:48 +0000 Subject: [PATCH 002/140] OMAP2, 3: DSS2: remove forced clk-disable from omap_dss_remove As part of omap hwmod changes, DSS will not be the only controller of its clocks. hwmod initialization also enables the interface clocks, and manages them. So, when DSS is built as a module, omap_dss_remove doesn't try to disable all clocks that have a higher usecount. Reviewed-by: Kevin Hilman Tested-by: Kevin Hilman Signed-off-by: Sumit Semwal Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/core.c | 46 ++++++---------------------------- 1 file changed, 7 insertions(+), 39 deletions(-) diff --git a/drivers/video/omap2/dss/core.c b/drivers/video/omap2/dss/core.c index 8e89f6049280..ee56859c52ce 100644 --- a/drivers/video/omap2/dss/core.c +++ b/drivers/video/omap2/dss/core.c @@ -623,7 +623,6 @@ static int omap_dss_remove(struct platform_device *pdev) { struct omap_dss_board_info *pdata = pdev->dev.platform_data; int i; - int c; dss_uninitialize_debugfs(); @@ -638,44 +637,13 @@ static int omap_dss_remove(struct platform_device *pdev) dss_exit(); - /* these should be removed at some point */ - c = core.dss_ick->usecount; - if (c > 0) { - DSSERR("warning: dss_ick usecount %d, disabling\n", c); - while (c-- > 0) - clk_disable(core.dss_ick); - } - - c = core.dss1_fck->usecount; - if (c > 0) { - DSSERR("warning: dss1_fck usecount %d, disabling\n", c); - while (c-- > 0) - clk_disable(core.dss1_fck); - } - - c = core.dss2_fck->usecount; - if (c > 0) { - DSSERR("warning: dss2_fck usecount %d, disabling\n", c); - while (c-- > 0) - clk_disable(core.dss2_fck); - } - - c = core.dss_54m_fck->usecount; - if (c > 0) { - DSSERR("warning: dss_54m_fck usecount %d, disabling\n", c); - while (c-- > 0) - clk_disable(core.dss_54m_fck); - } - - if (core.dss_96m_fck) { - c = core.dss_96m_fck->usecount; - if (c > 0) { - DSSERR("warning: dss_96m_fck usecount %d, disabling\n", - c); - while (c-- > 0) - clk_disable(core.dss_96m_fck); - } - } + /* + * As part of hwmod changes, DSS is not the only controller of dss + * clocks; hwmod framework itself will also enable clocks during hwmod + * init for dss, and autoidle is set in h/w for DSS. Hence, there's no + * need to disable clocks if their usecounts > 1. + */ + WARN_ON(core.num_clks_enabled > 0); dss_put_clocks(); From cf07f5316215972e987c63b0a75a922c89813781 Mon Sep 17 00:00:00 2001 From: Senthilvadivu Guruswamy Date: Mon, 24 Jan 2011 06:21:56 +0000 Subject: [PATCH 003/140] OMAP2,3: DSS2: Build omap_device for each DSS HWIP Looks up the hwmod database for each of the given DSS HW IP and builds omap_device which inturn does the platform device register for each of DSS HW IP Signed-off-by: Senthilvadivu Guruswamy Signed-off-by: Sumit Semwal Signed-off-by: Tomi Valkeinen --- arch/arm/mach-omap2/display.c | 52 +++++++++++++++++++++++ arch/arm/plat-omap/include/plat/display.h | 5 +++ 2 files changed, 57 insertions(+) diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c index b18db84b0349..ee8303037d3d 100644 --- a/arch/arm/mach-omap2/display.c +++ b/arch/arm/mach-omap2/display.c @@ -23,6 +23,8 @@ #include #include +#include +#include static struct platform_device omap_display_device = { .name = "omapdss", @@ -32,9 +34,59 @@ static struct platform_device omap_display_device = { }, }; +static struct omap_device_pm_latency omap_dss_latency[] = { + [0] = { + .deactivate_func = omap_device_idle_hwmods, + .activate_func = omap_device_enable_hwmods, + .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, + }, +}; + int __init omap_display_init(struct omap_dss_board_info *board_data) { int r = 0; + struct omap_hwmod *oh; + struct omap_device *od; + int i; + struct omap_display_platform_data pdata; + + /* + * omap: valid DSS hwmod names + * omap2,3: dss_core, dss_dispc, dss_rfbi, dss_venc + * omap3: dss_dsi1 + */ + char *oh_name[] = { "dss_core", "dss_dispc", "dss_rfbi", "dss_venc", + "dss_dsi1" }; + char *dev_name[] = { "omapdss_dss", "omapdss_dispc", "omapdss_rfbi", + "omapdss_venc", "omapdss_dsi1" }; + int oh_count; + + memset(&pdata, 0, sizeof(pdata)); + + if (cpu_is_omap24xx()) + oh_count = ARRAY_SIZE(oh_name) - 1; + /* last hwmod dev in oh_name is not available for omap2 */ + else + oh_count = ARRAY_SIZE(oh_name); + + pdata.board_data = board_data; + pdata.board_data->get_last_off_on_transaction_id = NULL; + + for (i = 0; i < oh_count; i++) { + oh = omap_hwmod_lookup(oh_name[i]); + if (!oh) { + pr_err("Could not look up %s\n", oh_name[i]); + return -ENODEV; + } + od = omap_device_build(dev_name[i], -1, oh, &pdata, + sizeof(struct omap_display_platform_data), + omap_dss_latency, + ARRAY_SIZE(omap_dss_latency), 0); + + if (WARN((IS_ERR(od)), "Could not build omap_device for %s\n", + oh_name[i])) + return -ENODEV; + } omap_display_device.dev.platform_data = board_data; r = platform_device_register(&omap_display_device); diff --git a/arch/arm/plat-omap/include/plat/display.h b/arch/arm/plat-omap/include/plat/display.h index 0f140ecedb01..2fb057e1cb98 100644 --- a/arch/arm/plat-omap/include/plat/display.h +++ b/arch/arm/plat-omap/include/plat/display.h @@ -237,6 +237,11 @@ static inline int omap_display_init(struct omap_dss_board_info *board_data) } #endif +struct omap_display_platform_data { + struct omap_dss_board_info *board_data; + /* TODO: Additional members to be added when PM is considered */ +}; + struct omap_video_timings { /* Unit: pixels */ u16 x_res; From 96c401bcb83a182a4f332f2f64ee6530ba35511a Mon Sep 17 00:00:00 2001 From: Senthilvadivu Guruswamy Date: Mon, 24 Jan 2011 06:21:57 +0000 Subject: [PATCH 004/140] OMAP2, 3: DSS2: DSS: create platform_driver, move init, exit to driver Hwmod adaptation design requires each of the DSS HW IP to be a platform driver. So a platform_driver of DSS is created and init exit methods are moved from core.c to its driver probe,remove. pdev member has to be maintained by its own drivers. DSS platform driver is registered from inside omap_dss_probe, in the order desired. Signed-off-by: Senthilvadivu Guruswamy Signed-off-by: Sumit Semwal Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/core.c | 19 ++++++------ drivers/video/omap2/dss/dss.c | 55 ++++++++++++++++++++++++++++++++-- drivers/video/omap2/dss/dss.h | 4 +-- 3 files changed, 64 insertions(+), 14 deletions(-) diff --git a/drivers/video/omap2/dss/core.c b/drivers/video/omap2/dss/core.c index ee56859c52ce..e399ca22e514 100644 --- a/drivers/video/omap2/dss/core.c +++ b/drivers/video/omap2/dss/core.c @@ -517,15 +517,9 @@ static int omap_dss_probe(struct platform_device *pdev) core.ctx_id = dss_get_ctx_id(); DSSDBG("initial ctx id %u\n", core.ctx_id); -#ifdef CONFIG_FB_OMAP_BOOTLOADER_INIT - /* DISPC_CONTROL */ - if (omap_readl(0x48050440) & 1) /* LCD enabled? */ - skip_init = 1; -#endif - - r = dss_init(skip_init); + r = dss_init_platform_driver(); if (r) { - DSSERR("Failed to initialize DSS\n"); + DSSERR("Failed to initialize DSS platform driver\n"); goto err_dss; } @@ -553,6 +547,11 @@ static int omap_dss_probe(struct platform_device *pdev) goto err_venc; } +#ifdef CONFIG_FB_OMAP_BOOTLOADER_INIT + /* DISPC_CONTROL */ + if (omap_readl(0x48050440) & 1) /* LCD enabled? */ + skip_init = 1; +#endif if (cpu_is_omap34xx()) { r = sdi_init(skip_init); if (r) { @@ -610,7 +609,7 @@ err_dispc: err_dpi: rfbi_exit(); err_rfbi: - dss_exit(); + dss_uninit_platform_driver(); err_dss: dss_clk_disable_all_no_ctx(); dss_put_clocks(); @@ -635,7 +634,7 @@ static int omap_dss_remove(struct platform_device *pdev) sdi_exit(); } - dss_exit(); + dss_uninit_platform_driver(); /* * As part of hwmod changes, DSS is not the only controller of dss diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c index 77c3621c9171..01406f48f438 100644 --- a/drivers/video/omap2/dss/dss.c +++ b/drivers/video/omap2/dss/dss.c @@ -59,6 +59,7 @@ struct dss_reg { dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end)) static struct { + struct platform_device *pdev; void __iomem *base; struct clk *dpll4_m4_ck; @@ -549,7 +550,7 @@ void dss_set_dac_pwrdn_bgz(bool enable) REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */ } -int dss_init(bool skip_init) +static int dss_init(bool skip_init) { int r; u32 rev; @@ -629,7 +630,7 @@ fail0: return r; } -void dss_exit(void) +static void dss_exit(void) { if (cpu_is_omap34xx()) clk_put(dss.dpll4_m4_ck); @@ -639,3 +640,53 @@ void dss_exit(void) iounmap(dss.base); } +/* DSS HW IP initialisation */ +static int omap_dsshw_probe(struct platform_device *pdev) +{ + int r; + int skip_init = 0; + + dss.pdev = pdev; + +#ifdef CONFIG_FB_OMAP_BOOTLOADER_INIT + /* DISPC_CONTROL */ + if (omap_readl(0x48050440) & 1) /* LCD enabled? */ + skip_init = 1; +#endif + + r = dss_init(skip_init); + if (r) { + DSSERR("Failed to initialize DSS\n"); + goto err_dss; + } + +err_dss: + + return r; +} + +static int omap_dsshw_remove(struct platform_device *pdev) +{ + dss_exit(); + + return 0; +} + +static struct platform_driver omap_dsshw_driver = { + .probe = omap_dsshw_probe, + .remove = omap_dsshw_remove, + .driver = { + .name = "omapdss_dss", + .owner = THIS_MODULE, + }, +}; + +int dss_init_platform_driver(void) +{ + return platform_driver_register(&omap_dsshw_driver); +} + +void dss_uninit_platform_driver(void) +{ + return platform_driver_unregister(&omap_dsshw_driver); +} diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h index b394951120ac..37c4544e8907 100644 --- a/drivers/video/omap2/dss/dss.h +++ b/drivers/video/omap2/dss/dss.h @@ -214,8 +214,8 @@ void dss_overlay_setup_l4_manager(struct omap_overlay_manager *mgr); void dss_recheck_connections(struct omap_dss_device *dssdev, bool force); /* DSS */ -int dss_init(bool skip_init); -void dss_exit(void); +int dss_init_platform_driver(void); +void dss_uninit_platform_driver(void); void dss_save_context(void); void dss_restore_context(void); From 8b9cb3a8f39d0864c925c5cd5c2c54cfd85ad551 Mon Sep 17 00:00:00 2001 From: Senthilvadivu Guruswamy Date: Mon, 24 Jan 2011 06:21:58 +0000 Subject: [PATCH 005/140] OMAP2, 3: DSS2: Move clocks from core driver to dss driver All clock management is moved to dss platform driver. clk_get/put APIs use dss device instead of core platform device. Hwmod adaptation design requires each of the DSS HW IP to be a platform driver. So the device name is changed from omapdss to omapdss_dss in 2420, 2430, 3xxx clock database files. Now the core driver "omapdss" only takes care of panel registration with the custom bus. core driver also uses the clk_enable() / clk_disable() APIs exposed by DSS for clock management. DSS driver would do clock management of clocks needed by DISPC, RFBI, DSI, VENC TODO: The clock content would be adapted to omap_hwmod in a seperate series. Signed-off-by: Senthilvadivu Guruswamy Signed-off-by: Sumit Semwal Signed-off-by: Tomi Valkeinen --- arch/arm/mach-omap2/clock2420_data.c | 8 +- arch/arm/mach-omap2/clock2430_data.c | 8 +- arch/arm/mach-omap2/clock3xxx_data.c | 14 +- drivers/video/omap2/dss/core.c | 343 +-------------------------- drivers/video/omap2/dss/dss.c | 334 +++++++++++++++++++++++++- drivers/video/omap2/dss/dss.h | 13 +- 6 files changed, 360 insertions(+), 360 deletions(-) diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c index 0a992bc8d0d8..9ece62a44a3f 100644 --- a/arch/arm/mach-omap2/clock2420_data.c +++ b/arch/arm/mach-omap2/clock2420_data.c @@ -1786,10 +1786,10 @@ static struct omap_clk omap2420_clks[] = { CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_242X), CLK(NULL, "gfx_ick", &gfx_ick, CK_242X), /* DSS domain clocks */ - CLK("omapdss", "ick", &dss_ick, CK_242X), - CLK("omapdss", "dss1_fck", &dss1_fck, CK_242X), - CLK("omapdss", "dss2_fck", &dss2_fck, CK_242X), - CLK("omapdss", "tv_fck", &dss_54m_fck, CK_242X), + CLK("omapdss_dss", "ick", &dss_ick, CK_242X), + CLK("omapdss_dss", "dss1_fck", &dss1_fck, CK_242X), + CLK("omapdss_dss", "dss2_fck", &dss2_fck, CK_242X), + CLK("omapdss_dss", "tv_fck", &dss_54m_fck, CK_242X), /* L3 domain clocks */ CLK(NULL, "core_l3_ck", &core_l3_ck, CK_242X), CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_242X), diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c index 5c647ce05b04..61006ae7eac4 100644 --- a/arch/arm/mach-omap2/clock2430_data.c +++ b/arch/arm/mach-omap2/clock2430_data.c @@ -1890,10 +1890,10 @@ static struct omap_clk omap2430_clks[] = { CLK(NULL, "mdm_ick", &mdm_ick, CK_243X), CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X), /* DSS domain clocks */ - CLK("omapdss", "ick", &dss_ick, CK_243X), - CLK("omapdss", "dss1_fck", &dss1_fck, CK_243X), - CLK("omapdss", "dss2_fck", &dss2_fck, CK_243X), - CLK("omapdss", "tv_fck", &dss_54m_fck, CK_243X), + CLK("omapdss_dss", "ick", &dss_ick, CK_243X), + CLK("omapdss_dss", "dss1_fck", &dss1_fck, CK_243X), + CLK("omapdss_dss", "dss2_fck", &dss2_fck, CK_243X), + CLK("omapdss_dss", "tv_fck", &dss_54m_fck, CK_243X), /* L3 domain clocks */ CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X), CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X), diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index 052ac329282f..2e47d16fce77 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -3357,13 +3357,13 @@ static struct omap_clk omap3xxx_clks[] = { CLK("omap_rng", "ick", &rng_ick, CK_34XX | CK_36XX), CLK(NULL, "sha11_ick", &sha11_ick, CK_34XX | CK_36XX), CLK(NULL, "des1_ick", &des1_ick, CK_34XX | CK_36XX), - CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es1, CK_3430ES1), - CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK("omapdss", "tv_fck", &dss_tv_fck, CK_3XXX), - CLK("omapdss", "video_fck", &dss_96m_fck, CK_3XXX), - CLK("omapdss", "dss2_fck", &dss2_alwon_fck, CK_3XXX), - CLK("omapdss", "ick", &dss_ick_3430es1, CK_3430ES1), - CLK("omapdss", "ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK("omapdss_dss", "dss1_fck", &dss1_alwon_fck_3430es1, CK_3430ES1), + CLK("omapdss_dss", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK("omapdss_dss", "tv_fck", &dss_tv_fck, CK_3XXX), + CLK("omapdss_dss", "video_fck", &dss_96m_fck, CK_3XXX), + CLK("omapdss_dss", "dss2_fck", &dss2_alwon_fck, CK_3XXX), + CLK("omapdss_dss", "ick", &dss_ick_3430es1, CK_3430ES1), + CLK("omapdss_dss", "ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK(NULL, "cam_mclk", &cam_mclk, CK_34XX | CK_36XX), CLK(NULL, "cam_ick", &cam_ick, CK_34XX | CK_36XX), CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_34XX | CK_36XX), diff --git a/drivers/video/omap2/dss/core.c b/drivers/video/omap2/dss/core.c index e399ca22e514..255935541d0d 100644 --- a/drivers/video/omap2/dss/core.c +++ b/drivers/video/omap2/dss/core.c @@ -34,32 +34,18 @@ #include #include -#include #include "dss.h" #include "dss_features.h" static struct { struct platform_device *pdev; - int ctx_id; - - struct clk *dss_ick; - struct clk *dss1_fck; - struct clk *dss2_fck; - struct clk *dss_54m_fck; - struct clk *dss_96m_fck; - unsigned num_clks_enabled; struct regulator *vdds_dsi_reg; struct regulator *vdds_sdi_reg; struct regulator *vdda_dac_reg; } core; -static void dss_clk_enable_all_no_ctx(void); -static void dss_clk_disable_all_no_ctx(void); -static void dss_clk_enable_no_ctx(enum dss_clock clks); -static void dss_clk_disable_no_ctx(enum dss_clock clks); - static char *def_disp_name; module_param_named(def_disp, def_disp_name, charp, 0); MODULE_PARM_DESC(def_disp_name, "default display name"); @@ -69,297 +55,6 @@ unsigned int dss_debug; module_param_named(debug, dss_debug, bool, 0644); #endif -/* CONTEXT */ -static int dss_get_ctx_id(void) -{ - struct omap_dss_board_info *pdata = core.pdev->dev.platform_data; - int r; - - if (!pdata->get_last_off_on_transaction_id) - return 0; - r = pdata->get_last_off_on_transaction_id(&core.pdev->dev); - if (r < 0) { - dev_err(&core.pdev->dev, "getting transaction ID failed, " - "will force context restore\n"); - r = -1; - } - return r; -} - -int dss_need_ctx_restore(void) -{ - int id = dss_get_ctx_id(); - - if (id < 0 || id != core.ctx_id) { - DSSDBG("ctx id %d -> id %d\n", - core.ctx_id, id); - core.ctx_id = id; - return 1; - } else { - return 0; - } -} - -static void save_all_ctx(void) -{ - DSSDBG("save context\n"); - - dss_clk_enable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1); - - dss_save_context(); - dispc_save_context(); -#ifdef CONFIG_OMAP2_DSS_DSI - dsi_save_context(); -#endif - - dss_clk_disable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1); -} - -static void restore_all_ctx(void) -{ - DSSDBG("restore context\n"); - - dss_clk_enable_all_no_ctx(); - - dss_restore_context(); - dispc_restore_context(); -#ifdef CONFIG_OMAP2_DSS_DSI - dsi_restore_context(); -#endif - - dss_clk_disable_all_no_ctx(); -} - -#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) -/* CLOCKS */ -static void core_dump_clocks(struct seq_file *s) -{ - int i; - struct clk *clocks[5] = { - core.dss_ick, - core.dss1_fck, - core.dss2_fck, - core.dss_54m_fck, - core.dss_96m_fck - }; - - seq_printf(s, "- CORE -\n"); - - seq_printf(s, "internal clk count\t\t%u\n", core.num_clks_enabled); - - for (i = 0; i < 5; i++) { - if (!clocks[i]) - continue; - seq_printf(s, "%-15s\t%lu\t%d\n", - clocks[i]->name, - clk_get_rate(clocks[i]), - clocks[i]->usecount); - } -} -#endif /* defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) */ - -static int dss_get_clock(struct clk **clock, const char *clk_name) -{ - struct clk *clk; - - clk = clk_get(&core.pdev->dev, clk_name); - - if (IS_ERR(clk)) { - DSSERR("can't get clock %s", clk_name); - return PTR_ERR(clk); - } - - *clock = clk; - - DSSDBG("clk %s, rate %ld\n", clk_name, clk_get_rate(clk)); - - return 0; -} - -static int dss_get_clocks(void) -{ - int r; - - core.dss_ick = NULL; - core.dss1_fck = NULL; - core.dss2_fck = NULL; - core.dss_54m_fck = NULL; - core.dss_96m_fck = NULL; - - r = dss_get_clock(&core.dss_ick, "ick"); - if (r) - goto err; - - r = dss_get_clock(&core.dss1_fck, "dss1_fck"); - if (r) - goto err; - - r = dss_get_clock(&core.dss2_fck, "dss2_fck"); - if (r) - goto err; - - r = dss_get_clock(&core.dss_54m_fck, "tv_fck"); - if (r) - goto err; - - r = dss_get_clock(&core.dss_96m_fck, "video_fck"); - if (r) - goto err; - - return 0; - -err: - if (core.dss_ick) - clk_put(core.dss_ick); - if (core.dss1_fck) - clk_put(core.dss1_fck); - if (core.dss2_fck) - clk_put(core.dss2_fck); - if (core.dss_54m_fck) - clk_put(core.dss_54m_fck); - if (core.dss_96m_fck) - clk_put(core.dss_96m_fck); - - return r; -} - -static void dss_put_clocks(void) -{ - if (core.dss_96m_fck) - clk_put(core.dss_96m_fck); - clk_put(core.dss_54m_fck); - clk_put(core.dss1_fck); - clk_put(core.dss2_fck); - clk_put(core.dss_ick); -} - -unsigned long dss_clk_get_rate(enum dss_clock clk) -{ - switch (clk) { - case DSS_CLK_ICK: - return clk_get_rate(core.dss_ick); - case DSS_CLK_FCK1: - return clk_get_rate(core.dss1_fck); - case DSS_CLK_FCK2: - return clk_get_rate(core.dss2_fck); - case DSS_CLK_54M: - return clk_get_rate(core.dss_54m_fck); - case DSS_CLK_96M: - return clk_get_rate(core.dss_96m_fck); - } - - BUG(); - return 0; -} - -static unsigned count_clk_bits(enum dss_clock clks) -{ - unsigned num_clks = 0; - - if (clks & DSS_CLK_ICK) - ++num_clks; - if (clks & DSS_CLK_FCK1) - ++num_clks; - if (clks & DSS_CLK_FCK2) - ++num_clks; - if (clks & DSS_CLK_54M) - ++num_clks; - if (clks & DSS_CLK_96M) - ++num_clks; - - return num_clks; -} - -static void dss_clk_enable_no_ctx(enum dss_clock clks) -{ - unsigned num_clks = count_clk_bits(clks); - - if (clks & DSS_CLK_ICK) - clk_enable(core.dss_ick); - if (clks & DSS_CLK_FCK1) - clk_enable(core.dss1_fck); - if (clks & DSS_CLK_FCK2) - clk_enable(core.dss2_fck); - if (clks & DSS_CLK_54M) - clk_enable(core.dss_54m_fck); - if (clks & DSS_CLK_96M) - clk_enable(core.dss_96m_fck); - - core.num_clks_enabled += num_clks; -} - -void dss_clk_enable(enum dss_clock clks) -{ - bool check_ctx = core.num_clks_enabled == 0; - - dss_clk_enable_no_ctx(clks); - - if (check_ctx && cpu_is_omap34xx() && dss_need_ctx_restore()) - restore_all_ctx(); -} - -static void dss_clk_disable_no_ctx(enum dss_clock clks) -{ - unsigned num_clks = count_clk_bits(clks); - - if (clks & DSS_CLK_ICK) - clk_disable(core.dss_ick); - if (clks & DSS_CLK_FCK1) - clk_disable(core.dss1_fck); - if (clks & DSS_CLK_FCK2) - clk_disable(core.dss2_fck); - if (clks & DSS_CLK_54M) - clk_disable(core.dss_54m_fck); - if (clks & DSS_CLK_96M) - clk_disable(core.dss_96m_fck); - - core.num_clks_enabled -= num_clks; -} - -void dss_clk_disable(enum dss_clock clks) -{ - if (cpu_is_omap34xx()) { - unsigned num_clks = count_clk_bits(clks); - - BUG_ON(core.num_clks_enabled < num_clks); - - if (core.num_clks_enabled == num_clks) - save_all_ctx(); - } - - dss_clk_disable_no_ctx(clks); -} - -static void dss_clk_enable_all_no_ctx(void) -{ - enum dss_clock clks; - - clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M; - if (cpu_is_omap34xx()) - clks |= DSS_CLK_96M; - dss_clk_enable_no_ctx(clks); -} - -static void dss_clk_disable_all_no_ctx(void) -{ - enum dss_clock clks; - - clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M; - if (cpu_is_omap34xx()) - clks |= DSS_CLK_96M; - dss_clk_disable_no_ctx(clks); -} - -static void dss_clk_disable_all(void) -{ - enum dss_clock clks; - - clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M; - if (cpu_is_omap34xx()) - clks |= DSS_CLK_96M; - dss_clk_disable(clks); -} - /* REGULATORS */ struct regulator *dss_get_vdds_dsi(void) @@ -404,18 +99,7 @@ struct regulator *dss_get_vdda_dac(void) return reg; } -/* DEBUGFS */ #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) -static void dss_debug_dump_clocks(struct seq_file *s) -{ - core_dump_clocks(s); - dss_dump_clocks(s); - dispc_dump_clocks(s); -#ifdef CONFIG_OMAP2_DSS_DSI - dsi_dump_clocks(s); -#endif -} - static int dss_debug_show(struct seq_file *s, void *unused) { void (*func)(struct seq_file *) = s->private; @@ -508,21 +192,15 @@ static int omap_dss_probe(struct platform_device *pdev) dss_init_overlay_managers(pdev); dss_init_overlays(pdev); - r = dss_get_clocks(); - if (r) - goto err_clocks; - - dss_clk_enable_all_no_ctx(); - - core.ctx_id = dss_get_ctx_id(); - DSSDBG("initial ctx id %u\n", core.ctx_id); - r = dss_init_platform_driver(); if (r) { DSSERR("Failed to initialize DSS platform driver\n"); goto err_dss; } + /* keep clocks enabled to prevent context saves/restores during init */ + dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); + r = rfbi_init(); if (r) { DSSERR("Failed to initialize rfbi\n"); @@ -588,7 +266,7 @@ static int omap_dss_probe(struct platform_device *pdev) pdata->default_device = dssdev; } - dss_clk_disable_all(); + dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); return 0; @@ -611,9 +289,6 @@ err_dpi: err_rfbi: dss_uninit_platform_driver(); err_dss: - dss_clk_disable_all_no_ctx(); - dss_put_clocks(); -err_clocks: return r; } @@ -636,16 +311,6 @@ static int omap_dss_remove(struct platform_device *pdev) dss_uninit_platform_driver(); - /* - * As part of hwmod changes, DSS is not the only controller of dss - * clocks; hwmod framework itself will also enable clocks during hwmod - * init for dss, and autoidle is set in h/w for DSS. Hence, there's no - * need to disable clocks if their usecounts > 1. - */ - WARN_ON(core.num_clks_enabled > 0); - - dss_put_clocks(); - dss_uninit_overlays(pdev); dss_uninit_overlay_managers(pdev); diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c index 01406f48f438..72b395d69aae 100644 --- a/drivers/video/omap2/dss/dss.c +++ b/drivers/video/omap2/dss/dss.c @@ -31,6 +31,7 @@ #include #include +#include #include "dss.h" #define DSS_BASE 0x48050000 @@ -61,8 +62,15 @@ struct dss_reg { static struct { struct platform_device *pdev; void __iomem *base; + int ctx_id; struct clk *dpll4_m4_ck; + struct clk *dss_ick; + struct clk *dss1_fck; + struct clk *dss2_fck; + struct clk *dss_54m_fck; + struct clk *dss_96m_fck; + unsigned num_clks_enabled; unsigned long cache_req_pck; unsigned long cache_prate; @@ -75,6 +83,11 @@ static struct { u32 ctx[DSS_SZ_REGS / sizeof(u32)]; } dss; +static void dss_clk_enable_all_no_ctx(void); +static void dss_clk_disable_all_no_ctx(void); +static void dss_clk_enable_no_ctx(enum dss_clock clks); +static void dss_clk_disable_no_ctx(enum dss_clock clks); + static int _omap_dss_wait_reset(void); static inline void dss_write_reg(const struct dss_reg idx, u32 val) @@ -640,6 +653,301 @@ static void dss_exit(void) iounmap(dss.base); } +/* CONTEXT */ +static int dss_get_ctx_id(void) +{ + struct omap_display_platform_data *pdata = dss.pdev->dev.platform_data; + int r; + + if (!pdata->board_data->get_last_off_on_transaction_id) + return 0; + r = pdata->board_data->get_last_off_on_transaction_id(&dss.pdev->dev); + if (r < 0) { + dev_err(&dss.pdev->dev, "getting transaction ID failed, " + "will force context restore\n"); + r = -1; + } + return r; +} + +int dss_need_ctx_restore(void) +{ + int id = dss_get_ctx_id(); + + if (id < 0 || id != dss.ctx_id) { + DSSDBG("ctx id %d -> id %d\n", + dss.ctx_id, id); + dss.ctx_id = id; + return 1; + } else { + return 0; + } +} + +static void save_all_ctx(void) +{ + DSSDBG("save context\n"); + + dss_clk_enable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1); + + dss_save_context(); + dispc_save_context(); +#ifdef CONFIG_OMAP2_DSS_DSI + dsi_save_context(); +#endif + + dss_clk_disable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1); +} + +static void restore_all_ctx(void) +{ + DSSDBG("restore context\n"); + + dss_clk_enable_all_no_ctx(); + + dss_restore_context(); + dispc_restore_context(); +#ifdef CONFIG_OMAP2_DSS_DSI + dsi_restore_context(); +#endif + + dss_clk_disable_all_no_ctx(); +} + +static int dss_get_clock(struct clk **clock, const char *clk_name) +{ + struct clk *clk; + + clk = clk_get(&dss.pdev->dev, clk_name); + + if (IS_ERR(clk)) { + DSSERR("can't get clock %s", clk_name); + return PTR_ERR(clk); + } + + *clock = clk; + + DSSDBG("clk %s, rate %ld\n", clk_name, clk_get_rate(clk)); + + return 0; +} + +static int dss_get_clocks(void) +{ + int r; + + dss.dss_ick = NULL; + dss.dss1_fck = NULL; + dss.dss2_fck = NULL; + dss.dss_54m_fck = NULL; + dss.dss_96m_fck = NULL; + + r = dss_get_clock(&dss.dss_ick, "ick"); + if (r) + goto err; + + r = dss_get_clock(&dss.dss1_fck, "dss1_fck"); + if (r) + goto err; + + r = dss_get_clock(&dss.dss2_fck, "dss2_fck"); + if (r) + goto err; + + r = dss_get_clock(&dss.dss_54m_fck, "tv_fck"); + if (r) + goto err; + + r = dss_get_clock(&dss.dss_96m_fck, "video_fck"); + if (r) + goto err; + + return 0; + +err: + if (dss.dss_ick) + clk_put(dss.dss_ick); + if (dss.dss1_fck) + clk_put(dss.dss1_fck); + if (dss.dss2_fck) + clk_put(dss.dss2_fck); + if (dss.dss_54m_fck) + clk_put(dss.dss_54m_fck); + if (dss.dss_96m_fck) + clk_put(dss.dss_96m_fck); + + return r; +} + +static void dss_put_clocks(void) +{ + if (dss.dss_96m_fck) + clk_put(dss.dss_96m_fck); + clk_put(dss.dss_54m_fck); + clk_put(dss.dss1_fck); + clk_put(dss.dss2_fck); + clk_put(dss.dss_ick); +} + +unsigned long dss_clk_get_rate(enum dss_clock clk) +{ + switch (clk) { + case DSS_CLK_ICK: + return clk_get_rate(dss.dss_ick); + case DSS_CLK_FCK1: + return clk_get_rate(dss.dss1_fck); + case DSS_CLK_FCK2: + return clk_get_rate(dss.dss2_fck); + case DSS_CLK_54M: + return clk_get_rate(dss.dss_54m_fck); + case DSS_CLK_96M: + return clk_get_rate(dss.dss_96m_fck); + } + + BUG(); + return 0; +} + +static unsigned count_clk_bits(enum dss_clock clks) +{ + unsigned num_clks = 0; + + if (clks & DSS_CLK_ICK) + ++num_clks; + if (clks & DSS_CLK_FCK1) + ++num_clks; + if (clks & DSS_CLK_FCK2) + ++num_clks; + if (clks & DSS_CLK_54M) + ++num_clks; + if (clks & DSS_CLK_96M) + ++num_clks; + + return num_clks; +} + +static void dss_clk_enable_no_ctx(enum dss_clock clks) +{ + unsigned num_clks = count_clk_bits(clks); + + if (clks & DSS_CLK_ICK) + clk_enable(dss.dss_ick); + if (clks & DSS_CLK_FCK1) + clk_enable(dss.dss1_fck); + if (clks & DSS_CLK_FCK2) + clk_enable(dss.dss2_fck); + if (clks & DSS_CLK_54M) + clk_enable(dss.dss_54m_fck); + if (clks & DSS_CLK_96M) + clk_enable(dss.dss_96m_fck); + + dss.num_clks_enabled += num_clks; +} + +void dss_clk_enable(enum dss_clock clks) +{ + bool check_ctx = dss.num_clks_enabled == 0; + + dss_clk_enable_no_ctx(clks); + + if (check_ctx && cpu_is_omap34xx() && dss_need_ctx_restore()) + restore_all_ctx(); +} + +static void dss_clk_disable_no_ctx(enum dss_clock clks) +{ + unsigned num_clks = count_clk_bits(clks); + + if (clks & DSS_CLK_ICK) + clk_disable(dss.dss_ick); + if (clks & DSS_CLK_FCK1) + clk_disable(dss.dss1_fck); + if (clks & DSS_CLK_FCK2) + clk_disable(dss.dss2_fck); + if (clks & DSS_CLK_54M) + clk_disable(dss.dss_54m_fck); + if (clks & DSS_CLK_96M) + clk_disable(dss.dss_96m_fck); + + dss.num_clks_enabled -= num_clks; +} + +void dss_clk_disable(enum dss_clock clks) +{ + if (cpu_is_omap34xx()) { + unsigned num_clks = count_clk_bits(clks); + + BUG_ON(dss.num_clks_enabled < num_clks); + + if (dss.num_clks_enabled == num_clks) + save_all_ctx(); + } + + dss_clk_disable_no_ctx(clks); +} + +static void dss_clk_enable_all_no_ctx(void) +{ + enum dss_clock clks; + + clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M; + if (cpu_is_omap34xx()) + clks |= DSS_CLK_96M; + dss_clk_enable_no_ctx(clks); +} + +static void dss_clk_disable_all_no_ctx(void) +{ + enum dss_clock clks; + + clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M; + if (cpu_is_omap34xx()) + clks |= DSS_CLK_96M; + dss_clk_disable_no_ctx(clks); +} + +#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) +/* CLOCKS */ +static void core_dump_clocks(struct seq_file *s) +{ + int i; + struct clk *clocks[5] = { + dss.dss_ick, + dss.dss1_fck, + dss.dss2_fck, + dss.dss_54m_fck, + dss.dss_96m_fck + }; + + seq_printf(s, "- CORE -\n"); + + seq_printf(s, "internal clk count\t\t%u\n", dss.num_clks_enabled); + + for (i = 0; i < 5; i++) { + if (!clocks[i]) + continue; + seq_printf(s, "%-15s\t%lu\t%d\n", + clocks[i]->name, + clk_get_rate(clocks[i]), + clocks[i]->usecount); + } +} +#endif /* defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) */ + +/* DEBUGFS */ +#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) +void dss_debug_dump_clocks(struct seq_file *s) +{ + core_dump_clocks(s); + dss_dump_clocks(s); + dispc_dump_clocks(s); +#ifdef CONFIG_OMAP2_DSS_DSI + dsi_dump_clocks(s); +#endif +} +#endif + + /* DSS HW IP initialisation */ static int omap_dsshw_probe(struct platform_device *pdev) { @@ -648,6 +956,15 @@ static int omap_dsshw_probe(struct platform_device *pdev) dss.pdev = pdev; + r = dss_get_clocks(); + if (r) + goto err_clocks; + + dss_clk_enable_all_no_ctx(); + + dss.ctx_id = dss_get_ctx_id(); + DSSDBG("initial ctx id %u\n", dss.ctx_id); + #ifdef CONFIG_FB_OMAP_BOOTLOADER_INIT /* DISPC_CONTROL */ if (omap_readl(0x48050440) & 1) /* LCD enabled? */ @@ -660,15 +977,30 @@ static int omap_dsshw_probe(struct platform_device *pdev) goto err_dss; } -err_dss: + dss_clk_disable_all_no_ctx(); + return 0; +err_dss: + dss_clk_disable_all_no_ctx(); + dss_put_clocks(); +err_clocks: return r; } static int omap_dsshw_remove(struct platform_device *pdev) { + dss_exit(); + /* + * As part of hwmod changes, DSS is not the only controller of dss + * clocks; hwmod framework itself will also enable clocks during hwmod + * init for dss, and autoidle is set in h/w for DSS. Hence, there's no + * need to disable clocks if their usecounts > 1. + */ + WARN_ON(dss.num_clks_enabled > 0); + + dss_put_clocks(); return 0; } diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h index 37c4544e8907..c535ee1db3ee 100644 --- a/drivers/video/omap2/dss/dss.h +++ b/drivers/video/omap2/dss/dss.h @@ -169,11 +169,6 @@ struct seq_file; struct platform_device; /* core */ -void dss_clk_enable(enum dss_clock clks); -void dss_clk_disable(enum dss_clock clks); -unsigned long dss_clk_get_rate(enum dss_clock clk); -int dss_need_ctx_restore(void); -void dss_dump_clocks(struct seq_file *s); struct bus_type *dss_get_bus(void); struct regulator *dss_get_vdds_dsi(void); struct regulator *dss_get_vdds_sdi(void); @@ -219,8 +214,16 @@ void dss_uninit_platform_driver(void); void dss_save_context(void); void dss_restore_context(void); +void dss_clk_enable(enum dss_clock clks); +void dss_clk_disable(enum dss_clock clks); +unsigned long dss_clk_get_rate(enum dss_clock clk); +int dss_need_ctx_restore(void); +void dss_dump_clocks(struct seq_file *s); void dss_dump_regs(struct seq_file *s); +#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) +void dss_debug_dump_clocks(struct seq_file *s); +#endif void dss_sdi_init(u8 datapairs); int dss_sdi_enable(void); From 3448d500f7002a5ee374ec92d954b1667cbf72a4 Mon Sep 17 00:00:00 2001 From: Senthilvadivu Guruswamy Date: Mon, 24 Jan 2011 06:21:59 +0000 Subject: [PATCH 006/140] OMAP2, 3: DSS2: RFBI: create platform_driver, move init, exit to driver Hwmod adaptation design requires each of the DSS HW IP to be a platform driver. So a platform_driver for RFBI is created and init exit methods are moved from core.c to its driver probe,remove. pdev member has to be maintained by its own drivers. RFBI platform driver is registered from inside omap_dss_probe, in the order desired. Signed-off-by: Senthilvadivu Guruswamy Signed-off-by: Sumit Semwal Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/core.c | 8 +-- drivers/video/omap2/dss/dss.h | 8 +-- drivers/video/omap2/dss/rfbi.c | 110 ++++++++++++++++++++------------- 3 files changed, 74 insertions(+), 52 deletions(-) diff --git a/drivers/video/omap2/dss/core.c b/drivers/video/omap2/dss/core.c index 255935541d0d..8eef616fee03 100644 --- a/drivers/video/omap2/dss/core.c +++ b/drivers/video/omap2/dss/core.c @@ -201,9 +201,9 @@ static int omap_dss_probe(struct platform_device *pdev) /* keep clocks enabled to prevent context saves/restores during init */ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); - r = rfbi_init(); + r = rfbi_init_platform_driver(); if (r) { - DSSERR("Failed to initialize rfbi\n"); + DSSERR("Failed to initialize rfbi platform driver\n"); goto err_rfbi; } @@ -285,7 +285,7 @@ err_venc: err_dispc: dpi_exit(); err_dpi: - rfbi_exit(); + rfbi_uninit_platform_driver(); err_rfbi: dss_uninit_platform_driver(); err_dss: @@ -303,7 +303,7 @@ static int omap_dss_remove(struct platform_device *pdev) venc_exit(); dispc_exit(); dpi_exit(); - rfbi_exit(); + rfbi_uninit_platform_driver(); if (cpu_is_omap34xx()) { dsi_exit(); sdi_exit(); diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h index c535ee1db3ee..0ba4bdbd6b01 100644 --- a/drivers/video/omap2/dss/dss.h +++ b/drivers/video/omap2/dss/dss.h @@ -428,8 +428,8 @@ static inline void venc_exit(void) /* RFBI */ #ifdef CONFIG_OMAP2_DSS_RFBI -int rfbi_init(void); -void rfbi_exit(void); +int rfbi_init_platform_driver(void); +void rfbi_uninit_platform_driver(void); void rfbi_dump_regs(struct seq_file *s); int rfbi_configure(int rfbi_module, int bpp, int lines); @@ -440,11 +440,11 @@ void rfbi_set_timings(int rfbi_module, struct rfbi_timings *t); unsigned long rfbi_get_max_tx_rate(void); int rfbi_init_display(struct omap_dss_device *display); #else -static inline int rfbi_init(void) +static inline int rfbi_init_platform_driver(void) { return 0; } -static inline void rfbi_exit(void) +static inline void rfbi_uninit_platform_driver(void) { } #endif diff --git a/drivers/video/omap2/dss/rfbi.c b/drivers/video/omap2/dss/rfbi.c index 10a2ffe02882..153f963e8e89 100644 --- a/drivers/video/omap2/dss/rfbi.c +++ b/drivers/video/omap2/dss/rfbi.c @@ -100,6 +100,7 @@ static int rfbi_convert_timings(struct rfbi_timings *t); static void rfbi_get_clk_info(u32 *clk_period, u32 *max_clk_div); static struct { + struct platform_device *pdev; void __iomem *base; unsigned long l4_khz; @@ -957,50 +958,6 @@ void rfbi_dump_regs(struct seq_file *s) #undef DUMPREG } -int rfbi_init(void) -{ - u32 rev; - u32 l; - - spin_lock_init(&rfbi.cmd_lock); - - init_completion(&rfbi.cmd_done); - atomic_set(&rfbi.cmd_fifo_full, 0); - atomic_set(&rfbi.cmd_pending, 0); - - rfbi.base = ioremap(RFBI_BASE, SZ_256); - if (!rfbi.base) { - DSSERR("can't ioremap RFBI\n"); - return -ENOMEM; - } - - rfbi_enable_clocks(1); - - msleep(10); - - rfbi.l4_khz = dss_clk_get_rate(DSS_CLK_ICK) / 1000; - - /* Enable autoidle and smart-idle */ - l = rfbi_read_reg(RFBI_SYSCONFIG); - l |= (1 << 0) | (2 << 3); - rfbi_write_reg(RFBI_SYSCONFIG, l); - - rev = rfbi_read_reg(RFBI_REVISION); - printk(KERN_INFO "OMAP RFBI rev %d.%d\n", - FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); - - rfbi_enable_clocks(0); - - return 0; -} - -void rfbi_exit(void) -{ - DSSDBG("rfbi_exit\n"); - - iounmap(rfbi.base); -} - int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev) { int r; @@ -1056,3 +1013,68 @@ int rfbi_init_display(struct omap_dss_device *dssdev) dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE; return 0; } + +/* RFBI HW IP initialisation */ +static int omap_rfbihw_probe(struct platform_device *pdev) +{ + u32 rev; + u32 l; + + rfbi.pdev = pdev; + + spin_lock_init(&rfbi.cmd_lock); + + init_completion(&rfbi.cmd_done); + atomic_set(&rfbi.cmd_fifo_full, 0); + atomic_set(&rfbi.cmd_pending, 0); + + rfbi.base = ioremap(RFBI_BASE, SZ_256); + if (!rfbi.base) { + DSSERR("can't ioremap RFBI\n"); + return -ENOMEM; + } + + rfbi_enable_clocks(1); + + msleep(10); + + rfbi.l4_khz = dss_clk_get_rate(DSS_CLK_ICK) / 1000; + + /* Enable autoidle and smart-idle */ + l = rfbi_read_reg(RFBI_SYSCONFIG); + l |= (1 << 0) | (2 << 3); + rfbi_write_reg(RFBI_SYSCONFIG, l); + + rev = rfbi_read_reg(RFBI_REVISION); + printk(KERN_INFO "OMAP RFBI rev %d.%d\n", + FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); + + rfbi_enable_clocks(0); + + return 0; +} + +static int omap_rfbihw_remove(struct platform_device *pdev) +{ + iounmap(rfbi.base); + return 0; +} + +static struct platform_driver omap_rfbihw_driver = { + .probe = omap_rfbihw_probe, + .remove = omap_rfbihw_remove, + .driver = { + .name = "omapdss_rfbi", + .owner = THIS_MODULE, + }, +}; + +int rfbi_init_platform_driver(void) +{ + return platform_driver_register(&omap_rfbihw_driver); +} + +void rfbi_uninit_platform_driver(void) +{ + return platform_driver_unregister(&omap_rfbihw_driver); +} From 060b6d9cbab03f1379dbe00393ab26d6eb371ce2 Mon Sep 17 00:00:00 2001 From: Senthilvadivu Guruswamy Date: Mon, 24 Jan 2011 06:22:00 +0000 Subject: [PATCH 007/140] OMAP2, 3: DSS2: DISPC: create platform_driver, move init, exit to driver Hwmod adaptation design requires each of the DSS HW IP to be a platform driver. So a platform_driver for DISPC is created and init exit methods are moved from core.c to its driver probe,remove. pdev member has to be maintained by its own drivers. DISPC platform driver is registered from inside omap_dss_probe, in the order desired. Signed-off-by: Senthilvadivu Guruswamy Signed-off-by: Sumit Semwal Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/core.c | 8 +-- drivers/video/omap2/dss/dispc.c | 105 +++++++++++++++++++------------- drivers/video/omap2/dss/dss.h | 4 +- 3 files changed, 70 insertions(+), 47 deletions(-) diff --git a/drivers/video/omap2/dss/core.c b/drivers/video/omap2/dss/core.c index 8eef616fee03..8b7eab83e412 100644 --- a/drivers/video/omap2/dss/core.c +++ b/drivers/video/omap2/dss/core.c @@ -213,9 +213,9 @@ static int omap_dss_probe(struct platform_device *pdev) goto err_dpi; } - r = dispc_init(); + r = dispc_init_platform_driver(); if (r) { - DSSERR("Failed to initialize dispc\n"); + DSSERR("Failed to initialize dispc platform driver\n"); goto err_dispc; } @@ -281,7 +281,7 @@ err_dsi: err_sdi: venc_exit(); err_venc: - dispc_exit(); + dispc_uninit_platform_driver(); err_dispc: dpi_exit(); err_dpi: @@ -301,7 +301,7 @@ static int omap_dss_remove(struct platform_device *pdev) dss_uninitialize_debugfs(); venc_exit(); - dispc_exit(); + dispc_uninit_platform_driver(); dpi_exit(); rfbi_uninit_platform_driver(); if (cpu_is_omap34xx()) { diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c index 9f8c69f16e61..28ad68b6be48 100644 --- a/drivers/video/omap2/dss/dispc.c +++ b/drivers/video/omap2/dss/dispc.c @@ -178,6 +178,7 @@ struct dispc_irq_stats { }; static struct { + struct platform_device *pdev; void __iomem *base; u32 fifo_size[3]; @@ -3269,47 +3270,6 @@ static void _omap_dispc_initial_config(void) dispc_read_plane_fifo_sizes(); } -int dispc_init(void) -{ - u32 rev; - - spin_lock_init(&dispc.irq_lock); - -#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS - spin_lock_init(&dispc.irq_stats_lock); - dispc.irq_stats.last_reset = jiffies; -#endif - - INIT_WORK(&dispc.error_work, dispc_error_worker); - - dispc.base = ioremap(DISPC_BASE, DISPC_SZ_REGS); - if (!dispc.base) { - DSSERR("can't ioremap DISPC\n"); - return -ENOMEM; - } - - enable_clocks(1); - - _omap_dispc_initial_config(); - - _omap_dispc_initialize_irq(); - - dispc_save_context(); - - rev = dispc_read_reg(DISPC_REVISION); - printk(KERN_INFO "OMAP DISPC rev %d.%d\n", - FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); - - enable_clocks(0); - - return 0; -} - -void dispc_exit(void) -{ - iounmap(dispc.base); -} - int dispc_enable_plane(enum omap_plane plane, bool enable) { DSSDBG("dispc_enable_plane %d, %d\n", plane, enable); @@ -3359,3 +3319,66 @@ int dispc_setup_plane(enum omap_plane plane, return r; } + +/* DISPC HW IP initialisation */ +static int omap_dispchw_probe(struct platform_device *pdev) +{ + u32 rev; + dispc.pdev = pdev; + + spin_lock_init(&dispc.irq_lock); + +#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS + spin_lock_init(&dispc.irq_stats_lock); + dispc.irq_stats.last_reset = jiffies; +#endif + + INIT_WORK(&dispc.error_work, dispc_error_worker); + + dispc.base = ioremap(DISPC_BASE, DISPC_SZ_REGS); + if (!dispc.base) { + DSSERR("can't ioremap DISPC\n"); + return -ENOMEM; + } + + enable_clocks(1); + + _omap_dispc_initial_config(); + + _omap_dispc_initialize_irq(); + + dispc_save_context(); + + rev = dispc_read_reg(DISPC_REVISION); + printk(KERN_INFO "OMAP DISPC rev %d.%d\n", + FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); + + enable_clocks(0); + + return 0; +} + +static int omap_dispchw_remove(struct platform_device *pdev) +{ + iounmap(dispc.base); + return 0; +} + +static struct platform_driver omap_dispchw_driver = { + .probe = omap_dispchw_probe, + .remove = omap_dispchw_remove, + .driver = { + .name = "omapdss_dispc", + .owner = THIS_MODULE, + }, +}; + +int dispc_init_platform_driver(void) +{ + return platform_driver_register(&omap_dispchw_driver); +} + +void dispc_uninit_platform_driver(void) +{ + return platform_driver_unregister(&omap_dispchw_driver); +} diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h index 0ba4bdbd6b01..f4835c85db90 100644 --- a/drivers/video/omap2/dss/dss.h +++ b/drivers/video/omap2/dss/dss.h @@ -319,8 +319,8 @@ static inline void dpi_exit(void) #endif /* DISPC */ -int dispc_init(void); -void dispc_exit(void); +int dispc_init_platform_driver(void); +void dispc_uninit_platform_driver(void); void dispc_dump_clocks(struct seq_file *s); void dispc_dump_irqs(struct seq_file *s); void dispc_dump_regs(struct seq_file *s); From 30ea50c9f5166a375b4dc0109d18a5d21bab5711 Mon Sep 17 00:00:00 2001 From: Senthilvadivu Guruswamy Date: Mon, 24 Jan 2011 06:22:01 +0000 Subject: [PATCH 008/140] OMAP2, 3: DSS2: VENC: create platform_driver, move init, exit to driver Hwmod adaptation design requires each of the DSS HW IP to be a platform driver. So a platform_driver for VENC is created and init exit methods are moved from core.c to its driver probe,remove. pdev member has to be maintained by its own drivers. Also, venc_vdda_dac reading is moved to venc.c. VENC platform driver is registered from inside omap_dss_probe, in the order desired. Signed-off-by: Senthilvadivu Guruswamy Signed-off-by: Sumit Semwal Signed-off-by: Tomi Valkeinen --- arch/arm/mach-omap2/board-3430sdp.c | 2 +- arch/arm/mach-omap2/board-cm-t35.c | 2 +- arch/arm/mach-omap2/board-devkit8000.c | 2 +- arch/arm/mach-omap2/board-omap3beagle.c | 2 +- arch/arm/mach-omap2/board-omap3evm.c | 2 +- arch/arm/mach-omap2/board-omap3pandora.c | 2 +- arch/arm/mach-omap2/board-omap3stalker.c | 2 +- arch/arm/mach-omap2/board-rx51-peripherals.c | 2 +- arch/arm/mach-omap2/board-zoom-peripherals.c | 2 +- drivers/video/omap2/dss/core.c | 28 +---- drivers/video/omap2/dss/dss.h | 9 +- drivers/video/omap2/dss/venc.c | 116 ++++++++++++------- 12 files changed, 93 insertions(+), 78 deletions(-) diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index e018472861e6..652e7c38c62e 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c @@ -395,7 +395,7 @@ static struct regulator_consumer_supply sdp3430_vaux3_supplies[] = { }; static struct regulator_consumer_supply sdp3430_vdda_dac_supplies[] = { - REGULATOR_SUPPLY("vdda_dac", "omapdss"), + REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"), }; /* VPLL2 for digital video outputs */ diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index 27bea540ccbb..e55fde0a720d 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c @@ -488,7 +488,7 @@ static struct regulator_consumer_supply cm_t35_vsim_supply = { }; static struct regulator_consumer_supply cm_t35_vdac_supply = - REGULATOR_SUPPLY("vdda_dac", "omapdss"); + REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"); static struct regulator_consumer_supply cm_t35_vdvi_supply = REGULATOR_SUPPLY("vdvi", "omapdss"); diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c index 728f27c5bcb1..b64774b3d82c 100644 --- a/arch/arm/mach-omap2/board-devkit8000.c +++ b/arch/arm/mach-omap2/board-devkit8000.c @@ -196,7 +196,7 @@ static struct omap_dss_board_info devkit8000_dss_data = { }; static struct regulator_consumer_supply devkit8000_vdda_dac_supply = - REGULATOR_SUPPLY("vdda_dac", "omapdss"); + REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"); static uint32_t board_keymap[] = { KEY(0, 0, KEY_1), diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 20c5dbea8953..2fad38f9e683 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -232,7 +232,7 @@ static struct omap_dss_board_info beagle_dss_data = { }; static struct regulator_consumer_supply beagle_vdac_supply = - REGULATOR_SUPPLY("vdda_dac", "omapdss"); + REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"); static struct regulator_consumer_supply beagle_vdvi_supply = REGULATOR_SUPPLY("vdds_dsi", "omapdss"); diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index b65848c59e1d..a6564b41b97a 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -542,7 +542,7 @@ static struct twl4030_codec_data omap3evm_codec_data = { }; static struct regulator_consumer_supply omap3_evm_vdda_dac_supply = - REGULATOR_SUPPLY("vdda_dac", "omapdss"); + REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"); /* VDAC for DSS driving S-Video */ static struct regulator_init_data omap3_evm_vdac = { diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c index 5386a8190ea1..37de418edd2a 100644 --- a/arch/arm/mach-omap2/board-omap3pandora.c +++ b/arch/arm/mach-omap2/board-omap3pandora.c @@ -342,7 +342,7 @@ static struct regulator_consumer_supply pandora_vmmc3_supply = REGULATOR_SUPPLY("vmmc", "omap_hsmmc.2"); static struct regulator_consumer_supply pandora_vdda_dac_supply = - REGULATOR_SUPPLY("vdda_dac", "omapdss"); + REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"); static struct regulator_consumer_supply pandora_vdds_supplies[] = { REGULATOR_SUPPLY("vdds_sdi", "omapdss"), diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c index 15ede8b49815..bd0eed858078 100644 --- a/arch/arm/mach-omap2/board-omap3stalker.c +++ b/arch/arm/mach-omap2/board-omap3stalker.c @@ -439,7 +439,7 @@ static struct twl4030_codec_data omap3stalker_codec_data = { }; static struct regulator_consumer_supply omap3_stalker_vdda_dac_supply = - REGULATOR_SUPPLY("vdda_dac", "omapdss"); + REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"); /* VDAC for DSS driving S-Video */ static struct regulator_init_data omap3_stalker_vdac = { diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index 5f1900c532ec..bbcb6775a6a3 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -372,7 +372,7 @@ static struct regulator_consumer_supply rx51_vaux1_consumers[] = { }; static struct regulator_consumer_supply rx51_vdac_supply[] = { - REGULATOR_SUPPLY("vdda_dac", "omapdss"), + REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"), }; static struct regulator_init_data rx51_vaux1 = { diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c index 448ab60195d5..405400c4762b 100644 --- a/arch/arm/mach-omap2/board-zoom-peripherals.c +++ b/arch/arm/mach-omap2/board-zoom-peripherals.c @@ -230,7 +230,7 @@ static struct regulator_consumer_supply zoom_vpll2_supply = REGULATOR_SUPPLY("vdds_dsi", "omapdss"); static struct regulator_consumer_supply zoom_vdda_dac_supply = - REGULATOR_SUPPLY("vdda_dac", "omapdss"); + REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"); static struct regulator_init_data zoom_vpll2 = { .constraints = { diff --git a/drivers/video/omap2/dss/core.c b/drivers/video/omap2/dss/core.c index 8b7eab83e412..57c6303cb1cd 100644 --- a/drivers/video/omap2/dss/core.c +++ b/drivers/video/omap2/dss/core.c @@ -43,7 +43,6 @@ static struct { struct regulator *vdds_dsi_reg; struct regulator *vdds_sdi_reg; - struct regulator *vdda_dac_reg; } core; static char *def_disp_name; @@ -85,20 +84,6 @@ struct regulator *dss_get_vdds_sdi(void) return reg; } -struct regulator *dss_get_vdda_dac(void) -{ - struct regulator *reg; - - if (core.vdda_dac_reg != NULL) - return core.vdda_dac_reg; - - reg = regulator_get(&core.pdev->dev, "vdda_dac"); - if (!IS_ERR(reg)) - core.vdda_dac_reg = reg; - - return reg; -} - #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) static int dss_debug_show(struct seq_file *s, void *unused) { @@ -219,9 +204,9 @@ static int omap_dss_probe(struct platform_device *pdev) goto err_dispc; } - r = venc_init(pdev); + r = venc_init_platform_driver(); if (r) { - DSSERR("Failed to initialize venc\n"); + DSSERR("Failed to initialize venc platform driver\n"); goto err_venc; } @@ -279,7 +264,7 @@ err_dsi: if (cpu_is_omap34xx()) sdi_exit(); err_sdi: - venc_exit(); + venc_uninit_platform_driver(); err_venc: dispc_uninit_platform_driver(); err_dispc: @@ -300,7 +285,7 @@ static int omap_dss_remove(struct platform_device *pdev) dss_uninitialize_debugfs(); - venc_exit(); + venc_uninit_platform_driver(); dispc_uninit_platform_driver(); dpi_exit(); rfbi_uninit_platform_driver(); @@ -597,11 +582,6 @@ static void __exit omap_dss_exit(void) core.vdds_sdi_reg = NULL; } - if (core.vdda_dac_reg != NULL) { - regulator_put(core.vdda_dac_reg); - core.vdda_dac_reg = NULL; - } - platform_driver_unregister(&omap_dss_driver); omap_dss_bus_unregister(); diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h index f4835c85db90..931385185dc6 100644 --- a/drivers/video/omap2/dss/dss.h +++ b/drivers/video/omap2/dss/dss.h @@ -172,7 +172,6 @@ struct platform_device; struct bus_type *dss_get_bus(void); struct regulator *dss_get_vdds_dsi(void); struct regulator *dss_get_vdds_sdi(void); -struct regulator *dss_get_vdda_dac(void); /* display */ int dss_suspend_all_devices(void); @@ -412,16 +411,16 @@ int dispc_get_clock_div(enum omap_channel channel, /* VENC */ #ifdef CONFIG_OMAP2_DSS_VENC -int venc_init(struct platform_device *pdev); -void venc_exit(void); +int venc_init_platform_driver(void); +void venc_uninit_platform_driver(void); void venc_dump_regs(struct seq_file *s); int venc_init_display(struct omap_dss_device *display); #else -static inline int venc_init(struct platform_device *pdev) +static inline int venc_init_platform_driver(void) { return 0; } -static inline void venc_exit(void) +static inline void venc_uninit_platform_driver(void) { } #endif diff --git a/drivers/video/omap2/dss/venc.c b/drivers/video/omap2/dss/venc.c index eff35050e28a..765a4ac44ecd 100644 --- a/drivers/video/omap2/dss/venc.c +++ b/drivers/video/omap2/dss/venc.c @@ -289,6 +289,7 @@ const struct omap_video_timings omap_dss_ntsc_timings = { EXPORT_SYMBOL(omap_dss_ntsc_timings); static struct { + struct platform_device *pdev; void __iomem *base; struct mutex venc_lock; u32 wss_data; @@ -306,6 +307,17 @@ static inline u32 venc_read_reg(int idx) return l; } +static struct regulator *venc_get_vdda_dac(void) +{ + struct regulator *reg; + + reg = regulator_get(&venc.pdev->dev, "vdda_dac"); + if (!IS_ERR(reg)) + venc.vdda_dac_reg = reg; + + return reg; +} + static void venc_write_config(const struct venc_config *config) { DSSDBG("write venc conf\n"); @@ -641,46 +653,6 @@ static struct omap_dss_driver venc_driver = { }; /* driver end */ - - -int venc_init(struct platform_device *pdev) -{ - u8 rev_id; - - mutex_init(&venc.venc_lock); - - venc.wss_data = 0; - - venc.base = ioremap(VENC_BASE, SZ_1K); - if (!venc.base) { - DSSERR("can't ioremap VENC\n"); - return -ENOMEM; - } - - venc.vdda_dac_reg = dss_get_vdda_dac(); - if (IS_ERR(venc.vdda_dac_reg)) { - iounmap(venc.base); - DSSERR("can't get VDDA_DAC regulator\n"); - return PTR_ERR(venc.vdda_dac_reg); - } - - venc_enable_clocks(1); - - rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff); - printk(KERN_INFO "OMAP VENC rev %d\n", rev_id); - - venc_enable_clocks(0); - - return omap_dss_register_driver(&venc_driver); -} - -void venc_exit(void) -{ - omap_dss_unregister_driver(&venc_driver); - - iounmap(venc.base); -} - int venc_init_display(struct omap_dss_device *dssdev) { DSSDBG("init_display\n"); @@ -740,3 +712,67 @@ void venc_dump_regs(struct seq_file *s) #undef DUMPREG } + +/* VENC HW IP initialisation */ +static int omap_venchw_probe(struct platform_device *pdev) +{ + u8 rev_id; + venc.pdev = pdev; + + mutex_init(&venc.venc_lock); + + venc.wss_data = 0; + + venc.base = ioremap(VENC_BASE, SZ_1K); + if (!venc.base) { + DSSERR("can't ioremap VENC\n"); + return -ENOMEM; + } + + venc.vdda_dac_reg = venc_get_vdda_dac(); + if (IS_ERR(venc.vdda_dac_reg)) { + iounmap(venc.base); + DSSERR("can't get VDDA_DAC regulator\n"); + return PTR_ERR(venc.vdda_dac_reg); + } + + venc_enable_clocks(1); + + rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff); + printk(KERN_INFO "OMAP VENC rev %d\n", rev_id); + + venc_enable_clocks(0); + + return omap_dss_register_driver(&venc_driver); +} + +static int omap_venchw_remove(struct platform_device *pdev) +{ + if (venc.vdda_dac_reg != NULL) { + regulator_put(venc.vdda_dac_reg); + venc.vdda_dac_reg = NULL; + } + omap_dss_unregister_driver(&venc_driver); + + iounmap(venc.base); + return 0; +} + +static struct platform_driver omap_venchw_driver = { + .probe = omap_venchw_probe, + .remove = omap_venchw_remove, + .driver = { + .name = "omapdss_venc", + .owner = THIS_MODULE, + }, +}; + +int venc_init_platform_driver(void) +{ + return platform_driver_register(&omap_venchw_driver); +} + +void venc_uninit_platform_driver(void) +{ + return platform_driver_unregister(&omap_venchw_driver); +} From c8aac01b7bd1109795586db11ea7f12ab1e2d163 Mon Sep 17 00:00:00 2001 From: Senthilvadivu Guruswamy Date: Mon, 24 Jan 2011 06:22:02 +0000 Subject: [PATCH 009/140] OMAP2, 3: DSS2: DSI: create platform_driver, move init, exit to driver Hwmod adaptation design requires each of the DSS HW IP to be a platform driver. So a platform_driver for DSI is created and init exit methods are moved from core.c to its driver probe,remove. pdev member has to be maintained by its own drivers. Also, vdds_dsi regulator handling is copied to dsi.c, since vdds_dsi regulator is needed by dpi_init() too. Board files are updated accordingly to add 2 instances of vdds_dsi regulator. DSI platform driver is registered from inside omap_dss_probe, in the order desired. Signed-off-by: Senthilvadivu Guruswamy Signed-off-by: Sumit Semwal Signed-off-by: Tomi Valkeinen --- arch/arm/mach-omap2/board-3430sdp.c | 1 + arch/arm/mach-omap2/board-devkit8000.c | 10 +-- arch/arm/mach-omap2/board-igep0020.c | 10 +-- arch/arm/mach-omap2/board-omap3beagle.c | 10 +-- arch/arm/mach-omap2/board-omap3evm.c | 10 +-- arch/arm/mach-omap2/board-omap3pandora.c | 1 + arch/arm/mach-omap2/board-omap3stalker.c | 10 +-- arch/arm/mach-omap2/board-zoom-peripherals.c | 10 +-- drivers/video/omap2/dss/core.c | 8 +-- drivers/video/omap2/dss/dsi.c | 64 +++++++++++++++++++- drivers/video/omap2/dss/dss.h | 8 +-- 11 files changed, 107 insertions(+), 35 deletions(-) diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index 652e7c38c62e..75814ae4dd07 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c @@ -401,6 +401,7 @@ static struct regulator_consumer_supply sdp3430_vdda_dac_supplies[] = { /* VPLL2 for digital video outputs */ static struct regulator_consumer_supply sdp3430_vpll2_supplies[] = { REGULATOR_SUPPLY("vdds_dsi", "omapdss"), + REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), }; static struct regulator_consumer_supply sdp3430_vmmc1_supplies[] = { diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c index b64774b3d82c..e102e143afb1 100644 --- a/arch/arm/mach-omap2/board-devkit8000.c +++ b/arch/arm/mach-omap2/board-devkit8000.c @@ -277,8 +277,10 @@ static struct twl4030_gpio_platform_data devkit8000_gpio_data = { .setup = devkit8000_twl_gpio_setup, }; -static struct regulator_consumer_supply devkit8000_vpll1_supply = - REGULATOR_SUPPLY("vdds_dsi", "omapdss"); +static struct regulator_consumer_supply devkit8000_vpll1_supplies[] = { + REGULATOR_SUPPLY("vdds_dsi", "omapdss"), + REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), +}; /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ static struct regulator_init_data devkit8000_vmmc1 = { @@ -319,8 +321,8 @@ static struct regulator_init_data devkit8000_vpll1 = { .valid_ops_mask = REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, }, - .num_consumer_supplies = 1, - .consumer_supplies = &devkit8000_vpll1_supply, + .num_consumer_supplies = ARRAY_SIZE(devkit8000_vpll1_supplies), + .consumer_supplies = devkit8000_vpll1_supplies, }; /* VAUX4 for ads7846 and nubs */ diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index c4b3c1c47ec6..12b3e41b6f78 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -485,8 +485,10 @@ static struct omap_dss_board_info igep2_dss_data = { .default_device = &igep2_dvi_device, }; -static struct regulator_consumer_supply igep2_vpll2_supply = - REGULATOR_SUPPLY("vdds_dsi", "omapdss"); +static struct regulator_consumer_supply igep2_vpll2_supplies[] = { + REGULATOR_SUPPLY("vdds_dsi", "omapdss"), + REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), +}; static struct regulator_init_data igep2_vpll2 = { .constraints = { @@ -499,8 +501,8 @@ static struct regulator_init_data igep2_vpll2 = { .valid_ops_mask = REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, }, - .num_consumer_supplies = 1, - .consumer_supplies = &igep2_vpll2_supply, + .num_consumer_supplies = ARRAY_SIZE(igep2_vpll2_supplies), + .consumer_supplies = igep2_vpll2_supplies, }; static void __init igep2_display_init(void) diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 2fad38f9e683..e663c43fe039 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -234,8 +234,10 @@ static struct omap_dss_board_info beagle_dss_data = { static struct regulator_consumer_supply beagle_vdac_supply = REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"); -static struct regulator_consumer_supply beagle_vdvi_supply = - REGULATOR_SUPPLY("vdds_dsi", "omapdss"); +static struct regulator_consumer_supply beagle_vdvi_supplies[] = { + REGULATOR_SUPPLY("vdds_dsi", "omapdss"), + REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), +}; static void __init beagle_display_init(void) { @@ -422,8 +424,8 @@ static struct regulator_init_data beagle_vpll2 = { .valid_ops_mask = REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, }, - .num_consumer_supplies = 1, - .consumer_supplies = &beagle_vdvi_supply, + .num_consumer_supplies = ARRAY_SIZE(beagle_vdvi_supplies), + .consumer_supplies = beagle_vdvi_supplies, }; static struct twl4030_usb_data beagle_usb_data = { diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index a6564b41b97a..5800db31e561 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -560,8 +560,10 @@ static struct regulator_init_data omap3_evm_vdac = { }; /* VPLL2 for digital video outputs */ -static struct regulator_consumer_supply omap3_evm_vpll2_supply = - REGULATOR_SUPPLY("vdds_dsi", "omapdss"); +static struct regulator_consumer_supply omap3_evm_vpll2_supplies[] = { + REGULATOR_SUPPLY("vdds_dsi", "omapdss"), + REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), +}; static struct regulator_init_data omap3_evm_vpll2 = { .constraints = { @@ -573,8 +575,8 @@ static struct regulator_init_data omap3_evm_vpll2 = { .valid_ops_mask = REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, }, - .num_consumer_supplies = 1, - .consumer_supplies = &omap3_evm_vpll2_supply, + .num_consumer_supplies = ARRAY_SIZE(omap3_evm_vpll2_supplies), + .consumer_supplies = omap3_evm_vpll2_supplies, }; /* ads7846 on SPI */ diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c index 37de418edd2a..131a58dd3c96 100644 --- a/arch/arm/mach-omap2/board-omap3pandora.c +++ b/arch/arm/mach-omap2/board-omap3pandora.c @@ -347,6 +347,7 @@ static struct regulator_consumer_supply pandora_vdda_dac_supply = static struct regulator_consumer_supply pandora_vdds_supplies[] = { REGULATOR_SUPPLY("vdds_sdi", "omapdss"), REGULATOR_SUPPLY("vdds_dsi", "omapdss"), + REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), }; static struct regulator_consumer_supply pandora_vcc_lcd_supply = diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c index bd0eed858078..d1163a80f843 100644 --- a/arch/arm/mach-omap2/board-omap3stalker.c +++ b/arch/arm/mach-omap2/board-omap3stalker.c @@ -457,8 +457,10 @@ static struct regulator_init_data omap3_stalker_vdac = { }; /* VPLL2 for digital video outputs */ -static struct regulator_consumer_supply omap3_stalker_vpll2_supply = - REGULATOR_SUPPLY("vdds_dsi", "omapdss"); +static struct regulator_consumer_supply omap3_stalker_vpll2_supplies[] = { + REGULATOR_SUPPLY("vdds_dsi", "omapdss"), + REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), +}; static struct regulator_init_data omap3_stalker_vpll2 = { .constraints = { @@ -471,8 +473,8 @@ static struct regulator_init_data omap3_stalker_vpll2 = { .valid_ops_mask = REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, }, - .num_consumer_supplies = 1, - .consumer_supplies = &omap3_stalker_vpll2_supply, + .num_consumer_supplies = ARRAY_SIZE(omap3_stalker_vpll2_supplies), + .consumer_supplies = omap3_stalker_vpll2_supplies, }; static struct twl4030_platform_data omap3stalker_twldata = { diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c index 405400c4762b..8dee7549fbdf 100644 --- a/arch/arm/mach-omap2/board-zoom-peripherals.c +++ b/arch/arm/mach-omap2/board-zoom-peripherals.c @@ -226,8 +226,10 @@ static struct omap2_hsmmc_info mmc[] = { {} /* Terminator */ }; -static struct regulator_consumer_supply zoom_vpll2_supply = - REGULATOR_SUPPLY("vdds_dsi", "omapdss"); +static struct regulator_consumer_supply zoom_vpll2_supplies[] = { + REGULATOR_SUPPLY("vdds_dsi", "omapdss"), + REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), +}; static struct regulator_consumer_supply zoom_vdda_dac_supply = REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"); @@ -241,8 +243,8 @@ static struct regulator_init_data zoom_vpll2 = { .valid_ops_mask = REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, }, - .num_consumer_supplies = 1, - .consumer_supplies = &zoom_vpll2_supply, + .num_consumer_supplies = ARRAY_SIZE(zoom_vpll2_supplies), + .consumer_supplies = zoom_vpll2_supplies, }; static struct regulator_init_data zoom_vdac = { diff --git a/drivers/video/omap2/dss/core.c b/drivers/video/omap2/dss/core.c index 57c6303cb1cd..3f7a5fcd1142 100644 --- a/drivers/video/omap2/dss/core.c +++ b/drivers/video/omap2/dss/core.c @@ -222,9 +222,9 @@ static int omap_dss_probe(struct platform_device *pdev) goto err_sdi; } - r = dsi_init(pdev); + r = dsi_init_platform_driver(); if (r) { - DSSERR("Failed to initialize DSI\n"); + DSSERR("Failed to initialize DSI platform driver\n"); goto err_dsi; } } @@ -259,7 +259,7 @@ err_register: dss_uninitialize_debugfs(); err_debugfs: if (cpu_is_omap34xx()) - dsi_exit(); + dsi_uninit_platform_driver(); err_dsi: if (cpu_is_omap34xx()) sdi_exit(); @@ -290,7 +290,7 @@ static int omap_dss_remove(struct platform_device *pdev) dpi_exit(); rfbi_uninit_platform_driver(); if (cpu_is_omap34xx()) { - dsi_exit(); + dsi_uninit_platform_driver(); sdi_exit(); } diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c index ddf3a0560822..fa85f1adba2a 100644 --- a/drivers/video/omap2/dss/dsi.c +++ b/drivers/video/omap2/dss/dsi.c @@ -222,6 +222,7 @@ struct dsi_irq_stats { static struct { + struct platform_device *pdev; void __iomem *base; struct dsi_clock_info current_cinfo; @@ -292,6 +293,20 @@ static inline u32 dsi_read_reg(const struct dsi_reg idx) return __raw_readl(dsi.base + idx.idx); } +static struct regulator *dsi_get_vdds_dsi(void) +{ + struct regulator *reg; + + if (dsi.vdds_dsi_reg != NULL) + return dsi.vdds_dsi_reg; + + reg = regulator_get(&dsi.pdev->dev, "vdds_dsi"); + if (!IS_ERR(reg)) + dsi.vdds_dsi_reg = reg; + + return reg; +} + void dsi_save_context(void) { @@ -3238,7 +3253,7 @@ void dsi_wait_dsi2_pll_active(void) DSSERR("DSI2 PLL clock not active\n"); } -int dsi_init(struct platform_device *pdev) +static int dsi_init(struct platform_device *pdev) { u32 rev; int r; @@ -3275,7 +3290,7 @@ int dsi_init(struct platform_device *pdev) goto err1; } - dsi.vdds_dsi_reg = dss_get_vdds_dsi(); + dsi.vdds_dsi_reg = dsi_get_vdds_dsi(); if (IS_ERR(dsi.vdds_dsi_reg)) { DSSERR("can't get VDDS_DSI regulator\n"); r = PTR_ERR(dsi.vdds_dsi_reg); @@ -3298,8 +3313,13 @@ err1: return r; } -void dsi_exit(void) +static void dsi_exit(void) { + if (dsi.vdds_dsi_reg != NULL) { + regulator_put(dsi.vdds_dsi_reg); + dsi.vdds_dsi_reg = NULL; + } + iounmap(dsi.base); destroy_workqueue(dsi.workqueue); @@ -3307,3 +3327,41 @@ void dsi_exit(void) DSSDBG("omap_dsi_exit\n"); } +/* DSI1 HW IP initialisation */ +static int omap_dsi1hw_probe(struct platform_device *pdev) +{ + int r; + dsi.pdev = pdev; + r = dsi_init(pdev); + if (r) { + DSSERR("Failed to initialize DSI\n"); + goto err_dsi; + } +err_dsi: + return r; +} + +static int omap_dsi1hw_remove(struct platform_device *pdev) +{ + dsi_exit(); + return 0; +} + +static struct platform_driver omap_dsi1hw_driver = { + .probe = omap_dsi1hw_probe, + .remove = omap_dsi1hw_remove, + .driver = { + .name = "omapdss_dsi1", + .owner = THIS_MODULE, + }, +}; + +int dsi_init_platform_driver(void) +{ + return platform_driver_register(&omap_dsi1hw_driver); +} + +void dsi_uninit_platform_driver(void) +{ + return platform_driver_unregister(&omap_dsi1hw_driver); +} diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h index 931385185dc6..981d247c30f2 100644 --- a/drivers/video/omap2/dss/dss.h +++ b/drivers/video/omap2/dss/dss.h @@ -261,8 +261,8 @@ static inline void sdi_exit(void) /* DSI */ #ifdef CONFIG_OMAP2_DSS_DSI -int dsi_init(struct platform_device *pdev); -void dsi_exit(void); +int dsi_init_platform_driver(void); +void dsi_uninit_platform_driver(void); void dsi_dump_clocks(struct seq_file *s); void dsi_dump_irqs(struct seq_file *s); @@ -287,11 +287,11 @@ void dsi_get_overlay_fifo_thresholds(enum omap_plane plane, void dsi_wait_dsi1_pll_active(void); void dsi_wait_dsi2_pll_active(void); #else -static inline int dsi_init(struct platform_device *pdev) +static inline int dsi_init_platform_driver(void) { return 0; } -static inline void dsi_exit(void) +static inline void dsi_uninit_platform_driver(void) { } static inline void dsi_wait_dsi1_pll_active(void) From a06b62f8004bd95c132fa312e8593c9a10f466ec Mon Sep 17 00:00:00 2001 From: Sumit Semwal Date: Mon, 24 Jan 2011 06:22:03 +0000 Subject: [PATCH 010/140] OMAP2,3: DSS2: replace printk with dev_dbg in init This patch replaces printk's in the init/probe functions to dev_dbg for boot time optimization. Reviewed-by: Kevin Hilman Tested-by: Kevin Hilman Signed-off-by: Sumit Semwal Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dispc.c | 2 +- drivers/video/omap2/dss/dsi.c | 2 +- drivers/video/omap2/dss/rfbi.c | 2 +- drivers/video/omap2/dss/venc.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c index 28ad68b6be48..032e5dd19e09 100644 --- a/drivers/video/omap2/dss/dispc.c +++ b/drivers/video/omap2/dss/dispc.c @@ -3350,7 +3350,7 @@ static int omap_dispchw_probe(struct platform_device *pdev) dispc_save_context(); rev = dispc_read_reg(DISPC_REVISION); - printk(KERN_INFO "OMAP DISPC rev %d.%d\n", + dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n", FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); enable_clocks(0); diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c index fa85f1adba2a..df246033b940 100644 --- a/drivers/video/omap2/dss/dsi.c +++ b/drivers/video/omap2/dss/dsi.c @@ -3300,7 +3300,7 @@ static int dsi_init(struct platform_device *pdev) enable_clocks(1); rev = dsi_read_reg(DSI_REVISION); - printk(KERN_INFO "OMAP DSI rev %d.%d\n", + dev_dbg(&pdev->dev, "OMAP DSI rev %d.%d\n", FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); enable_clocks(0); diff --git a/drivers/video/omap2/dss/rfbi.c b/drivers/video/omap2/dss/rfbi.c index 153f963e8e89..5f186484984f 100644 --- a/drivers/video/omap2/dss/rfbi.c +++ b/drivers/video/omap2/dss/rfbi.c @@ -1046,7 +1046,7 @@ static int omap_rfbihw_probe(struct platform_device *pdev) rfbi_write_reg(RFBI_SYSCONFIG, l); rev = rfbi_read_reg(RFBI_REVISION); - printk(KERN_INFO "OMAP RFBI rev %d.%d\n", + dev_dbg(&pdev->dev, "OMAP RFBI rev %d.%d\n", FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); rfbi_enable_clocks(0); diff --git a/drivers/video/omap2/dss/venc.c b/drivers/video/omap2/dss/venc.c index 765a4ac44ecd..4a02f8eeb0d8 100644 --- a/drivers/video/omap2/dss/venc.c +++ b/drivers/video/omap2/dss/venc.c @@ -739,7 +739,7 @@ static int omap_venchw_probe(struct platform_device *pdev) venc_enable_clocks(1); rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff); - printk(KERN_INFO "OMAP VENC rev %d\n", rev_id); + dev_dbg(&pdev->dev, "OMAP VENC rev %d\n", rev_id); venc_enable_clocks(0); From ea9da36a304eed585fc5ef89c0f1c460eca61b48 Mon Sep 17 00:00:00 2001 From: Senthilvadivu Guruswamy Date: Mon, 24 Jan 2011 06:22:04 +0000 Subject: [PATCH 011/140] OMAP2,3: DSS2: Use platform device to get baseaddr DSS, DISPC, DSI, RFBI, VENC baseaddr can be obtained from platform_get_resource(). This API in turn picks the right silicon baseaddr from the hwmod database. So hardcoding of base addr could be removed. Reviewed-by: Paul Walmsley Reviewed-by: Kevin Hilman Tested-by: Kevin Hilman Signed-off-by: Sumit Semwal Signed-off-by: Senthilvadivu Guruswamy Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dispc.c | 11 ++++++++--- drivers/video/omap2/dss/dsi.c | 11 ++++++++--- drivers/video/omap2/dss/dss.c | 11 ++++++++--- drivers/video/omap2/dss/rfbi.c | 10 +++++++--- drivers/video/omap2/dss/venc.c | 11 ++++++++--- 5 files changed, 39 insertions(+), 15 deletions(-) diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c index 032e5dd19e09..96e37f8e75dc 100644 --- a/drivers/video/omap2/dss/dispc.c +++ b/drivers/video/omap2/dss/dispc.c @@ -42,8 +42,6 @@ #include "dss_features.h" /* DISPC */ -#define DISPC_BASE 0x48050400 - #define DISPC_SZ_REGS SZ_4K struct dispc_reg { u16 idx; }; @@ -3324,6 +3322,8 @@ int dispc_setup_plane(enum omap_plane plane, static int omap_dispchw_probe(struct platform_device *pdev) { u32 rev; + struct resource *dispc_mem; + dispc.pdev = pdev; spin_lock_init(&dispc.irq_lock); @@ -3335,7 +3335,12 @@ static int omap_dispchw_probe(struct platform_device *pdev) INIT_WORK(&dispc.error_work, dispc_error_worker); - dispc.base = ioremap(DISPC_BASE, DISPC_SZ_REGS); + dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0); + if (!dispc_mem) { + DSSERR("can't get IORESOURCE_MEM DISPC\n"); + return -EINVAL; + } + dispc.base = ioremap(dispc_mem->start, resource_size(dispc_mem)); if (!dispc.base) { DSSERR("can't ioremap DISPC\n"); return -ENOMEM; diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c index df246033b940..c42acae10af0 100644 --- a/drivers/video/omap2/dss/dsi.c +++ b/drivers/video/omap2/dss/dsi.c @@ -42,8 +42,6 @@ /*#define VERBOSE_IRQ*/ #define DSI_CATCH_MISSING_TE -#define DSI_BASE 0x4804FC00 - struct dsi_reg { u16 idx; }; #define DSI_REG(idx) ((const struct dsi_reg) { idx }) @@ -3257,6 +3255,7 @@ static int dsi_init(struct platform_device *pdev) { u32 rev; int r; + struct resource *dsi_mem; spin_lock_init(&dsi.errors_lock); dsi.errors = 0; @@ -3283,7 +3282,13 @@ static int dsi_init(struct platform_device *pdev) dsi.te_timer.function = dsi_te_timeout; dsi.te_timer.data = 0; #endif - dsi.base = ioremap(DSI_BASE, DSI_SZ_REGS); + dsi_mem = platform_get_resource(dsi.pdev, IORESOURCE_MEM, 0); + if (!dsi_mem) { + DSSERR("can't get IORESOURCE_MEM DSI\n"); + r = -EINVAL; + goto err1; + } + dsi.base = ioremap(dsi_mem->start, resource_size(dsi_mem)); if (!dsi.base) { DSSERR("can't ioremap DSI\n"); r = -ENOMEM; diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c index 72b395d69aae..ee9ce4af58b5 100644 --- a/drivers/video/omap2/dss/dss.c +++ b/drivers/video/omap2/dss/dss.c @@ -34,8 +34,6 @@ #include #include "dss.h" -#define DSS_BASE 0x48050000 - #define DSS_SZ_REGS SZ_512 struct dss_reg { @@ -567,8 +565,15 @@ static int dss_init(bool skip_init) { int r; u32 rev; + struct resource *dss_mem; - dss.base = ioremap(DSS_BASE, DSS_SZ_REGS); + dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0); + if (!dss_mem) { + DSSERR("can't get IORESOURCE_MEM DSS\n"); + r = -EINVAL; + goto fail0; + } + dss.base = ioremap(dss_mem->start, resource_size(dss_mem)); if (!dss.base) { DSSERR("can't ioremap DSS\n"); r = -ENOMEM; diff --git a/drivers/video/omap2/dss/rfbi.c b/drivers/video/omap2/dss/rfbi.c index 5f186484984f..6dbb95d557f8 100644 --- a/drivers/video/omap2/dss/rfbi.c +++ b/drivers/video/omap2/dss/rfbi.c @@ -36,8 +36,6 @@ #include #include "dss.h" -#define RFBI_BASE 0x48050800 - struct rfbi_reg { u16 idx; }; #define RFBI_REG(idx) ((const struct rfbi_reg) { idx }) @@ -1019,6 +1017,7 @@ static int omap_rfbihw_probe(struct platform_device *pdev) { u32 rev; u32 l; + struct resource *rfbi_mem; rfbi.pdev = pdev; @@ -1028,7 +1027,12 @@ static int omap_rfbihw_probe(struct platform_device *pdev) atomic_set(&rfbi.cmd_fifo_full, 0); atomic_set(&rfbi.cmd_pending, 0); - rfbi.base = ioremap(RFBI_BASE, SZ_256); + rfbi_mem = platform_get_resource(rfbi.pdev, IORESOURCE_MEM, 0); + if (!rfbi_mem) { + DSSERR("can't get IORESOURCE_MEM RFBI\n"); + return -EINVAL; + } + rfbi.base = ioremap(rfbi_mem->start, resource_size(rfbi_mem)); if (!rfbi.base) { DSSERR("can't ioremap RFBI\n"); return -ENOMEM; diff --git a/drivers/video/omap2/dss/venc.c b/drivers/video/omap2/dss/venc.c index 4a02f8eeb0d8..ef36811f6ac8 100644 --- a/drivers/video/omap2/dss/venc.c +++ b/drivers/video/omap2/dss/venc.c @@ -39,8 +39,6 @@ #include "dss.h" -#define VENC_BASE 0x48050C00 - /* Venc registers */ #define VENC_REV_ID 0x00 #define VENC_STATUS 0x04 @@ -717,13 +715,20 @@ void venc_dump_regs(struct seq_file *s) static int omap_venchw_probe(struct platform_device *pdev) { u8 rev_id; + struct resource *venc_mem; + venc.pdev = pdev; mutex_init(&venc.venc_lock); venc.wss_data = 0; - venc.base = ioremap(VENC_BASE, SZ_1K); + venc_mem = platform_get_resource(venc.pdev, IORESOURCE_MEM, 0); + if (!venc_mem) { + DSSERR("can't get IORESOURCE_MEM VENC\n"); + return -EINVAL; + } + venc.base = ioremap(venc_mem->start, resource_size(venc_mem)); if (!venc.base) { DSSERR("can't ioremap VENC\n"); return -ENOMEM; From ef631f82500390b3dfc20b16214e53c443d675a4 Mon Sep 17 00:00:00 2001 From: Senthilvadivu Guruswamy Date: Tue, 15 Feb 2011 23:14:00 -0600 Subject: [PATCH 012/140] OMAP2,3: DSS2: Get DSS IRQ from platform device DSS IRQ number can be obtained from platform_get_irq(). This API in turn picks the right IRQ number belonging to HW IP from the hwmod database. So hardcoding of IRQ number could be removed. This IRQ is stored in dss_irq as part of dss structure, and freed it in dss_exit(). Reviewed-by: Paul Walmsley Reviewed-by: Kevin Hilman Tested-by: Kevin Hilman Signed-off-by: Senthilvadivu Guruswamy Signed-off-by: Sumit Semwal Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dss.c | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c index ee9ce4af58b5..a00733d6436a 100644 --- a/drivers/video/omap2/dss/dss.c +++ b/drivers/video/omap2/dss/dss.c @@ -79,6 +79,7 @@ static struct { enum dss_clk_source dispc_clk_source; u32 ctx[DSS_SZ_REGS / sizeof(u32)]; + int dss_irq; } dss; static void dss_clk_enable_all_no_ctx(void); @@ -609,11 +610,18 @@ static int dss_init(bool skip_init) REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */ #endif - r = request_irq(INT_24XX_DSS_IRQ, - cpu_is_omap24xx() - ? dss_irq_handler_omap2 - : dss_irq_handler_omap3, - 0, "OMAP DSS", NULL); + dss.dss_irq = platform_get_irq(dss.pdev, 0); + if (dss.dss_irq < 0) { + DSSERR("omap2 dss: platform_get_irq failed\n"); + r = -ENODEV; + goto fail1; + } + + r = request_irq(dss.dss_irq, + cpu_is_omap24xx() + ? dss_irq_handler_omap2 + : dss_irq_handler_omap3, + 0, "OMAP DSS", NULL); if (r < 0) { DSSERR("omap2 dss: request_irq failed\n"); @@ -641,7 +649,7 @@ static int dss_init(bool skip_init) return 0; fail2: - free_irq(INT_24XX_DSS_IRQ, NULL); + free_irq(dss.dss_irq, NULL); fail1: iounmap(dss.base); fail0: @@ -653,7 +661,7 @@ static void dss_exit(void) if (cpu_is_omap34xx()) clk_put(dss.dpll4_m4_ck); - free_irq(INT_24XX_DSS_IRQ, NULL); + free_irq(dss.dss_irq, NULL); iounmap(dss.base); } From 872462cdfc74e7b93c09870128d9bb436d4e9804 Mon Sep 17 00:00:00 2001 From: Sumit Semwal Date: Mon, 31 Jan 2011 16:27:43 +0000 Subject: [PATCH 013/140] OMAP2PLUS: clocks: Align DSS clock names and roles Currently, clock database has tuples for DSS2. Because of this, the clock names are different across different OMAP platforms. This patch aligns the DSS2 clock names and roles across OMAP 2420, 2430, 3xxx, 44xx platforms in the clock databases, hwmod databases for opt-clocks, and DSS clock handling. This ensures that clk_get/put/enable/disable APIs in DSS can use uniform role names. Signed-off-by: Sumit Semwal Acked-by: Paul Walmsley Signed-off-by: Tomi Valkeinen --- arch/arm/mach-omap2/clock2420_data.c | 6 +++--- arch/arm/mach-omap2/clock2430_data.c | 6 +++--- arch/arm/mach-omap2/clock3xxx_data.c | 10 +++++----- arch/arm/mach-omap2/clock44xx_data.c | 10 +++++----- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 2 +- drivers/video/omap2/dss/dss.c | 8 ++++---- 6 files changed, 21 insertions(+), 21 deletions(-) diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c index 9ece62a44a3f..26d89d5827c8 100644 --- a/arch/arm/mach-omap2/clock2420_data.c +++ b/arch/arm/mach-omap2/clock2420_data.c @@ -1787,9 +1787,9 @@ static struct omap_clk omap2420_clks[] = { CLK(NULL, "gfx_ick", &gfx_ick, CK_242X), /* DSS domain clocks */ CLK("omapdss_dss", "ick", &dss_ick, CK_242X), - CLK("omapdss_dss", "dss1_fck", &dss1_fck, CK_242X), - CLK("omapdss_dss", "dss2_fck", &dss2_fck, CK_242X), - CLK("omapdss_dss", "tv_fck", &dss_54m_fck, CK_242X), + CLK("omapdss_dss", "fck", &dss1_fck, CK_242X), + CLK("omapdss_dss", "sys_clk", &dss2_fck, CK_242X), + CLK("omapdss_dss", "tv_clk", &dss_54m_fck, CK_242X), /* L3 domain clocks */ CLK(NULL, "core_l3_ck", &core_l3_ck, CK_242X), CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_242X), diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c index 61006ae7eac4..0bfe4872b02b 100644 --- a/arch/arm/mach-omap2/clock2430_data.c +++ b/arch/arm/mach-omap2/clock2430_data.c @@ -1891,9 +1891,9 @@ static struct omap_clk omap2430_clks[] = { CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X), /* DSS domain clocks */ CLK("omapdss_dss", "ick", &dss_ick, CK_243X), - CLK("omapdss_dss", "dss1_fck", &dss1_fck, CK_243X), - CLK("omapdss_dss", "dss2_fck", &dss2_fck, CK_243X), - CLK("omapdss_dss", "tv_fck", &dss_54m_fck, CK_243X), + CLK("omapdss_dss", "fck", &dss1_fck, CK_243X), + CLK("omapdss_dss", "sys_clk", &dss2_fck, CK_243X), + CLK("omapdss_dss", "tv_clk", &dss_54m_fck, CK_243X), /* L3 domain clocks */ CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X), CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X), diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index 2e47d16fce77..427f6c8d1585 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -3357,11 +3357,11 @@ static struct omap_clk omap3xxx_clks[] = { CLK("omap_rng", "ick", &rng_ick, CK_34XX | CK_36XX), CLK(NULL, "sha11_ick", &sha11_ick, CK_34XX | CK_36XX), CLK(NULL, "des1_ick", &des1_ick, CK_34XX | CK_36XX), - CLK("omapdss_dss", "dss1_fck", &dss1_alwon_fck_3430es1, CK_3430ES1), - CLK("omapdss_dss", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK("omapdss_dss", "tv_fck", &dss_tv_fck, CK_3XXX), - CLK("omapdss_dss", "video_fck", &dss_96m_fck, CK_3XXX), - CLK("omapdss_dss", "dss2_fck", &dss2_alwon_fck, CK_3XXX), + CLK("omapdss_dss", "fck", &dss1_alwon_fck_3430es1, CK_3430ES1), + CLK("omapdss_dss", "fck", &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK("omapdss_dss", "tv_clk", &dss_tv_fck, CK_3XXX), + CLK("omapdss_dss", "video_clk", &dss_96m_fck, CK_3XXX), + CLK("omapdss_dss", "sys_clk", &dss2_alwon_fck, CK_3XXX), CLK("omapdss_dss", "ick", &dss_ick_3430es1, CK_3430ES1), CLK("omapdss_dss", "ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK(NULL, "cam_mclk", &cam_mclk, CK_34XX | CK_36XX), diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index fdbc0426b6f4..6ba69b1158e6 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -3106,11 +3106,11 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), CLK(NULL, "dmic_fck", &dmic_fck, CK_443X), CLK(NULL, "dsp_fck", &dsp_fck, CK_443X), - CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X), - CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X), - CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X), - CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X), - CLK(NULL, "dss_fck", &dss_fck, CK_443X), + CLK("omapdss_dss", "sys_clk", &dss_sys_clk, CK_443X), + CLK("omapdss_dss", "tv_clk", &dss_tv_clk, CK_443X), + CLK("omapdss_dss", "dss_clk", &dss_dss_clk, CK_443X), + CLK("omapdss_dss", "video_clk", &dss_48mhz_clk, CK_443X), + CLK("omapdss_dss", "fck", &dss_fck, CK_443X), CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X), CLK(NULL, "emif1_fck", &emif1_fck, CK_443X), CLK(NULL, "emif2_fck", &emif2_fck, CK_443X), diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index c4ca005f8bb5..4ed48cab06fe 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -1571,7 +1571,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = { static struct omap_hwmod_opt_clk dss_opt_clks[] = { { .role = "tv_clk", .clk = "dss_tv_fck" }, - { .role = "dssclk", .clk = "dss_96m_fck" }, + { .role = "video_clk", .clk = "dss_96m_fck" }, { .role = "sys_clk", .clk = "dss2_alwon_fck" }, }; diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c index a00733d6436a..56d37bfefd4d 100644 --- a/drivers/video/omap2/dss/dss.c +++ b/drivers/video/omap2/dss/dss.c @@ -759,19 +759,19 @@ static int dss_get_clocks(void) if (r) goto err; - r = dss_get_clock(&dss.dss1_fck, "dss1_fck"); + r = dss_get_clock(&dss.dss1_fck, "fck"); if (r) goto err; - r = dss_get_clock(&dss.dss2_fck, "dss2_fck"); + r = dss_get_clock(&dss.dss2_fck, "sys_clk"); if (r) goto err; - r = dss_get_clock(&dss.dss_54m_fck, "tv_fck"); + r = dss_get_clock(&dss.dss_54m_fck, "tv_clk"); if (r) goto err; - r = dss_get_clock(&dss.dss_96m_fck, "video_fck"); + r = dss_get_clock(&dss.dss_96m_fck, "video_clk"); if (r) goto err; From 6af9cd1431db952a7f9f8931497c9989a48b07df Mon Sep 17 00:00:00 2001 From: Archit Taneja Date: Mon, 31 Jan 2011 16:27:44 +0000 Subject: [PATCH 014/140] OMAP2PLUS: DSS2: Generalize naming of PRCM related clock enums in DSS driver enum dss_clock structure is replaced with generic names that could be used across OMAP2420, 2430, 3xxx, 44xx platforms. Signed-off-by: Sumit Semwal Signed-off-by: Archit Taneja Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/core.c | 4 +- drivers/video/omap2/dss/dispc.c | 10 ++--- drivers/video/omap2/dss/dpi.c | 16 ++++---- drivers/video/omap2/dss/dsi.c | 18 ++++----- drivers/video/omap2/dss/dss.c | 62 +++++++++++++++---------------- drivers/video/omap2/dss/dss.h | 10 ++--- drivers/video/omap2/dss/manager.c | 4 +- drivers/video/omap2/dss/overlay.c | 4 +- drivers/video/omap2/dss/rfbi.c | 10 ++--- drivers/video/omap2/dss/sdi.c | 8 ++-- drivers/video/omap2/dss/venc.c | 8 ++-- 11 files changed, 77 insertions(+), 77 deletions(-) diff --git a/drivers/video/omap2/dss/core.c b/drivers/video/omap2/dss/core.c index 3f7a5fcd1142..f56ee64f5b58 100644 --- a/drivers/video/omap2/dss/core.c +++ b/drivers/video/omap2/dss/core.c @@ -184,7 +184,7 @@ static int omap_dss_probe(struct platform_device *pdev) } /* keep clocks enabled to prevent context saves/restores during init */ - dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); + dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); r = rfbi_init_platform_driver(); if (r) { @@ -251,7 +251,7 @@ static int omap_dss_probe(struct platform_device *pdev) pdata->default_device = dssdev; } - dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); + dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); return 0; diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c index 96e37f8e75dc..dc4518c4b0e4 100644 --- a/drivers/video/omap2/dss/dispc.c +++ b/drivers/video/omap2/dss/dispc.c @@ -551,9 +551,9 @@ void dispc_restore_context(void) static inline void enable_clocks(bool enable) { if (enable) - dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); + dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); else - dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); + dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); } bool dispc_go_busy(enum omap_channel channel) @@ -2311,7 +2311,7 @@ unsigned long dispc_fclk_rate(void) unsigned long r = 0; if (dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK) - r = dss_clk_get_rate(DSS_CLK_FCK1); + r = dss_clk_get_rate(DSS_CLK_FCK); else #ifdef CONFIG_OMAP2_DSS_DSI r = dsi_get_dsi1_pll_rate(); @@ -2439,7 +2439,7 @@ void dispc_dump_regs(struct seq_file *s) { #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dispc_read_reg(r)) - dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); + dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); DUMPREG(DISPC_REVISION); DUMPREG(DISPC_SYSCONFIG); @@ -2596,7 +2596,7 @@ void dispc_dump_regs(struct seq_file *s) DUMPREG(DISPC_VID_PRELOAD(0)); DUMPREG(DISPC_VID_PRELOAD(1)); - dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); + dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); #undef DUMPREG } diff --git a/drivers/video/omap2/dss/dpi.c b/drivers/video/omap2/dss/dpi.c index 75fb0a515430..746f1b6dd897 100644 --- a/drivers/video/omap2/dss/dpi.c +++ b/drivers/video/omap2/dss/dpi.c @@ -107,7 +107,7 @@ static int dpi_set_mode(struct omap_dss_device *dssdev) bool is_tft; int r = 0; - dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); + dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); dispc_set_pol_freq(dssdev->manager->id, dssdev->panel.config, dssdev->panel.acbi, dssdev->panel.acb); @@ -137,7 +137,7 @@ static int dpi_set_mode(struct omap_dss_device *dssdev) dispc_set_lcd_timings(dssdev->manager->id, t); err0: - dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); + dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); return r; } @@ -173,14 +173,14 @@ int omapdss_dpi_display_enable(struct omap_dss_device *dssdev) goto err1; } - dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); + dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); r = dpi_basic_init(dssdev); if (r) goto err2; #ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL - dss_clk_enable(DSS_CLK_FCK2); + dss_clk_enable(DSS_CLK_SYSCK); r = dsi_pll_init(dssdev, 0, 1); if (r) goto err3; @@ -199,10 +199,10 @@ err4: #ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL dsi_pll_uninit(); err3: - dss_clk_disable(DSS_CLK_FCK2); + dss_clk_disable(DSS_CLK_SYSCK); #endif err2: - dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); + dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); if (cpu_is_omap34xx()) regulator_disable(dpi.vdds_dsi_reg); err1: @@ -219,10 +219,10 @@ void omapdss_dpi_display_disable(struct omap_dss_device *dssdev) #ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK); dsi_pll_uninit(); - dss_clk_disable(DSS_CLK_FCK2); + dss_clk_disable(DSS_CLK_SYSCK); #endif - dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); + dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); if (cpu_is_omap34xx()) regulator_disable(dpi.vdds_dsi_reg); diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c index c42acae10af0..c7b5382e1a6b 100644 --- a/drivers/video/omap2/dss/dsi.c +++ b/drivers/video/omap2/dss/dsi.c @@ -654,18 +654,18 @@ static void dsi_vc_disable_bta_irq(int channel) static inline void enable_clocks(bool enable) { if (enable) - dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); + dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); else - dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); + dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); } /* source clock for DSI PLL. this could also be PCLKFREE */ static inline void dsi_enable_pll_clock(bool enable) { if (enable) - dss_clk_enable(DSS_CLK_FCK2); + dss_clk_enable(DSS_CLK_SYSCK); else - dss_clk_disable(DSS_CLK_FCK2); + dss_clk_disable(DSS_CLK_SYSCK); if (enable && dsi.pll_locked) { if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1) @@ -741,7 +741,7 @@ static unsigned long dsi_fclk_rate(void) if (dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK) { /* DSI FCLK source is DSS1_ALWON_FCK, which is dss1_fck */ - r = dss_clk_get_rate(DSS_CLK_FCK1); + r = dss_clk_get_rate(DSS_CLK_FCK); } else { /* DSI FCLK source is DSI2_PLL_FCLK */ r = dsi_get_dsi2_pll_rate(); @@ -821,7 +821,7 @@ static int dsi_calc_clock_rates(struct omap_dss_device *dssdev, return -EINVAL; if (cinfo->use_dss2_fck) { - cinfo->clkin = dss_clk_get_rate(DSS_CLK_FCK2); + cinfo->clkin = dss_clk_get_rate(DSS_CLK_SYSCK); /* XXX it is unclear if highfreq should be used * with DSS2_FCK source also */ cinfo->highfreq = 0; @@ -867,7 +867,7 @@ int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck, int match = 0; unsigned long dss_clk_fck2; - dss_clk_fck2 = dss_clk_get_rate(DSS_CLK_FCK2); + dss_clk_fck2 = dss_clk_get_rate(DSS_CLK_SYSCK); if (req_pck == dsi.cache_req_pck && dsi.cache_cinfo.clkin == dss_clk_fck2) { @@ -1319,7 +1319,7 @@ void dsi_dump_regs(struct seq_file *s) { #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(r)) - dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); + dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); DUMPREG(DSI_REVISION); DUMPREG(DSI_SYSCONFIG); @@ -1391,7 +1391,7 @@ void dsi_dump_regs(struct seq_file *s) DUMPREG(DSI_PLL_CONFIGURATION1); DUMPREG(DSI_PLL_CONFIGURATION2); - dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); + dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); #undef DUMPREG } diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c index 56d37bfefd4d..0372befbb692 100644 --- a/drivers/video/omap2/dss/dss.c +++ b/drivers/video/omap2/dss/dss.c @@ -227,7 +227,7 @@ void dss_dump_clocks(struct seq_file *s) unsigned long dpll4_ck_rate; unsigned long dpll4_m4_ck_rate; - dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); + dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); dpll4_ck_rate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); dpll4_m4_ck_rate = clk_get_rate(dss.dpll4_m4_ck); @@ -240,21 +240,21 @@ void dss_dump_clocks(struct seq_file *s) seq_printf(s, "dss1_alwon_fclk = %lu / %lu = %lu\n", dpll4_ck_rate, dpll4_ck_rate / dpll4_m4_ck_rate, - dss_clk_get_rate(DSS_CLK_FCK1)); + dss_clk_get_rate(DSS_CLK_FCK)); else seq_printf(s, "dss1_alwon_fclk = %lu / %lu * 2 = %lu\n", dpll4_ck_rate, dpll4_ck_rate / dpll4_m4_ck_rate, - dss_clk_get_rate(DSS_CLK_FCK1)); + dss_clk_get_rate(DSS_CLK_FCK)); - dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); + dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); } void dss_dump_regs(struct seq_file *s) { #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r)) - dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); + dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); DUMPREG(DSS_REVISION); DUMPREG(DSS_SYSCONFIG); @@ -265,7 +265,7 @@ void dss_dump_regs(struct seq_file *s) DUMPREG(DSS_PLL_CONTROL); DUMPREG(DSS_SDI_STATUS); - dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); + dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); #undef DUMPREG } @@ -350,7 +350,7 @@ int dss_set_clock_div(struct dss_clock_info *cinfo) int dss_get_clock_div(struct dss_clock_info *cinfo) { - cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK1); + cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK); if (cpu_is_omap34xx()) { unsigned long prate; @@ -391,7 +391,7 @@ int dss_calc_clock_div(bool is_tft, unsigned long req_pck, prate = dss_get_dpll4_rate(); - fck = dss_clk_get_rate(DSS_CLK_FCK1); + fck = dss_clk_get_rate(DSS_CLK_FCK); if (req_pck == dss.cache_req_pck && ((cpu_is_omap34xx() && prate == dss.cache_prate) || dss.cache_dss_cinfo.fck == fck)) { @@ -418,7 +418,7 @@ retry: if (cpu_is_omap24xx()) { struct dispc_clock_info cur_dispc; /* XXX can we change the clock on omap2? */ - fck = dss_clk_get_rate(DSS_CLK_FCK1); + fck = dss_clk_get_rate(DSS_CLK_FCK); fck_div = 1; dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc); @@ -701,7 +701,7 @@ static void save_all_ctx(void) { DSSDBG("save context\n"); - dss_clk_enable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1); + dss_clk_enable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK); dss_save_context(); dispc_save_context(); @@ -709,7 +709,7 @@ static void save_all_ctx(void) dsi_save_context(); #endif - dss_clk_disable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1); + dss_clk_disable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK); } static void restore_all_ctx(void) @@ -807,13 +807,13 @@ unsigned long dss_clk_get_rate(enum dss_clock clk) switch (clk) { case DSS_CLK_ICK: return clk_get_rate(dss.dss_ick); - case DSS_CLK_FCK1: + case DSS_CLK_FCK: return clk_get_rate(dss.dss1_fck); - case DSS_CLK_FCK2: + case DSS_CLK_SYSCK: return clk_get_rate(dss.dss2_fck); - case DSS_CLK_54M: + case DSS_CLK_TVFCK: return clk_get_rate(dss.dss_54m_fck); - case DSS_CLK_96M: + case DSS_CLK_VIDFCK: return clk_get_rate(dss.dss_96m_fck); } @@ -827,13 +827,13 @@ static unsigned count_clk_bits(enum dss_clock clks) if (clks & DSS_CLK_ICK) ++num_clks; - if (clks & DSS_CLK_FCK1) + if (clks & DSS_CLK_FCK) ++num_clks; - if (clks & DSS_CLK_FCK2) + if (clks & DSS_CLK_SYSCK) ++num_clks; - if (clks & DSS_CLK_54M) + if (clks & DSS_CLK_TVFCK) ++num_clks; - if (clks & DSS_CLK_96M) + if (clks & DSS_CLK_VIDFCK) ++num_clks; return num_clks; @@ -845,13 +845,13 @@ static void dss_clk_enable_no_ctx(enum dss_clock clks) if (clks & DSS_CLK_ICK) clk_enable(dss.dss_ick); - if (clks & DSS_CLK_FCK1) + if (clks & DSS_CLK_FCK) clk_enable(dss.dss1_fck); - if (clks & DSS_CLK_FCK2) + if (clks & DSS_CLK_SYSCK) clk_enable(dss.dss2_fck); - if (clks & DSS_CLK_54M) + if (clks & DSS_CLK_TVFCK) clk_enable(dss.dss_54m_fck); - if (clks & DSS_CLK_96M) + if (clks & DSS_CLK_VIDFCK) clk_enable(dss.dss_96m_fck); dss.num_clks_enabled += num_clks; @@ -873,13 +873,13 @@ static void dss_clk_disable_no_ctx(enum dss_clock clks) if (clks & DSS_CLK_ICK) clk_disable(dss.dss_ick); - if (clks & DSS_CLK_FCK1) + if (clks & DSS_CLK_FCK) clk_disable(dss.dss1_fck); - if (clks & DSS_CLK_FCK2) + if (clks & DSS_CLK_SYSCK) clk_disable(dss.dss2_fck); - if (clks & DSS_CLK_54M) + if (clks & DSS_CLK_TVFCK) clk_disable(dss.dss_54m_fck); - if (clks & DSS_CLK_96M) + if (clks & DSS_CLK_VIDFCK) clk_disable(dss.dss_96m_fck); dss.num_clks_enabled -= num_clks; @@ -903,9 +903,9 @@ static void dss_clk_enable_all_no_ctx(void) { enum dss_clock clks; - clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M; + clks = DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_SYSCK | DSS_CLK_TVFCK; if (cpu_is_omap34xx()) - clks |= DSS_CLK_96M; + clks |= DSS_CLK_VIDFCK; dss_clk_enable_no_ctx(clks); } @@ -913,9 +913,9 @@ static void dss_clk_disable_all_no_ctx(void) { enum dss_clock clks; - clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M; + clks = DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_SYSCK | DSS_CLK_TVFCK; if (cpu_is_omap34xx()) - clks |= DSS_CLK_96M; + clks |= DSS_CLK_VIDFCK; dss_clk_disable_no_ctx(clks); } diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h index 981d247c30f2..4b02e079f20e 100644 --- a/drivers/video/omap2/dss/dss.h +++ b/drivers/video/omap2/dss/dss.h @@ -112,11 +112,11 @@ enum omap_parallel_interface_mode { }; enum dss_clock { - DSS_CLK_ICK = 1 << 0, - DSS_CLK_FCK1 = 1 << 1, - DSS_CLK_FCK2 = 1 << 2, - DSS_CLK_54M = 1 << 3, - DSS_CLK_96M = 1 << 4, + DSS_CLK_ICK = 1 << 0, /* DSS_L3_ICLK and DSS_L4_ICLK */ + DSS_CLK_FCK = 1 << 1, /* DSS1_ALWON_FCLK */ + DSS_CLK_SYSCK = 1 << 2, /* DSS2_ALWON_FCLK */ + DSS_CLK_TVFCK = 1 << 3, /* DSS_TV_FCLK */ + DSS_CLK_VIDFCK = 1 << 4, /* DSS_96M_FCLK*/ }; enum dss_clk_source { diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c index 172d4e697309..1f53bf20b6cb 100644 --- a/drivers/video/omap2/dss/manager.c +++ b/drivers/video/omap2/dss/manager.c @@ -1394,7 +1394,7 @@ static int omap_dss_mgr_apply(struct omap_overlay_manager *mgr) } r = 0; - dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); + dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); if (!dss_cache.irq_enabled) { u32 mask; @@ -1407,7 +1407,7 @@ static int omap_dss_mgr_apply(struct omap_overlay_manager *mgr) dss_cache.irq_enabled = true; } configure_dispc(); - dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); + dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); spin_unlock_irqrestore(&dss_cache.lock, flags); diff --git a/drivers/video/omap2/dss/overlay.c b/drivers/video/omap2/dss/overlay.c index 456efef03c20..996e9a4f6771 100644 --- a/drivers/video/omap2/dss/overlay.c +++ b/drivers/video/omap2/dss/overlay.c @@ -490,7 +490,7 @@ static int omap_dss_set_manager(struct omap_overlay *ovl, ovl->manager = mgr; - dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); + dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); /* XXX: on manual update display, in auto update mode, a bug happens * here. When an overlay is first enabled on LCD, then it's disabled, * and the manager is changed to TV, we sometimes get SYNC_LOST_DIGIT @@ -499,7 +499,7 @@ static int omap_dss_set_manager(struct omap_overlay *ovl, * but I don't understand how or why. */ msleep(40); dispc_set_channel_out(ovl->id, mgr->id); - dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); + dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); return 0; } diff --git a/drivers/video/omap2/dss/rfbi.c b/drivers/video/omap2/dss/rfbi.c index 6dbb95d557f8..5ea17f49c611 100644 --- a/drivers/video/omap2/dss/rfbi.c +++ b/drivers/video/omap2/dss/rfbi.c @@ -141,9 +141,9 @@ static inline u32 rfbi_read_reg(const struct rfbi_reg idx) static void rfbi_enable_clocks(bool enable) { if (enable) - dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); + dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); else - dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); + dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); } void omap_rfbi_write_command(const void *buf, u32 len) @@ -496,7 +496,7 @@ unsigned long rfbi_get_max_tx_rate(void) }; l4_rate = rfbi.l4_khz / 1000; - dss1_rate = dss_clk_get_rate(DSS_CLK_FCK1) / 1000000; + dss1_rate = dss_clk_get_rate(DSS_CLK_FCK) / 1000000; for (i = 0; i < ARRAY_SIZE(ftab); i++) { /* Use a window instead of an exact match, to account @@ -921,7 +921,7 @@ void rfbi_dump_regs(struct seq_file *s) { #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, rfbi_read_reg(r)) - dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); + dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); DUMPREG(RFBI_REVISION); DUMPREG(RFBI_SYSCONFIG); @@ -952,7 +952,7 @@ void rfbi_dump_regs(struct seq_file *s) DUMPREG(RFBI_VSYNC_WIDTH); DUMPREG(RFBI_HSYNC_WIDTH); - dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); + dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); #undef DUMPREG } diff --git a/drivers/video/omap2/dss/sdi.c b/drivers/video/omap2/dss/sdi.c index b64adf7dfc88..8272fc1f3279 100644 --- a/drivers/video/omap2/dss/sdi.c +++ b/drivers/video/omap2/dss/sdi.c @@ -70,7 +70,7 @@ int omapdss_sdi_display_enable(struct omap_dss_device *dssdev) /* In case of skip_init sdi_init has already enabled the clocks */ if (!sdi.skip_init) - dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); + dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); sdi_basic_init(dssdev); @@ -130,7 +130,7 @@ int omapdss_sdi_display_enable(struct omap_dss_device *dssdev) return 0; err2: - dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); + dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); regulator_disable(sdi.vdds_sdi_reg); err1: omap_dss_stop_device(dssdev); @@ -145,7 +145,7 @@ void omapdss_sdi_display_disable(struct omap_dss_device *dssdev) dss_sdi_disable(); - dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); + dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); regulator_disable(sdi.vdds_sdi_reg); @@ -175,7 +175,7 @@ int sdi_init(bool skip_init) * of them until sdi_display_enable is called. */ if (skip_init) - dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); + dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); return 0; } diff --git a/drivers/video/omap2/dss/venc.c b/drivers/video/omap2/dss/venc.c index ef36811f6ac8..1aadceb76e1d 100644 --- a/drivers/video/omap2/dss/venc.c +++ b/drivers/video/omap2/dss/venc.c @@ -391,11 +391,11 @@ static void venc_reset(void) static void venc_enable_clocks(int enable) { if (enable) - dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_54M | - DSS_CLK_96M); + dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_TVFCK | + DSS_CLK_VIDFCK); else - dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_54M | - DSS_CLK_96M); + dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_TVFCK | + DSS_CLK_VIDFCK); } static const struct venc_config *venc_timings_to_config( From c7642f67e5bd71f91d165620f601f00c7c9802c9 Mon Sep 17 00:00:00 2001 From: Archit Taneja Date: Mon, 31 Jan 2011 16:27:45 +0000 Subject: [PATCH 015/140] OMAP2PLUS: DSS2: Generalize external clock names in struct dss of dss.c The dss struct in dss.c has omap2/3 specific clock names. Making them generic, to increase readability and extendability. Signed-off-by: Sumit Semwal Signed-off-by: Archit Taneja Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dss.c | 82 +++++++++++++++++------------------ 1 file changed, 41 insertions(+), 41 deletions(-) diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c index 0372befbb692..ab82f7937675 100644 --- a/drivers/video/omap2/dss/dss.c +++ b/drivers/video/omap2/dss/dss.c @@ -64,10 +64,10 @@ static struct { struct clk *dpll4_m4_ck; struct clk *dss_ick; - struct clk *dss1_fck; - struct clk *dss2_fck; - struct clk *dss_54m_fck; - struct clk *dss_96m_fck; + struct clk *dss_fck; + struct clk *dss_sys_clk; + struct clk *dss_tv_fck; + struct clk *dss_video_fck; unsigned num_clks_enabled; unsigned long cache_req_pck; @@ -750,28 +750,28 @@ static int dss_get_clocks(void) int r; dss.dss_ick = NULL; - dss.dss1_fck = NULL; - dss.dss2_fck = NULL; - dss.dss_54m_fck = NULL; - dss.dss_96m_fck = NULL; + dss.dss_fck = NULL; + dss.dss_sys_clk = NULL; + dss.dss_tv_fck = NULL; + dss.dss_video_fck = NULL; r = dss_get_clock(&dss.dss_ick, "ick"); if (r) goto err; - r = dss_get_clock(&dss.dss1_fck, "fck"); + r = dss_get_clock(&dss.dss_fck, "fck"); if (r) goto err; - r = dss_get_clock(&dss.dss2_fck, "sys_clk"); + r = dss_get_clock(&dss.dss_sys_clk, "sys_clk"); if (r) goto err; - r = dss_get_clock(&dss.dss_54m_fck, "tv_clk"); + r = dss_get_clock(&dss.dss_tv_fck, "tv_clk"); if (r) goto err; - r = dss_get_clock(&dss.dss_96m_fck, "video_clk"); + r = dss_get_clock(&dss.dss_video_fck, "video_clk"); if (r) goto err; @@ -780,25 +780,25 @@ static int dss_get_clocks(void) err: if (dss.dss_ick) clk_put(dss.dss_ick); - if (dss.dss1_fck) - clk_put(dss.dss1_fck); - if (dss.dss2_fck) - clk_put(dss.dss2_fck); - if (dss.dss_54m_fck) - clk_put(dss.dss_54m_fck); - if (dss.dss_96m_fck) - clk_put(dss.dss_96m_fck); + if (dss.dss_fck) + clk_put(dss.dss_fck); + if (dss.dss_sys_clk) + clk_put(dss.dss_sys_clk); + if (dss.dss_tv_fck) + clk_put(dss.dss_tv_fck); + if (dss.dss_video_fck) + clk_put(dss.dss_video_fck); return r; } static void dss_put_clocks(void) { - if (dss.dss_96m_fck) - clk_put(dss.dss_96m_fck); - clk_put(dss.dss_54m_fck); - clk_put(dss.dss1_fck); - clk_put(dss.dss2_fck); + if (dss.dss_video_fck) + clk_put(dss.dss_video_fck); + clk_put(dss.dss_tv_fck); + clk_put(dss.dss_fck); + clk_put(dss.dss_sys_clk); clk_put(dss.dss_ick); } @@ -808,13 +808,13 @@ unsigned long dss_clk_get_rate(enum dss_clock clk) case DSS_CLK_ICK: return clk_get_rate(dss.dss_ick); case DSS_CLK_FCK: - return clk_get_rate(dss.dss1_fck); + return clk_get_rate(dss.dss_fck); case DSS_CLK_SYSCK: - return clk_get_rate(dss.dss2_fck); + return clk_get_rate(dss.dss_sys_clk); case DSS_CLK_TVFCK: - return clk_get_rate(dss.dss_54m_fck); + return clk_get_rate(dss.dss_tv_fck); case DSS_CLK_VIDFCK: - return clk_get_rate(dss.dss_96m_fck); + return clk_get_rate(dss.dss_video_fck); } BUG(); @@ -846,13 +846,13 @@ static void dss_clk_enable_no_ctx(enum dss_clock clks) if (clks & DSS_CLK_ICK) clk_enable(dss.dss_ick); if (clks & DSS_CLK_FCK) - clk_enable(dss.dss1_fck); + clk_enable(dss.dss_fck); if (clks & DSS_CLK_SYSCK) - clk_enable(dss.dss2_fck); + clk_enable(dss.dss_sys_clk); if (clks & DSS_CLK_TVFCK) - clk_enable(dss.dss_54m_fck); + clk_enable(dss.dss_tv_fck); if (clks & DSS_CLK_VIDFCK) - clk_enable(dss.dss_96m_fck); + clk_enable(dss.dss_video_fck); dss.num_clks_enabled += num_clks; } @@ -874,13 +874,13 @@ static void dss_clk_disable_no_ctx(enum dss_clock clks) if (clks & DSS_CLK_ICK) clk_disable(dss.dss_ick); if (clks & DSS_CLK_FCK) - clk_disable(dss.dss1_fck); + clk_disable(dss.dss_fck); if (clks & DSS_CLK_SYSCK) - clk_disable(dss.dss2_fck); + clk_disable(dss.dss_sys_clk); if (clks & DSS_CLK_TVFCK) - clk_disable(dss.dss_54m_fck); + clk_disable(dss.dss_tv_fck); if (clks & DSS_CLK_VIDFCK) - clk_disable(dss.dss_96m_fck); + clk_disable(dss.dss_video_fck); dss.num_clks_enabled -= num_clks; } @@ -926,10 +926,10 @@ static void core_dump_clocks(struct seq_file *s) int i; struct clk *clocks[5] = { dss.dss_ick, - dss.dss1_fck, - dss.dss2_fck, - dss.dss_54m_fck, - dss.dss_96m_fck + dss.dss_fck, + dss.dss_sys_clk, + dss.dss_tv_fck, + dss.dss_video_fck }; seq_printf(s, "- CORE -\n"); From f38190d61fe378d8eaf21b160c22e78b3b925747 Mon Sep 17 00:00:00 2001 From: Sumit Semwal Date: Mon, 31 Jan 2011 16:27:46 +0000 Subject: [PATCH 016/140] OMAP4: DSS2: clocks: Add ick as dummy clock DSS code uses ick as one of the clocks in clk_get/clk_put. OMAP4 clock database doesn't have ick for DSS, so adding ick as dummy clock. This is needed for backward compatibility with OMAP2/3. Once pm_runtime* APIs get introduced in DSS, this will be revisited. Signed-off-by: Sumit Semwal Signed-off-by: Tomi Valkeinen --- arch/arm/mach-omap2/clock44xx_data.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index 6ba69b1158e6..555101373595 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -3111,6 +3111,11 @@ static struct omap_clk omap44xx_clks[] = { CLK("omapdss_dss", "dss_clk", &dss_dss_clk, CK_443X), CLK("omapdss_dss", "video_clk", &dss_48mhz_clk, CK_443X), CLK("omapdss_dss", "fck", &dss_fck, CK_443X), + /* + * On OMAP4, DSS ick is a dummy clock; this is needed for compatibility + * with OMAP2/3. + */ + CLK("omapdss_dss", "ick", &dummy_ck, CK_443X), CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X), CLK(NULL, "emif1_fck", &emif1_fck, CK_443X), CLK(NULL, "emif2_fck", &emif2_fck, CK_443X), From 3f3aa06c46796cd2dc0f71d7d2f41bb75f7e97ff Mon Sep 17 00:00:00 2001 From: Mayuresh Janorkar Date: Tue, 15 Feb 2011 22:54:29 -0600 Subject: [PATCH 017/140] OMAP2PLUS: DSS2: Add OMAP4 Kconfig support Enable DSS2 and OMAPFB for OMAP4 in Kconfig Signed-off-by: Mayuresh Janorkar Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/Kconfig | 6 +++--- drivers/video/omap2/omapfb/Kconfig | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/video/omap2/dss/Kconfig b/drivers/video/omap2/dss/Kconfig index 43b64403eaa4..db01473c3307 100644 --- a/drivers/video/omap2/dss/Kconfig +++ b/drivers/video/omap2/dss/Kconfig @@ -1,8 +1,8 @@ menuconfig OMAP2_DSS - tristate "OMAP2/3 Display Subsystem support (EXPERIMENTAL)" - depends on ARCH_OMAP2 || ARCH_OMAP3 + tristate "OMAP2+ Display Subsystem support (EXPERIMENTAL)" + depends on ARCH_OMAP2PLUS help - OMAP2/3 Display Subsystem support. + OMAP2+ Display Subsystem support. if OMAP2_DSS diff --git a/drivers/video/omap2/omapfb/Kconfig b/drivers/video/omap2/omapfb/Kconfig index 65149b22cf37..aa33386c81ff 100644 --- a/drivers/video/omap2/omapfb/Kconfig +++ b/drivers/video/omap2/omapfb/Kconfig @@ -1,5 +1,5 @@ menuconfig FB_OMAP2 - tristate "OMAP2/3 frame buffer support (EXPERIMENTAL)" + tristate "OMAP2+ frame buffer support (EXPERIMENTAL)" depends on FB && OMAP2_DSS select OMAP2_VRAM @@ -8,10 +8,10 @@ menuconfig FB_OMAP2 select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT help - Frame buffer driver for OMAP2/3 based boards. + Frame buffer driver for OMAP2+ based boards. config FB_OMAP2_DEBUG_SUPPORT - bool "Debug support for OMAP2/3 FB" + bool "Debug support for OMAP2+ FB" default y depends on FB_OMAP2 help From 545376e734a6b0a4c66efb7616724ae4dbb2e57a Mon Sep 17 00:00:00 2001 From: Mayuresh Janorkar Date: Thu, 27 Jan 2011 11:17:04 +0000 Subject: [PATCH 018/140] OMAP4: DSS2: Add hwmod device names for OMAP4. Add hwmod device names for OMAP4; this enables device build for omap4 dss hwmod IPs. Signed-off-by: Sumit Semwal Signed-off-by: Mayuresh Janorkar Signed-off-by: Tomi Valkeinen --- arch/arm/mach-omap2/display.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c index ee8303037d3d..16d0db6718ae 100644 --- a/arch/arm/mach-omap2/display.c +++ b/arch/arm/mach-omap2/display.c @@ -52,22 +52,28 @@ int __init omap_display_init(struct omap_dss_board_info *board_data) /* * omap: valid DSS hwmod names - * omap2,3: dss_core, dss_dispc, dss_rfbi, dss_venc - * omap3: dss_dsi1 + * omap2,3,4: dss_core, dss_dispc, dss_rfbi, dss_venc + * omap3,4: dss_dsi1 + * omap4: dss_dsi2, dss_hdmi */ char *oh_name[] = { "dss_core", "dss_dispc", "dss_rfbi", "dss_venc", - "dss_dsi1" }; + "dss_dsi1", "dss_dsi2", "dss_hdmi" }; char *dev_name[] = { "omapdss_dss", "omapdss_dispc", "omapdss_rfbi", - "omapdss_venc", "omapdss_dsi1" }; + "omapdss_venc", "omapdss_dsi1", "omapdss_dsi2", + "omapdss_hdmi" }; int oh_count; memset(&pdata, 0, sizeof(pdata)); if (cpu_is_omap24xx()) - oh_count = ARRAY_SIZE(oh_name) - 1; - /* last hwmod dev in oh_name is not available for omap2 */ - else + oh_count = ARRAY_SIZE(oh_name) - 3; + /* last 3 hwmod dev in oh_name are not available for omap2 */ + else if (cpu_is_omap44xx()) oh_count = ARRAY_SIZE(oh_name); + else + oh_count = ARRAY_SIZE(oh_name) - 2; + /* last 2 hwmod dev in oh_name are not available for omap3 */ + pdata.board_data = board_data; pdata.board_data->get_last_off_on_transaction_id = NULL; From ac425ed5fb0b6564d4eeee9fb13ef0c1f6da8e8f Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 16 Feb 2011 04:53:44 -0600 Subject: [PATCH 019/140] OMAP: DSS2: Fix def_disp module param description MODULE_PARM_DESC() takes the name of the actual module parameter, not the name of the variable, as input. Fix the module parameter description for def_disp. Signed-off-by: Jani Nikula Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/video/omap2/dss/core.c b/drivers/video/omap2/dss/core.c index f56ee64f5b58..bcf69a462b5f 100644 --- a/drivers/video/omap2/dss/core.c +++ b/drivers/video/omap2/dss/core.c @@ -47,7 +47,7 @@ static struct { static char *def_disp_name; module_param_named(def_disp, def_disp_name, charp, 0); -MODULE_PARM_DESC(def_disp_name, "default display name"); +MODULE_PARM_DESC(def_disp, "default display name"); #ifdef DEBUG unsigned int dss_debug; From 5f42f2ce63f5ecbd9bc744b9c25d9786e9a8e3b4 Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Tue, 22 Feb 2011 15:53:46 +0200 Subject: [PATCH 020/140] OMAP: DSS2: Delay regulator_get() calls DSS submodules DPI/SDI/DSI/VENC require a regulator to function. However, if the board doesn't use, say, SDI, the board shouldn't need to configure vdds_sdi regulator required by the SDI module. Currently the regulators are acquired when the DSS driver is loaded. This means that if the kernel is configured with SDI, vdds_sdi regulator is needed for all boards. This patch changes the DSS driver to acquire the regulators only when a display of particular type is initialized. For example, vdds_sdi is acquired when sdi_init_display() is called. Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dpi.c | 21 ++++++++++++-------- drivers/video/omap2/dss/dsi.c | 36 ++++++++++++---------------------- drivers/video/omap2/dss/sdi.c | 18 ++++++++++++----- drivers/video/omap2/dss/venc.c | 31 ++++++++++++----------------- 4 files changed, 52 insertions(+), 54 deletions(-) diff --git a/drivers/video/omap2/dss/dpi.c b/drivers/video/omap2/dss/dpi.c index 746f1b6dd897..026702b921e5 100644 --- a/drivers/video/omap2/dss/dpi.c +++ b/drivers/video/omap2/dss/dpi.c @@ -303,19 +303,24 @@ int dpi_init_display(struct omap_dss_device *dssdev) { DSSDBG("init_display\n"); + if (cpu_is_omap34xx() && dpi.vdds_dsi_reg == NULL) { + struct regulator *vdds_dsi; + + vdds_dsi = dss_get_vdds_dsi(); + + if (IS_ERR(vdds_dsi)) { + DSSERR("can't get VDDS_DSI regulator\n"); + return PTR_ERR(vdds_dsi); + } + + dpi.vdds_dsi_reg = vdds_dsi; + } + return 0; } int dpi_init(struct platform_device *pdev) { - if (cpu_is_omap34xx()) { - dpi.vdds_dsi_reg = dss_get_vdds_dsi(); - if (IS_ERR(dpi.vdds_dsi_reg)) { - DSSERR("can't get VDDS_DSI regulator\n"); - return PTR_ERR(dpi.vdds_dsi_reg); - } - } - return 0; } diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c index c7b5382e1a6b..2928cddeb3fc 100644 --- a/drivers/video/omap2/dss/dsi.c +++ b/drivers/video/omap2/dss/dsi.c @@ -291,20 +291,6 @@ static inline u32 dsi_read_reg(const struct dsi_reg idx) return __raw_readl(dsi.base + idx.idx); } -static struct regulator *dsi_get_vdds_dsi(void) -{ - struct regulator *reg; - - if (dsi.vdds_dsi_reg != NULL) - return dsi.vdds_dsi_reg; - - reg = regulator_get(&dsi.pdev->dev, "vdds_dsi"); - if (!IS_ERR(reg)) - dsi.vdds_dsi_reg = reg; - - return reg; -} - void dsi_save_context(void) { @@ -3236,6 +3222,19 @@ int dsi_init_display(struct omap_dss_device *dssdev) dsi.vc[0].dssdev = dssdev; dsi.vc[1].dssdev = dssdev; + if (dsi.vdds_dsi_reg == NULL) { + struct regulator *vdds_dsi; + + vdds_dsi = regulator_get(&dsi.pdev->dev, "vdds_dsi"); + + if (IS_ERR(vdds_dsi)) { + DSSERR("can't get VDDS_DSI regulator\n"); + return PTR_ERR(vdds_dsi); + } + + dsi.vdds_dsi_reg = vdds_dsi; + } + return 0; } @@ -3295,13 +3294,6 @@ static int dsi_init(struct platform_device *pdev) goto err1; } - dsi.vdds_dsi_reg = dsi_get_vdds_dsi(); - if (IS_ERR(dsi.vdds_dsi_reg)) { - DSSERR("can't get VDDS_DSI regulator\n"); - r = PTR_ERR(dsi.vdds_dsi_reg); - goto err2; - } - enable_clocks(1); rev = dsi_read_reg(DSI_REVISION); @@ -3311,8 +3303,6 @@ static int dsi_init(struct platform_device *pdev) enable_clocks(0); return 0; -err2: - iounmap(dsi.base); err1: destroy_workqueue(dsi.workqueue); return r; diff --git a/drivers/video/omap2/dss/sdi.c b/drivers/video/omap2/dss/sdi.c index 8272fc1f3279..9f10a0d9e760 100644 --- a/drivers/video/omap2/dss/sdi.c +++ b/drivers/video/omap2/dss/sdi.c @@ -157,6 +157,19 @@ int sdi_init_display(struct omap_dss_device *dssdev) { DSSDBG("SDI init\n"); + if (sdi.vdds_sdi_reg == NULL) { + struct regulator *vdds_sdi; + + vdds_sdi = dss_get_vdds_sdi(); + + if (IS_ERR(vdds_sdi)) { + DSSERR("can't get VDDS_SDI regulator\n"); + return PTR_ERR(vdds_sdi); + } + + sdi.vdds_sdi_reg = vdds_sdi; + } + return 0; } @@ -165,11 +178,6 @@ int sdi_init(bool skip_init) /* we store this for first display enable, then clear it */ sdi.skip_init = skip_init; - sdi.vdds_sdi_reg = dss_get_vdds_sdi(); - if (IS_ERR(sdi.vdds_sdi_reg)) { - DSSERR("can't get VDDS_SDI regulator\n"); - return PTR_ERR(sdi.vdds_sdi_reg); - } /* * Enable clocks already here, otherwise there would be a toggle * of them until sdi_display_enable is called. diff --git a/drivers/video/omap2/dss/venc.c b/drivers/video/omap2/dss/venc.c index 1aadceb76e1d..43009e57cd3e 100644 --- a/drivers/video/omap2/dss/venc.c +++ b/drivers/video/omap2/dss/venc.c @@ -305,17 +305,6 @@ static inline u32 venc_read_reg(int idx) return l; } -static struct regulator *venc_get_vdda_dac(void) -{ - struct regulator *reg; - - reg = regulator_get(&venc.pdev->dev, "vdda_dac"); - if (!IS_ERR(reg)) - venc.vdda_dac_reg = reg; - - return reg; -} - static void venc_write_config(const struct venc_config *config) { DSSDBG("write venc conf\n"); @@ -655,6 +644,19 @@ int venc_init_display(struct omap_dss_device *dssdev) { DSSDBG("init_display\n"); + if (venc.vdda_dac_reg == NULL) { + struct regulator *vdda_dac; + + vdda_dac = regulator_get(&venc.pdev->dev, "vdda_dac"); + + if (IS_ERR(vdda_dac)) { + DSSERR("can't get VDDA_DAC regulator\n"); + return PTR_ERR(vdda_dac); + } + + venc.vdda_dac_reg = vdda_dac; + } + return 0; } @@ -734,13 +736,6 @@ static int omap_venchw_probe(struct platform_device *pdev) return -ENOMEM; } - venc.vdda_dac_reg = venc_get_vdda_dac(); - if (IS_ERR(venc.vdda_dac_reg)) { - iounmap(venc.base); - DSSERR("can't get VDDA_DAC regulator\n"); - return PTR_ERR(venc.vdda_dac_reg); - } - venc_enable_clocks(1); rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff); From 09dc89cb3123d102e1615fab9e3d65a70402d061 Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Tue, 22 Feb 2011 16:39:47 +0200 Subject: [PATCH 021/140] OMAP: DSS2: Support for Samsung LTE430WQ-F0C Add support for Samsung LTE430WQ-F0C to panel-generic-dpi. Signed-off-by: Tomi Valkeinen --- .../video/omap2/displays/panel-generic-dpi.c | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/video/omap2/displays/panel-generic-dpi.c b/drivers/video/omap2/displays/panel-generic-dpi.c index 07eb30ee59c8..4a9b9ff59467 100644 --- a/drivers/video/omap2/displays/panel-generic-dpi.c +++ b/drivers/video/omap2/displays/panel-generic-dpi.c @@ -156,6 +156,31 @@ static struct panel_config generic_dpi_panels[] = { .power_off_delay = 0, .name = "toppoly_tdo35s", }, + + /* Samsung LTE430WQ-F0C */ + { + { + .x_res = 480, + .y_res = 272, + + .pixel_clock = 9200, + + .hfp = 8, + .hsw = 41, + .hbp = 45 - 41, + + .vfp = 4, + .vsw = 10, + .vbp = 12 - 10, + }, + .acbi = 0x0, + .acb = 0x0, + .config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS | + OMAP_DSS_LCD_IHS, + .power_on_delay = 0, + .power_off_delay = 0, + .name = "samsung_lte430wq_f0c", + }, }; struct panel_drv_data { From 371e2081447ce2bc6a25c20b513b9ba33cf5769e Mon Sep 17 00:00:00 2001 From: "Janorkar, Mayuresh" Date: Tue, 22 Feb 2011 07:35:13 -0600 Subject: [PATCH 022/140] OMAPFB: Adding a check for timings in set_def_mode When omapfb.mode is passed through bootargs, when omapfb is setting mode, it would check if timings passed are fine for panel attached to it. It makes use of check_timing API provided by the panel. In current code if check_timing API is not available for attached panel, OMAPFB would return -EINVAL and BPP sent via bootargs will not have any effect. In case of panels like TAAL panel, omapfb or any other driver should not be allowed to change the timings. So bpps sent via bootargs will not have an effect. In such case we can check only the x_res and y_res with the panels resolution and if they match go ahead and set the bpps. The bpp value sent via bootarg would have an effect. Signed-off-by: Mayuresh Janorkar Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/omapfb/omapfb-main.c | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c index 4fdab8e9c496..505ec6672049 100644 --- a/drivers/video/omap2/omapfb/omapfb-main.c +++ b/drivers/video/omap2/omapfb/omapfb-main.c @@ -2090,7 +2090,7 @@ static int omapfb_set_def_mode(struct omapfb2_device *fbdev, { int r; u8 bpp; - struct omap_video_timings timings; + struct omap_video_timings timings, temp_timings; r = omapfb_mode_to_timings(mode_str, &timings, &bpp); if (r) @@ -2100,14 +2100,23 @@ static int omapfb_set_def_mode(struct omapfb2_device *fbdev, fbdev->bpp_overrides[fbdev->num_bpp_overrides].bpp = bpp; ++fbdev->num_bpp_overrides; - if (!display->driver->check_timings || !display->driver->set_timings) - return -EINVAL; + if (display->driver->check_timings) { + r = display->driver->check_timings(display, &timings); + if (r) + return r; + } else { + /* If check_timings is not present compare xres and yres */ + if (display->driver->get_timings) { + display->driver->get_timings(display, &temp_timings); - r = display->driver->check_timings(display, &timings); - if (r) - return r; + if (temp_timings.x_res != timings.x_res || + temp_timings.y_res != timings.y_res) + return -EINVAL; + } + } - display->driver->set_timings(display, &timings); + if (display->driver->set_timings) + display->driver->set_timings(display, &timings); return 0; } From affe360d13e54b415cde2f11cee02369b4ed54bd Mon Sep 17 00:00:00 2001 From: archit taneja Date: Wed, 23 Feb 2011 08:41:03 +0000 Subject: [PATCH 023/140] OMAP: DSS2: Have separate irq handlers for DISPC and DSI Currently, the core DSS platform device requests for an irq line for OMAP2 and OMAP3. Make DISPC and DSI platform devices request for a shared IRQ line. On OMAP3, the logical OR of DSI and DISPC interrupt lines goes to the MPU. There is a register DSS_IRQSTATUS which tells if the interrupt came from DISPC or DSI. On OMAP2, there is no DSI, only DISPC interrupts goto the MPU. There is no DSS_IRQSTATUS register. Hence, it makes more sense to have separate irq handlers corresponding to the DSS sub modules instead of having a common handler. Since on OMAP3 the logical OR of the lines goes to MPU, the irq line is shared among the IRQ handlers. The hwmod irq info has been removed for DSS to DISPC and DSI for OMAP2 and OMAP3 hwmod databases. The Probes of DISPC and DSI now request for irq handlers. Signed-off-by: Archit Taneja Signed-off-by: Tomi Valkeinen --- arch/arm/mach-omap2/omap_hwmod_2420_data.c | 13 +++--- arch/arm/mach-omap2/omap_hwmod_2430_data.c | 12 ++--- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 21 +++++---- drivers/video/omap2/dss/dispc.c | 40 +++++++++++++++-- drivers/video/omap2/dss/dsi.c | 25 ++++++++++- drivers/video/omap2/dss/dss.c | 51 +--------------------- 6 files changed, 84 insertions(+), 78 deletions(-) diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index 61e58bd27aec..3a1ad0074978 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -1168,11 +1168,6 @@ static struct omap_hwmod_class omap2420_dss_hwmod_class = { .sysc = &omap2420_dss_sysc, }; -/* dss */ -static struct omap_hwmod_irq_info omap2420_dss_irqs[] = { - { .irq = 25 }, -}; - static struct omap_hwmod_dma_info omap2420_dss_sdma_chs[] = { { .name = "dispc", .dma_req = 5 }, }; @@ -1221,8 +1216,6 @@ static struct omap_hwmod omap2420_dss_core_hwmod = { .name = "dss_core", .class = &omap2420_dss_hwmod_class, .main_clk = "dss1_fck", /* instead of dss_fck */ - .mpu_irqs = omap2420_dss_irqs, - .mpu_irqs_cnt = ARRAY_SIZE(omap2420_dss_irqs), .sdma_reqs = omap2420_dss_sdma_chs, .sdma_reqs_cnt = ARRAY_SIZE(omap2420_dss_sdma_chs), .prcm = { @@ -1265,6 +1258,10 @@ static struct omap_hwmod_class omap2420_dispc_hwmod_class = { .sysc = &omap2420_dispc_sysc, }; +static struct omap_hwmod_irq_info omap2420_dispc_irqs[] = { + { .irq = 25 }, +}; + static struct omap_hwmod_addr_space omap2420_dss_dispc_addrs[] = { { .pa_start = 0x48050400, @@ -1297,6 +1294,8 @@ static struct omap_hwmod_ocp_if *omap2420_dss_dispc_slaves[] = { static struct omap_hwmod omap2420_dss_dispc_hwmod = { .name = "dss_dispc", .class = &omap2420_dispc_hwmod_class, + .mpu_irqs = omap2420_dispc_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_dispc_irqs), .main_clk = "dss1_fck", .prcm = { .omap2 = { diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 490789a6bed0..c905c1bf90c4 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -1268,10 +1268,6 @@ static struct omap_hwmod_class omap2430_dss_hwmod_class = { .sysc = &omap2430_dss_sysc, }; -/* dss */ -static struct omap_hwmod_irq_info omap2430_dss_irqs[] = { - { .irq = 25 }, -}; static struct omap_hwmod_dma_info omap2430_dss_sdma_chs[] = { { .name = "dispc", .dma_req = 5 }, }; @@ -1314,8 +1310,6 @@ static struct omap_hwmod omap2430_dss_core_hwmod = { .name = "dss_core", .class = &omap2430_dss_hwmod_class, .main_clk = "dss1_fck", /* instead of dss_fck */ - .mpu_irqs = omap2430_dss_irqs, - .mpu_irqs_cnt = ARRAY_SIZE(omap2430_dss_irqs), .sdma_reqs = omap2430_dss_sdma_chs, .sdma_reqs_cnt = ARRAY_SIZE(omap2430_dss_sdma_chs), .prcm = { @@ -1358,6 +1352,10 @@ static struct omap_hwmod_class omap2430_dispc_hwmod_class = { .sysc = &omap2430_dispc_sysc, }; +static struct omap_hwmod_irq_info omap2430_dispc_irqs[] = { + { .irq = 25 }, +}; + static struct omap_hwmod_addr_space omap2430_dss_dispc_addrs[] = { { .pa_start = 0x48050400, @@ -1384,6 +1382,8 @@ static struct omap_hwmod_ocp_if *omap2430_dss_dispc_slaves[] = { static struct omap_hwmod omap2430_dss_dispc_hwmod = { .name = "dss_dispc", .class = &omap2430_dispc_hwmod_class, + .mpu_irqs = omap2430_dispc_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_dispc_irqs), .main_clk = "dss1_fck", .prcm = { .omap2 = { diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 4ed48cab06fe..f997b0e9759d 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -1503,11 +1503,6 @@ static struct omap_hwmod_class omap3xxx_dss_hwmod_class = { .sysc = &omap3xxx_dss_sysc, }; -/* dss */ -static struct omap_hwmod_irq_info omap3xxx_dss_irqs[] = { - { .irq = 25 }, -}; - static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = { { .name = "dispc", .dma_req = 5 }, { .name = "dsi1", .dma_req = 74 }, @@ -1579,8 +1574,6 @@ static struct omap_hwmod omap3430es1_dss_core_hwmod = { .name = "dss_core", .class = &omap3xxx_dss_hwmod_class, .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ - .mpu_irqs = omap3xxx_dss_irqs, - .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dss_irqs), .sdma_reqs = omap3xxx_dss_sdma_chs, .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs), @@ -1607,8 +1600,6 @@ static struct omap_hwmod omap3xxx_dss_core_hwmod = { .name = "dss_core", .class = &omap3xxx_dss_hwmod_class, .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ - .mpu_irqs = omap3xxx_dss_irqs, - .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dss_irqs), .sdma_reqs = omap3xxx_dss_sdma_chs, .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs), @@ -1654,6 +1645,10 @@ static struct omap_hwmod_class omap3xxx_dispc_hwmod_class = { .sysc = &omap3xxx_dispc_sysc, }; +static struct omap_hwmod_irq_info omap3xxx_dispc_irqs[] = { + { .irq = 25 }, +}; + static struct omap_hwmod_addr_space omap3xxx_dss_dispc_addrs[] = { { .pa_start = 0x48050400, @@ -1687,6 +1682,8 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = { static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { .name = "dss_dispc", .class = &omap3xxx_dispc_hwmod_class, + .mpu_irqs = omap3xxx_dispc_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dispc_irqs), .main_clk = "dss1_alwon_fck", .prcm = { .omap2 = { @@ -1712,6 +1709,10 @@ static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = { .name = "dsi", }; +static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = { + { .irq = 25 }, +}; + /* dss_dsi1 */ static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = { { @@ -1745,6 +1746,8 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = { static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = { .name = "dss_dsi1", .class = &omap3xxx_dsi_hwmod_class, + .mpu_irqs = omap3xxx_dsi1_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dsi1_irqs), .main_clk = "dss1_alwon_fck", .prcm = { .omap2 = { diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c index dc4518c4b0e4..43f7091c71cb 100644 --- a/drivers/video/omap2/dss/dispc.c +++ b/drivers/video/omap2/dss/dispc.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include @@ -178,6 +179,7 @@ struct dispc_irq_stats { static struct { struct platform_device *pdev; void __iomem *base; + int irq; u32 fifo_size[3]; @@ -2865,10 +2867,10 @@ static void print_irq_status(u32 status) * but we presume they are on because we got an IRQ. However, * an irq handler may turn the clocks off, so we may not have * clock later in the function. */ -void dispc_irq_handler(void) +static irqreturn_t omap_dispc_irq_handler(int irq, void *arg) { int i; - u32 irqstatus; + u32 irqstatus, irqenable; u32 handledirqs = 0; u32 unhandled_errors; struct omap_dispc_isr_data *isr_data; @@ -2877,6 +2879,13 @@ void dispc_irq_handler(void) spin_lock(&dispc.irq_lock); irqstatus = dispc_read_reg(DISPC_IRQSTATUS); + irqenable = dispc_read_reg(DISPC_IRQENABLE); + + /* IRQ is not for us */ + if (!(irqstatus & irqenable)) { + spin_unlock(&dispc.irq_lock); + return IRQ_NONE; + } #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS spin_lock(&dispc.irq_stats_lock); @@ -2928,6 +2937,8 @@ void dispc_irq_handler(void) } spin_unlock(&dispc.irq_lock); + + return IRQ_HANDLED; } static void dispc_error_worker(struct work_struct *work) @@ -3322,6 +3333,7 @@ int dispc_setup_plane(enum omap_plane plane, static int omap_dispchw_probe(struct platform_device *pdev) { u32 rev; + int r = 0; struct resource *dispc_mem; dispc.pdev = pdev; @@ -3338,12 +3350,27 @@ static int omap_dispchw_probe(struct platform_device *pdev) dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0); if (!dispc_mem) { DSSERR("can't get IORESOURCE_MEM DISPC\n"); - return -EINVAL; + r = -EINVAL; + goto fail0; } dispc.base = ioremap(dispc_mem->start, resource_size(dispc_mem)); if (!dispc.base) { DSSERR("can't ioremap DISPC\n"); - return -ENOMEM; + r = -ENOMEM; + goto fail0; + } + dispc.irq = platform_get_irq(dispc.pdev, 0); + if (dispc.irq < 0) { + DSSERR("platform_get_irq failed\n"); + r = -ENODEV; + goto fail1; + } + + r = request_irq(dispc.irq, omap_dispc_irq_handler, IRQF_SHARED, + "OMAP DISPC", dispc.pdev); + if (r < 0) { + DSSERR("request_irq failed\n"); + goto fail1; } enable_clocks(1); @@ -3361,10 +3388,15 @@ static int omap_dispchw_probe(struct platform_device *pdev) enable_clocks(0); return 0; +fail1: + iounmap(dispc.base); +fail0: + return r; } static int omap_dispchw_remove(struct platform_device *pdev) { + free_irq(dispc.irq, dispc.pdev); iounmap(dispc.base); return 0; } diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c index 2928cddeb3fc..2f7d9491cd02 100644 --- a/drivers/video/omap2/dss/dsi.c +++ b/drivers/video/omap2/dss/dsi.c @@ -222,6 +222,7 @@ static struct { struct platform_device *pdev; void __iomem *base; + int irq; struct dsi_clock_info current_cinfo; @@ -480,13 +481,17 @@ static void print_irq_status_cio(u32 status) static int debug_irq; /* called from dss */ -void dsi_irq_handler(void) +static irqreturn_t omap_dsi_irq_handler(int irq, void *arg) { u32 irqstatus, vcstatus, ciostatus; int i; irqstatus = dsi_read_reg(DSI_IRQSTATUS); + /* IRQ is not for us */ + if (!irqstatus) + return IRQ_NONE; + #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS spin_lock(&dsi.irq_stats_lock); dsi.irq_stats.irq_count++; @@ -564,9 +569,9 @@ void dsi_irq_handler(void) #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS spin_unlock(&dsi.irq_stats_lock); #endif + return IRQ_HANDLED; } - static void _dsi_initialize_irq(void) { u32 l; @@ -3293,6 +3298,19 @@ static int dsi_init(struct platform_device *pdev) r = -ENOMEM; goto err1; } + dsi.irq = platform_get_irq(dsi.pdev, 0); + if (dsi.irq < 0) { + DSSERR("platform_get_irq failed\n"); + r = -ENODEV; + goto err2; + } + + r = request_irq(dsi.irq, omap_dsi_irq_handler, IRQF_SHARED, + "OMAP DSI1", dsi.pdev); + if (r < 0) { + DSSERR("request_irq failed\n"); + goto err2; + } enable_clocks(1); @@ -3303,6 +3321,8 @@ static int dsi_init(struct platform_device *pdev) enable_clocks(0); return 0; +err2: + iounmap(dsi.base); err1: destroy_workqueue(dsi.workqueue); return r; @@ -3315,6 +3335,7 @@ static void dsi_exit(void) dsi.vdds_dsi_reg = NULL; } + free_irq(dsi.irq, dsi.pdev); iounmap(dsi.base); destroy_workqueue(dsi.workqueue); diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c index ab82f7937675..dc57100cc43d 100644 --- a/drivers/video/omap2/dss/dss.c +++ b/drivers/video/omap2/dss/dss.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include @@ -79,7 +78,6 @@ static struct { enum dss_clk_source dispc_clk_source; u32 ctx[DSS_SZ_REGS / sizeof(u32)]; - int dss_irq; } dss; static void dss_clk_enable_all_no_ctx(void); @@ -495,31 +493,6 @@ found: return 0; } - - -static irqreturn_t dss_irq_handler_omap2(int irq, void *arg) -{ - dispc_irq_handler(); - - return IRQ_HANDLED; -} - -static irqreturn_t dss_irq_handler_omap3(int irq, void *arg) -{ - u32 irqstatus; - - irqstatus = dss_read_reg(DSS_IRQSTATUS); - - if (irqstatus & (1<<0)) /* DISPC_IRQ */ - dispc_irq_handler(); -#ifdef CONFIG_OMAP2_DSS_DSI - if (irqstatus & (1<<1)) /* DSI_IRQ */ - dsi_irq_handler(); -#endif - - return IRQ_HANDLED; -} - static int _omap_dss_wait_reset(void) { int t = 0; @@ -610,30 +583,12 @@ static int dss_init(bool skip_init) REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */ #endif - dss.dss_irq = platform_get_irq(dss.pdev, 0); - if (dss.dss_irq < 0) { - DSSERR("omap2 dss: platform_get_irq failed\n"); - r = -ENODEV; - goto fail1; - } - - r = request_irq(dss.dss_irq, - cpu_is_omap24xx() - ? dss_irq_handler_omap2 - : dss_irq_handler_omap3, - 0, "OMAP DSS", NULL); - - if (r < 0) { - DSSERR("omap2 dss: request_irq failed\n"); - goto fail1; - } - if (cpu_is_omap34xx()) { dss.dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck"); if (IS_ERR(dss.dpll4_m4_ck)) { DSSERR("Failed to get dpll4_m4_ck\n"); r = PTR_ERR(dss.dpll4_m4_ck); - goto fail2; + goto fail1; } } @@ -648,8 +603,6 @@ static int dss_init(bool skip_init) return 0; -fail2: - free_irq(dss.dss_irq, NULL); fail1: iounmap(dss.base); fail0: @@ -661,8 +614,6 @@ static void dss_exit(void) if (cpu_is_omap34xx()) clk_put(dss.dpll4_m4_ck); - free_irq(dss.dss_irq, NULL); - iounmap(dss.base); } From 830e6384e100dc758392c41f68c807c002945928 Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Wed, 23 Feb 2011 16:34:17 +0200 Subject: [PATCH 024/140] MAINTAINERS: Update OMAP DSS maintainer Signed-off-by: Tomi Valkeinen --- MAINTAINERS | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 939e852ef74d..ee484254dcb5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4514,14 +4514,14 @@ S: Maintained F: sound/soc/omap/ OMAP FRAMEBUFFER SUPPORT -M: Tomi Valkeinen +M: Tomi Valkeinen L: linux-fbdev@vger.kernel.org L: linux-omap@vger.kernel.org S: Maintained F: drivers/video/omap/ OMAP DISPLAY SUBSYSTEM and FRAMEBUFFER SUPPORT (DSS2) -M: Tomi Valkeinen +M: Tomi Valkeinen L: linux-omap@vger.kernel.org L: linux-fbdev@vger.kernel.org S: Maintained From d0030452b5057570db47e953433f689e4a5475b5 Mon Sep 17 00:00:00 2001 From: Samreen Date: Thu, 24 Feb 2011 06:26:40 +0000 Subject: [PATCH 025/140] OMAP2/3/4: DSS2: Enable Display SubSystem as modules Enabling all the display interface options to be built as module And enabling all the display panels to be built as modules. Signed-off-by: Samreen Acked-by: Tony Lindgren Signed-off-by: Tomi Valkeinen --- arch/arm/configs/omap2plus_defconfig | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index 019fb7c67dc3..076db52ff672 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -193,6 +193,17 @@ CONFIG_FIRMWARE_EDID=y CONFIG_FB_MODE_HELPERS=y CONFIG_FB_TILEBLITTING=y CONFIG_FB_OMAP_LCD_VGA=y +CONFIG_OMAP2_DSS=m +CONFIG_OMAP2_DSS_RFBI=y +CONFIG_OMAP2_DSS_SDI=y +CONFIG_OMAP2_DSS_DSI=y +CONFIG_FB_OMAP2=m +CONFIG_PANEL_GENERIC_DPI=m +CONFIG_PANEL_SHARP_LS037V7DW01=m +CONFIG_PANEL_NEC_NL8048HL11_01B=m +CONFIG_PANEL_TAAL=m +CONFIG_PANEL_TPO_TD043MTEA1=m +CONFIG_PANEL_ACX565AKM=m CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_PLATFORM=y From e528e3a8b4e005e6e2c9e50fdee1ab7e84cf1e27 Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Thu, 24 Feb 2011 13:59:13 +0200 Subject: [PATCH 026/140] OMAP: DSS2: Clean up a switch-case Support for the display interface was checked in a separate switch-case. There's no reason for that, and this patch handles the fail code path in the same switch-case where the display initialization is done. Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/display.c | 27 +++------------------------ 1 file changed, 3 insertions(+), 24 deletions(-) diff --git a/drivers/video/omap2/dss/display.c b/drivers/video/omap2/dss/display.c index 22dd7a474f79..3f4fa0b08460 100644 --- a/drivers/video/omap2/dss/display.c +++ b/drivers/video/omap2/dss/display.c @@ -393,29 +393,6 @@ void dss_init_device(struct platform_device *pdev, int i; int r; - switch (dssdev->type) { -#ifdef CONFIG_OMAP2_DSS_DPI - case OMAP_DISPLAY_TYPE_DPI: -#endif -#ifdef CONFIG_OMAP2_DSS_RFBI - case OMAP_DISPLAY_TYPE_DBI: -#endif -#ifdef CONFIG_OMAP2_DSS_SDI - case OMAP_DISPLAY_TYPE_SDI: -#endif -#ifdef CONFIG_OMAP2_DSS_DSI - case OMAP_DISPLAY_TYPE_DSI: -#endif -#ifdef CONFIG_OMAP2_DSS_VENC - case OMAP_DISPLAY_TYPE_VENC: -#endif - break; - default: - DSSERR("Support for display '%s' not compiled in.\n", - dssdev->name); - return; - } - switch (dssdev->type) { #ifdef CONFIG_OMAP2_DSS_DPI case OMAP_DISPLAY_TYPE_DPI: @@ -443,7 +420,9 @@ void dss_init_device(struct platform_device *pdev, break; #endif default: - BUG(); + DSSERR("Support for display '%s' not compiled in.\n", + dssdev->name); + return; } if (r) { From 4e777dd765b7c10eb66532330cf3fe6ae0b477b0 Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Thu, 24 Feb 2011 14:20:31 +0200 Subject: [PATCH 027/140] OMAP: DSS2: FEATURES: Remove SDI from 3630 displays OMAP 3630 does not support SDI. Split omap3_dss_supported_displays into 3430 and 3630 entries, and remove the SDI from 3630 entry. Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dss_features.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/video/omap2/dss/dss_features.c b/drivers/video/omap2/dss/dss_features.c index cf3ef696e141..f4367f6564a2 100644 --- a/drivers/video/omap2/dss/dss_features.c +++ b/drivers/video/omap2/dss/dss_features.c @@ -73,7 +73,7 @@ static const enum omap_display_type omap2_dss_supported_displays[] = { OMAP_DISPLAY_TYPE_VENC, }; -static const enum omap_display_type omap3_dss_supported_displays[] = { +static const enum omap_display_type omap3430_dss_supported_displays[] = { /* OMAP_DSS_CHANNEL_LCD */ OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI | OMAP_DISPLAY_TYPE_SDI | OMAP_DISPLAY_TYPE_DSI, @@ -82,6 +82,15 @@ static const enum omap_display_type omap3_dss_supported_displays[] = { OMAP_DISPLAY_TYPE_VENC, }; +static const enum omap_display_type omap3630_dss_supported_displays[] = { + /* OMAP_DSS_CHANNEL_LCD */ + OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI | + OMAP_DISPLAY_TYPE_DSI, + + /* OMAP_DSS_CHANNEL_DIGIT */ + OMAP_DISPLAY_TYPE_VENC, +}; + static const enum omap_display_type omap4_dss_supported_displays[] = { /* OMAP_DSS_CHANNEL_LCD */ OMAP_DISPLAY_TYPE_DBI | OMAP_DISPLAY_TYPE_DSI, @@ -161,7 +170,7 @@ static struct omap_dss_features omap3430_dss_features = { .num_mgrs = 2, .num_ovls = 3, - .supported_displays = omap3_dss_supported_displays, + .supported_displays = omap3430_dss_supported_displays, .supported_color_modes = omap3_dss_supported_color_modes, }; @@ -176,7 +185,7 @@ static struct omap_dss_features omap3630_dss_features = { .num_mgrs = 2, .num_ovls = 3, - .supported_displays = omap3_dss_supported_displays, + .supported_displays = omap3630_dss_supported_displays, .supported_color_modes = omap3_dss_supported_color_modes, }; From f8df01f1a47ea6e503f5ba8d782fc6fb53bb40e8 Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Thu, 24 Feb 2011 14:21:25 +0200 Subject: [PATCH 028/140] OMAP: DSS2: FEATURES: Remove DSI & SDI from OMAP2 OMAP2 doesn't support SDI or DSI. Remove them from omap2_dss_supported_displays. Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dss_features.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/video/omap2/dss/dss_features.c b/drivers/video/omap2/dss/dss_features.c index f4367f6564a2..fe22d11068bd 100644 --- a/drivers/video/omap2/dss/dss_features.c +++ b/drivers/video/omap2/dss/dss_features.c @@ -66,8 +66,7 @@ static const struct dss_reg_field omap3_dss_reg_fields[] = { static const enum omap_display_type omap2_dss_supported_displays[] = { /* OMAP_DSS_CHANNEL_LCD */ - OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI | - OMAP_DISPLAY_TYPE_SDI | OMAP_DISPLAY_TYPE_DSI, + OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI, /* OMAP_DSS_CHANNEL_DIGIT */ OMAP_DISPLAY_TYPE_VENC, From 6ec549e50b192105ede7bb289a31da6f6e1a61e9 Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Thu, 24 Feb 2011 14:18:50 +0200 Subject: [PATCH 029/140] OMAP: DSS2: Check for SDI HW before accessing SDI registers Only OMAP 3430 hardware has SDI support. The availability of SDI HW can be found out by checking if the LCD channel supports SDI displays. This patch checks for SDI HW support before accessing SDI registers, which fixes a crash on OMAP4 when SDI SW support is compiled in. Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dss.c | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c index dc57100cc43d..50c18677684d 100644 --- a/drivers/video/omap2/dss/dss.c +++ b/drivers/video/omap2/dss/dss.c @@ -32,6 +32,7 @@ #include #include #include "dss.h" +#include "dss_features.h" #define DSS_SZ_REGS SZ_512 @@ -110,10 +111,11 @@ void dss_save_context(void) SR(SYSCONFIG); SR(CONTROL); -#ifdef CONFIG_OMAP2_DSS_SDI - SR(SDI_CONTROL); - SR(PLL_CONTROL); -#endif + if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) & + OMAP_DISPLAY_TYPE_SDI) { + SR(SDI_CONTROL); + SR(PLL_CONTROL); + } } void dss_restore_context(void) @@ -124,10 +126,11 @@ void dss_restore_context(void) RR(SYSCONFIG); RR(CONTROL); -#ifdef CONFIG_OMAP2_DSS_SDI - RR(SDI_CONTROL); - RR(PLL_CONTROL); -#endif + if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) & + OMAP_DISPLAY_TYPE_SDI) { + RR(SDI_CONTROL); + RR(PLL_CONTROL); + } } #undef SR @@ -259,9 +262,13 @@ void dss_dump_regs(struct seq_file *s) DUMPREG(DSS_SYSSTATUS); DUMPREG(DSS_IRQSTATUS); DUMPREG(DSS_CONTROL); - DUMPREG(DSS_SDI_CONTROL); - DUMPREG(DSS_PLL_CONTROL); - DUMPREG(DSS_SDI_STATUS); + + if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) & + OMAP_DISPLAY_TYPE_SDI) { + DUMPREG(DSS_SDI_CONTROL); + DUMPREG(DSS_PLL_CONTROL); + DUMPREG(DSS_SDI_STATUS); + } dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); #undef DUMPREG From 0897cc21036c4da0337d8ebcbe7d4b7bb81cf2ca Mon Sep 17 00:00:00 2001 From: "Janorkar, Mayuresh" Date: Thu, 24 Feb 2011 03:39:17 -0600 Subject: [PATCH 030/140] OMAP: OMAPFB: Adding help for FB_OMAP_LCD_VGA option CONFIG_FB_OMAP_LCD_VGA option is present in drivers/video/omap There is no explaination about what this flag does. Lets add information about it. FB_OMAP_LCD_VGA flag sets resolution of display to VGA (640 X 480). The default resolution of 3430 LDP is 320 X 240. Signed-off-by: Mayuresh Janorkar Signed-off-by: Tomi Valkeinen --- drivers/video/omap/Kconfig | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/video/omap/Kconfig b/drivers/video/omap/Kconfig index 083c8fe53e24..ff7049b2cc8f 100644 --- a/drivers/video/omap/Kconfig +++ b/drivers/video/omap/Kconfig @@ -11,7 +11,11 @@ config FB_OMAP config FB_OMAP_LCD_VGA bool "Use LCD in VGA mode" depends on MACH_OMAP_3430SDP || MACH_OMAP_LDP - + help + Set LCD resolution as VGA (640 X 480). + Default resolution without this option is QVGA(320 X 240). + Please take a look at drivers/video/omap/lcd_ldp.c file + for lcd driver code. choice depends on FB_OMAP && MACH_OVERO prompt "Screen resolution" From 4a0ab8df3e35da4d12df0631b2daae683dafe46c Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Thu, 28 Oct 2010 15:29:33 +0300 Subject: [PATCH 031/140] OMAP: DSS2: Remove unused list There was an unused list defined in display.c. Remove it. Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/display.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/video/omap2/dss/display.c b/drivers/video/omap2/dss/display.c index 3f4fa0b08460..7d96b724c992 100644 --- a/drivers/video/omap2/dss/display.c +++ b/drivers/video/omap2/dss/display.c @@ -25,14 +25,11 @@ #include #include #include -#include #include #include #include "dss.h" -static LIST_HEAD(display_list); - static ssize_t display_enabled_show(struct device *dev, struct device_attribute *attr, char *buf) { From 4b6b7fa2d3677d1d86780c73fe2284147713e3b1 Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Wed, 2 Jun 2010 15:09:37 +0300 Subject: [PATCH 032/140] OMAP: DSS2: DSI: remove unused function dsi_reset_tx_fifo() was not used. Furthermore, OMAP errata states that TX FIFO flush is not functional, so the function wouldn't even have worked. Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dsi.c | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c index 2f7d9491cd02..c3019d95618d 100644 --- a/drivers/video/omap2/dss/dsi.c +++ b/drivers/video/omap2/dss/dsi.c @@ -1626,20 +1626,6 @@ static int _dsi_reset(void) return _dsi_wait_reset(); } -static void dsi_reset_tx_fifo(int channel) -{ - u32 mask; - u32 l; - - /* set fifosize of the channel to 0, then return the old size */ - l = dsi_read_reg(DSI_TX_FIFO_VC_SIZE); - - mask = FLD_MASK((8 * channel) + 7, (8 * channel) + 4); - dsi_write_reg(DSI_TX_FIFO_VC_SIZE, l & ~mask); - - dsi_write_reg(DSI_TX_FIFO_VC_SIZE, l); -} - static void dsi_config_tx_fifo(enum fifo_size size1, enum fifo_size size2, enum fifo_size size3, enum fifo_size size4) { From fd4b34f60736a20c5acd81cbb3083a0c60ae058e Mon Sep 17 00:00:00 2001 From: "Semwal, Sumit" Date: Tue, 1 Mar 2011 02:42:13 -0600 Subject: [PATCH 033/140] OMAP2PLUS:DSS2: add opt_clock_available in pdata Provide a function in pdata to allow dss submodules to check if a given clock is available on a platform as an optional clock. Signed-off-by: Senthilvadivu Guruswamy (based on implementation from Senthil) Signed-off-by: Sumit Semwal Signed-off-by: Tomi Valkeinen --- arch/arm/mach-omap2/display.c | 22 ++++++++++++++++++++++ arch/arm/plat-omap/include/plat/display.h | 2 ++ 2 files changed, 24 insertions(+) diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c index 16d0db6718ae..256d23fb79ab 100644 --- a/arch/arm/mach-omap2/display.c +++ b/arch/arm/mach-omap2/display.c @@ -42,6 +42,20 @@ static struct omap_device_pm_latency omap_dss_latency[] = { }, }; +/* oh_core is used for getting opt-clocks */ +static struct omap_hwmod *oh_core; + +static bool opt_clock_available(const char *clk_role) +{ + int i; + + for (i = 0; i < oh_core->opt_clks_cnt; i++) { + if (!strcmp(oh_core->opt_clks[i].role, clk_role)) + return true; + } + return false; +} + int __init omap_display_init(struct omap_dss_board_info *board_data) { int r = 0; @@ -74,9 +88,16 @@ int __init omap_display_init(struct omap_dss_board_info *board_data) oh_count = ARRAY_SIZE(oh_name) - 2; /* last 2 hwmod dev in oh_name are not available for omap3 */ + /* opt_clks are always associated with dss hwmod */ + oh_core = omap_hwmod_lookup("dss_core"); + if (!oh_core) { + pr_err("Could not look up dss_core.\n"); + return -ENODEV; + } pdata.board_data = board_data; pdata.board_data->get_last_off_on_transaction_id = NULL; + pdata.opt_clock_available = opt_clock_available; for (i = 0; i < oh_count; i++) { oh = omap_hwmod_lookup(oh_name[i]); @@ -84,6 +105,7 @@ int __init omap_display_init(struct omap_dss_board_info *board_data) pr_err("Could not look up %s\n", oh_name[i]); return -ENODEV; } + od = omap_device_build(dev_name[i], -1, oh, &pdata, sizeof(struct omap_display_platform_data), omap_dss_latency, diff --git a/arch/arm/plat-omap/include/plat/display.h b/arch/arm/plat-omap/include/plat/display.h index 2fb057e1cb98..4101bcd2133e 100644 --- a/arch/arm/plat-omap/include/plat/display.h +++ b/arch/arm/plat-omap/include/plat/display.h @@ -240,6 +240,8 @@ static inline int omap_display_init(struct omap_dss_board_info *board_data) struct omap_display_platform_data { struct omap_dss_board_info *board_data; /* TODO: Additional members to be added when PM is considered */ + + bool (*opt_clock_available)(const char *clk_role); }; struct omap_video_timings { From a1a0dccaea9e036200dc0b1070af1bfae06690fb Mon Sep 17 00:00:00 2001 From: "Semwal, Sumit" Date: Tue, 1 Mar 2011 02:42:14 -0600 Subject: [PATCH 034/140] OMAP2PLUS:DSS2: Use opt_clock_available from pdata hwmod databases provide information about which optional clocks are available for a given platform. This is available via a function pointer opt_clock_enable in pdata. Use this information during get/enable/disable/put of clocks. Signed-off-by: Sumit Semwal Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dss.c | 46 +++++++++++++++++++++++------------ 1 file changed, 30 insertions(+), 16 deletions(-) diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c index 50c18677684d..0cf5f8bd1c8a 100644 --- a/drivers/video/omap2/dss/dss.c +++ b/drivers/video/omap2/dss/dss.c @@ -706,6 +706,7 @@ static int dss_get_clock(struct clk **clock, const char *clk_name) static int dss_get_clocks(void) { int r; + struct omap_display_platform_data *pdata = dss.pdev->dev.platform_data; dss.dss_ick = NULL; dss.dss_fck = NULL; @@ -721,17 +722,28 @@ static int dss_get_clocks(void) if (r) goto err; - r = dss_get_clock(&dss.dss_sys_clk, "sys_clk"); - if (r) + if (!pdata->opt_clock_available) { + r = -ENODEV; goto err; + } - r = dss_get_clock(&dss.dss_tv_fck, "tv_clk"); - if (r) - goto err; + if (pdata->opt_clock_available("sys_clk")) { + r = dss_get_clock(&dss.dss_sys_clk, "sys_clk"); + if (r) + goto err; + } - r = dss_get_clock(&dss.dss_video_fck, "video_clk"); - if (r) - goto err; + if (pdata->opt_clock_available("tv_clk")) { + r = dss_get_clock(&dss.dss_tv_fck, "tv_clk"); + if (r) + goto err; + } + + if (pdata->opt_clock_available("video_clk")) { + r = dss_get_clock(&dss.dss_video_fck, "video_clk"); + if (r) + goto err; + } return 0; @@ -754,9 +766,11 @@ static void dss_put_clocks(void) { if (dss.dss_video_fck) clk_put(dss.dss_video_fck); - clk_put(dss.dss_tv_fck); + if (dss.dss_tv_fck) + clk_put(dss.dss_tv_fck); + if (dss.dss_sys_clk) + clk_put(dss.dss_sys_clk); clk_put(dss.dss_fck); - clk_put(dss.dss_sys_clk); clk_put(dss.dss_ick); } @@ -805,11 +819,11 @@ static void dss_clk_enable_no_ctx(enum dss_clock clks) clk_enable(dss.dss_ick); if (clks & DSS_CLK_FCK) clk_enable(dss.dss_fck); - if (clks & DSS_CLK_SYSCK) + if ((clks & DSS_CLK_SYSCK) && dss.dss_sys_clk) clk_enable(dss.dss_sys_clk); - if (clks & DSS_CLK_TVFCK) + if ((clks & DSS_CLK_TVFCK) && dss.dss_tv_fck) clk_enable(dss.dss_tv_fck); - if (clks & DSS_CLK_VIDFCK) + if ((clks & DSS_CLK_VIDFCK) && dss.dss_video_fck) clk_enable(dss.dss_video_fck); dss.num_clks_enabled += num_clks; @@ -833,11 +847,11 @@ static void dss_clk_disable_no_ctx(enum dss_clock clks) clk_disable(dss.dss_ick); if (clks & DSS_CLK_FCK) clk_disable(dss.dss_fck); - if (clks & DSS_CLK_SYSCK) + if ((clks & DSS_CLK_SYSCK) && dss.dss_sys_clk) clk_disable(dss.dss_sys_clk); - if (clks & DSS_CLK_TVFCK) + if ((clks & DSS_CLK_TVFCK) && dss.dss_tv_fck) clk_disable(dss.dss_tv_fck); - if (clks & DSS_CLK_VIDFCK) + if ((clks & DSS_CLK_VIDFCK) && dss.dss_video_fck) clk_disable(dss.dss_video_fck); dss.num_clks_enabled -= num_clks; From 08a0a657949e723f0cbb6a33b1c706134d5a6d78 Mon Sep 17 00:00:00 2001 From: Jarkko Nikula Date: Tue, 1 Mar 2011 02:40:37 -0600 Subject: [PATCH 035/140] omapfb: Fix linker error in drivers/video/omap/lcd_2430sdp.c There is a linker error from lcd_2430sdp.c if CONFIG_TWL4030_CORE is not set. This can be triggered on OMAP2 builds when OMAP3 or OMAP4 are not set. drivers/built-in.o: In function `sdp2430_panel_disable': drivers/video/omap/lcd_2430sdp.c:123: undefined reference to `twl_i2c_write_u8' drivers/video/omap/lcd_2430sdp.c:124: undefined reference to `twl_i2c_write_u8' drivers/built-in.o: In function `sdp2430_panel_enable': drivers/video/omap/lcd_2430sdp.c:110: undefined reference to `twl_i2c_write_u8' drivers/video/omap/lcd_2430sdp.c:112: undefined reference to `twl_i2c_write_u8' Fix this by selecting the TWL4030_CORE for MACH_OMAP_2430SDP when building with CONFIG_FB_OMAP as there is no own Kconfig entry for lcd_2430 and it is compiled always when both MACH_OMAP_2430SDP and FB_OMAP are set. Signed-off-by: Jarkko Nikula Signed-off-by: Tomi Valkeinen --- drivers/video/omap/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/video/omap/Kconfig b/drivers/video/omap/Kconfig index ff7049b2cc8f..15e7f1912af9 100644 --- a/drivers/video/omap/Kconfig +++ b/drivers/video/omap/Kconfig @@ -5,6 +5,7 @@ config FB_OMAP select FB_CFB_FILLRECT select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT + select TWL4030_CORE if MACH_OMAP_2430SDP help Frame buffer driver for OMAP based boards. From 87a7484b6a9ceaa9e7a9a238154b02ed4495f26a Mon Sep 17 00:00:00 2001 From: Archit Taneja Date: Wed, 2 Mar 2011 11:19:50 +0530 Subject: [PATCH 036/140] OMAP2PLUS: DSS2: FEATURES: DISPC overlay code cleanup Add dss_features and register fields to incorporate changes in DISPC pipelines between OMAP3 and OMAP4. Register fields added: FEAT_REG_HORIZONTALACCU, FEAT_REG_VERTICALACCU DSS Features added: FEAT_LINEBUFFERSPLIT, FEAT_ROWREPEATENABLE, FEAT_RESIZECONF _dispc_set_scaling() and _dispc_set_rotation_attrs() have been cleaned up. Signed-off-by: Archit Taneja Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dispc.c | 54 ++++++++++++++++++-------- drivers/video/omap2/dss/dss_features.c | 30 +++++++++++--- drivers/video/omap2/dss/dss_features.h | 5 +++ 3 files changed, 67 insertions(+), 22 deletions(-) diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c index 43f7091c71cb..aa6479712d4c 100644 --- a/drivers/video/omap2/dss/dispc.c +++ b/drivers/video/omap2/dss/dispc.c @@ -1130,10 +1130,16 @@ static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu) u32 val; const struct dispc_reg ac0_reg[] = { DISPC_VID_ACCU0(0), DISPC_VID_ACCU0(1) }; + u8 hor_start, hor_end, vert_start, vert_end; BUG_ON(plane == OMAP_DSS_GFX); - val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0); + dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end); + dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end); + + val = FLD_VAL(vaccu, vert_start, vert_end) | + FLD_VAL(haccu, hor_start, hor_end); + dispc_write_reg(ac0_reg[plane-1], val); } @@ -1142,10 +1148,16 @@ static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu) u32 val; const struct dispc_reg ac1_reg[] = { DISPC_VID_ACCU1(0), DISPC_VID_ACCU1(1) }; + u8 hor_start, hor_end, vert_start, vert_end; BUG_ON(plane == OMAP_DSS_GFX); - val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0); + dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end); + dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end); + + val = FLD_VAL(vaccu, vert_start, vert_end) | + FLD_VAL(haccu, hor_start, hor_end); + dispc_write_reg(ac1_reg[plane-1], val); } @@ -1183,16 +1195,25 @@ static void _dispc_set_scaling(enum omap_plane plane, _dispc_set_fir(plane, fir_hinc, fir_vinc); l = dispc_read_reg(dispc_reg_att[plane]); - l &= ~((0x0f << 5) | (0x3 << 21)); + /* RESIZEENABLE and VERTICALTAPS */ + l &= ~((0x3 << 5) | (0x1 << 21)); l |= fir_hinc ? (1 << 5) : 0; l |= fir_vinc ? (1 << 6) : 0; - - l |= hscaleup ? 0 : (1 << 7); - l |= vscaleup ? 0 : (1 << 8); - l |= five_taps ? (1 << 21) : 0; - l |= five_taps ? (1 << 22) : 0; + + /* VRESIZECONF and HRESIZECONF */ + if (dss_has_feature(FEAT_RESIZECONF)) { + l &= ~(0x3 << 7); + l |= hscaleup ? 0 : (1 << 7); + l |= vscaleup ? 0 : (1 << 8); + } + + /* LINEBUFFERSPLIT */ + if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) { + l &= ~(0x1 << 22); + l |= five_taps ? (1 << 22) : 0; + } dispc_write_reg(dispc_reg_att[plane], l); @@ -1216,9 +1237,11 @@ static void _dispc_set_scaling(enum omap_plane plane, static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation, bool mirroring, enum omap_color_mode color_mode) { + bool row_repeat = false; + int vidrot = 0; + if (color_mode == OMAP_DSS_COLOR_YUV2 || color_mode == OMAP_DSS_COLOR_UYVY) { - int vidrot = 0; if (mirroring) { switch (rotation) { @@ -1252,16 +1275,15 @@ static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation, } } - REG_FLD_MOD(dispc_reg_att[plane], vidrot, 13, 12); - if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270) - REG_FLD_MOD(dispc_reg_att[plane], 0x1, 18, 18); + row_repeat = true; else - REG_FLD_MOD(dispc_reg_att[plane], 0x0, 18, 18); - } else { - REG_FLD_MOD(dispc_reg_att[plane], 0, 13, 12); - REG_FLD_MOD(dispc_reg_att[plane], 0, 18, 18); + row_repeat = false; } + + REG_FLD_MOD(dispc_reg_att[plane], vidrot, 13, 12); + if (dss_has_feature(FEAT_ROWREPEATENABLE)) + REG_FLD_MOD(dispc_reg_att[plane], row_repeat ? 1 : 0, 18, 18); } static int color_mode_to_bpp(enum omap_color_mode color_mode) diff --git a/drivers/video/omap2/dss/dss_features.c b/drivers/video/omap2/dss/dss_features.c index fe22d11068bd..679be14b73a8 100644 --- a/drivers/video/omap2/dss/dss_features.c +++ b/drivers/video/omap2/dss/dss_features.c @@ -54,6 +54,8 @@ static const struct dss_reg_field omap2_dss_reg_fields[] = { { FEAT_REG_FIFOLOWTHRESHOLD, 8, 0 }, { FEAT_REG_FIFOHIGHTHRESHOLD, 24, 16 }, { FEAT_REG_FIFOSIZE, 8, 0 }, + { FEAT_REG_HORIZONTALACCU, 9, 0 }, + { FEAT_REG_VERTICALACCU, 25, 16 }, }; static const struct dss_reg_field omap3_dss_reg_fields[] = { @@ -62,6 +64,18 @@ static const struct dss_reg_field omap3_dss_reg_fields[] = { { FEAT_REG_FIFOLOWTHRESHOLD, 11, 0 }, { FEAT_REG_FIFOHIGHTHRESHOLD, 27, 16 }, { FEAT_REG_FIFOSIZE, 10, 0 }, + { FEAT_REG_HORIZONTALACCU, 9, 0 }, + { FEAT_REG_VERTICALACCU, 25, 16 }, +}; + +static const struct dss_reg_field omap4_dss_reg_fields[] = { + { FEAT_REG_FIRHINC, 12, 0 }, + { FEAT_REG_FIRVINC, 28, 16 }, + { FEAT_REG_FIFOLOWTHRESHOLD, 15, 0 }, + { FEAT_REG_FIFOHIGHTHRESHOLD, 31, 16 }, + { FEAT_REG_FIFOSIZE, 15, 0 }, + { FEAT_REG_HORIZONTALACCU, 10, 0 }, + { FEAT_REG_VERTICALACCU, 26, 16 }, }; static const enum omap_display_type omap2_dss_supported_displays[] = { @@ -149,7 +163,8 @@ static struct omap_dss_features omap2_dss_features = { .has_feature = FEAT_LCDENABLEPOL | FEAT_LCDENABLESIGNAL | - FEAT_PCKFREEENABLE | FEAT_FUNCGATED, + FEAT_PCKFREEENABLE | FEAT_FUNCGATED | + FEAT_ROWREPEATENABLE | FEAT_RESIZECONF, .num_mgrs = 2, .num_ovls = 3, @@ -165,7 +180,8 @@ static struct omap_dss_features omap3430_dss_features = { .has_feature = FEAT_GLOBAL_ALPHA | FEAT_LCDENABLEPOL | FEAT_LCDENABLESIGNAL | FEAT_PCKFREEENABLE | - FEAT_FUNCGATED, + FEAT_FUNCGATED | FEAT_ROWREPEATENABLE | + FEAT_LINEBUFFERSPLIT | FEAT_RESIZECONF, .num_mgrs = 2, .num_ovls = 3, @@ -180,7 +196,9 @@ static struct omap_dss_features omap3630_dss_features = { .has_feature = FEAT_GLOBAL_ALPHA | FEAT_LCDENABLEPOL | FEAT_LCDENABLESIGNAL | FEAT_PCKFREEENABLE | - FEAT_PRE_MULT_ALPHA | FEAT_FUNCGATED, + FEAT_PRE_MULT_ALPHA | FEAT_FUNCGATED | + FEAT_ROWREPEATENABLE | FEAT_LINEBUFFERSPLIT | + FEAT_RESIZECONF, .num_mgrs = 2, .num_ovls = 3, @@ -190,12 +208,12 @@ static struct omap_dss_features omap3630_dss_features = { /* OMAP4 DSS Features */ static struct omap_dss_features omap4_dss_features = { - .reg_fields = omap3_dss_reg_fields, - .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields), + .reg_fields = omap4_dss_reg_fields, + .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields), .has_feature = FEAT_GLOBAL_ALPHA | FEAT_PRE_MULT_ALPHA | - FEAT_MGR_LCD2, + FEAT_MGR_LCD2 | FEAT_GLOBAL_ALPHA_VID1, .num_mgrs = 3, .num_ovls = 3, diff --git a/drivers/video/omap2/dss/dss_features.h b/drivers/video/omap2/dss/dss_features.h index b9c70be92588..b3f81415507c 100644 --- a/drivers/video/omap2/dss/dss_features.h +++ b/drivers/video/omap2/dss/dss_features.h @@ -33,6 +33,9 @@ enum dss_feat_id { FEAT_PCKFREEENABLE = 1 << 5, FEAT_FUNCGATED = 1 << 6, FEAT_MGR_LCD2 = 1 << 7, + FEAT_LINEBUFFERSPLIT = 1 << 8, + FEAT_ROWREPEATENABLE = 1 << 9, + FEAT_RESIZECONF = 1 << 10, }; /* DSS register field id */ @@ -42,6 +45,8 @@ enum dss_feat_reg_field { FEAT_REG_FIFOHIGHTHRESHOLD, FEAT_REG_FIFOLOWTHRESHOLD, FEAT_REG_FIFOSIZE, + FEAT_REG_HORIZONTALACCU, + FEAT_REG_VERTICALACCU, }; /* DSS Feature Functions */ From 819d807c59af10cce1dcbb13539c2fb100953fcd Mon Sep 17 00:00:00 2001 From: Archit Taneja Date: Tue, 1 Mar 2011 11:54:00 +0530 Subject: [PATCH 037/140] OMAP2PLUS: DSS2: FEATURES: Function to Provide the max fck supported The maximum supported frequency for DSS has increased from 173 to 186 Mhz on OMAP4. Introduce a dss feature function to get the max_fck to replace DISPC_MAX_FCK macro. Signed-off-by: Archit Taneja Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dsi.c | 9 ++++++--- drivers/video/omap2/dss/dss.c | 8 +++++--- drivers/video/omap2/dss/dss.h | 2 -- drivers/video/omap2/dss/dss_features.c | 11 +++++++++++ drivers/video/omap2/dss/dss_features.h | 1 + 5 files changed, 23 insertions(+), 8 deletions(-) diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c index c3019d95618d..705599ad3166 100644 --- a/drivers/video/omap2/dss/dsi.c +++ b/drivers/video/omap2/dss/dsi.c @@ -38,6 +38,7 @@ #include #include "dss.h" +#include "dss_features.h" /*#define VERBOSE_IRQ*/ #define DSI_CATCH_MISSING_TE @@ -856,10 +857,12 @@ int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck, struct dispc_clock_info best_dispc; int min_fck_per_pck; int match = 0; - unsigned long dss_clk_fck2; + unsigned long dss_clk_fck2, max_dss_fck; dss_clk_fck2 = dss_clk_get_rate(DSS_CLK_SYSCK); + max_dss_fck = dss_feat_get_max_dss_fck(); + if (req_pck == dsi.cache_req_pck && dsi.cache_cinfo.clkin == dss_clk_fck2) { DSSDBG("DSI clock info found from cache\n"); @@ -872,7 +875,7 @@ int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck, min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK; if (min_fck_per_pck && - req_pck * min_fck_per_pck > DISPC_MAX_FCK) { + req_pck * min_fck_per_pck > max_dss_fck) { DSSERR("Requested pixel clock not possible with the current " "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning " "the constraint off.\n"); @@ -925,7 +928,7 @@ retry: if (cur.dsi1_pll_fclk < req_pck) break; - if (cur.dsi1_pll_fclk > DISPC_MAX_FCK) + if (cur.dsi1_pll_fclk > max_dss_fck) continue; if (min_fck_per_pck && diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c index 0cf5f8bd1c8a..01be82a4f42f 100644 --- a/drivers/video/omap2/dss/dss.c +++ b/drivers/video/omap2/dss/dss.c @@ -387,7 +387,7 @@ int dss_calc_clock_div(bool is_tft, unsigned long req_pck, struct dss_clock_info best_dss; struct dispc_clock_info best_dispc; - unsigned long fck; + unsigned long fck, max_dss_fck; u16 fck_div; @@ -396,6 +396,8 @@ int dss_calc_clock_div(bool is_tft, unsigned long req_pck, prate = dss_get_dpll4_rate(); + max_dss_fck = dss_feat_get_max_dss_fck(); + fck = dss_clk_get_rate(DSS_CLK_FCK); if (req_pck == dss.cache_req_pck && ((cpu_is_omap34xx() && prate == dss.cache_prate) || @@ -409,7 +411,7 @@ int dss_calc_clock_div(bool is_tft, unsigned long req_pck, min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK; if (min_fck_per_pck && - req_pck * min_fck_per_pck > DISPC_MAX_FCK) { + req_pck * min_fck_per_pck > max_dss_fck) { DSSERR("Requested pixel clock not possible with the current " "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning " "the constraint off.\n"); @@ -445,7 +447,7 @@ retry: else fck = prate / fck_div * 2; - if (fck > DISPC_MAX_FCK) + if (fck > max_dss_fck) continue; if (min_fck_per_pck && diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h index 4b02e079f20e..7fe32d1647f9 100644 --- a/drivers/video/omap2/dss/dss.h +++ b/drivers/video/omap2/dss/dss.h @@ -97,8 +97,6 @@ extern unsigned int dss_debug; #define FLD_MOD(orig, val, start, end) \ (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end)) -#define DISPC_MAX_FCK 173000000 - enum omap_burst_size { OMAP_DSS_BURST_4x32 = 0, OMAP_DSS_BURST_8x32 = 1, diff --git a/drivers/video/omap2/dss/dss_features.c b/drivers/video/omap2/dss/dss_features.c index 679be14b73a8..3ebe0d91afd2 100644 --- a/drivers/video/omap2/dss/dss_features.c +++ b/drivers/video/omap2/dss/dss_features.c @@ -41,6 +41,7 @@ struct omap_dss_features { const int num_mgrs; const int num_ovls; + const unsigned long max_dss_fck; const enum omap_display_type *supported_displays; const enum omap_color_mode *supported_color_modes; }; @@ -168,6 +169,7 @@ static struct omap_dss_features omap2_dss_features = { .num_mgrs = 2, .num_ovls = 3, + .max_dss_fck = 173000000, .supported_displays = omap2_dss_supported_displays, .supported_color_modes = omap2_dss_supported_color_modes, }; @@ -185,6 +187,7 @@ static struct omap_dss_features omap3430_dss_features = { .num_mgrs = 2, .num_ovls = 3, + .max_dss_fck = 173000000, .supported_displays = omap3430_dss_supported_displays, .supported_color_modes = omap3_dss_supported_color_modes, }; @@ -202,6 +205,7 @@ static struct omap_dss_features omap3630_dss_features = { .num_mgrs = 2, .num_ovls = 3, + .max_dss_fck = 173000000, .supported_displays = omap3630_dss_supported_displays, .supported_color_modes = omap3_dss_supported_color_modes, }; @@ -217,6 +221,7 @@ static struct omap_dss_features omap4_dss_features = { .num_mgrs = 3, .num_ovls = 3, + .max_dss_fck = 186000000, .supported_displays = omap4_dss_supported_displays, .supported_color_modes = omap3_dss_supported_color_modes, }; @@ -232,6 +237,12 @@ int dss_feat_get_num_ovls(void) return omap_current_dss_features->num_ovls; } +/* Max supported DSS FCK in Hz */ +unsigned long dss_feat_get_max_dss_fck(void) +{ + return omap_current_dss_features->max_dss_fck; +} + enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel) { return omap_current_dss_features->supported_displays[channel]; diff --git a/drivers/video/omap2/dss/dss_features.h b/drivers/video/omap2/dss/dss_features.h index b3f81415507c..18ab19515817 100644 --- a/drivers/video/omap2/dss/dss_features.h +++ b/drivers/video/omap2/dss/dss_features.h @@ -52,6 +52,7 @@ enum dss_feat_reg_field { /* DSS Feature Functions */ int dss_feat_get_num_mgrs(void); int dss_feat_get_num_ovls(void); +unsigned long dss_feat_get_max_dss_fck(void); enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel); enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane); bool dss_feat_color_mode_supported(enum omap_plane plane, From 88134fa138b90518819b750891ffecc13f5f4886 Mon Sep 17 00:00:00 2001 From: Archit Taneja Date: Thu, 6 Jan 2011 10:44:10 +0530 Subject: [PATCH 038/140] OMAP2PLUS: DSS2: Make members of dss_clk_source generic The enum members of 'dss_clk_source' have clock source names specific to OMAP2/3. Change the names to more generic terms such that they now describe where the clocks come from and what they are used for. Also, change the enum member names to have "DSS_CLK_SRC" instead of "DSS_SRC" for more clarity. Signed-off-by: Archit Taneja Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dispc.c | 4 ++-- drivers/video/omap2/dss/dpi.c | 4 ++-- drivers/video/omap2/dss/dsi.c | 20 ++++++++++---------- drivers/video/omap2/dss/dss.c | 20 ++++++++++---------- drivers/video/omap2/dss/dss.h | 6 +++--- 5 files changed, 27 insertions(+), 27 deletions(-) diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c index aa6479712d4c..a06b2ea41e98 100644 --- a/drivers/video/omap2/dss/dispc.c +++ b/drivers/video/omap2/dss/dispc.c @@ -2334,7 +2334,7 @@ unsigned long dispc_fclk_rate(void) { unsigned long r = 0; - if (dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK) + if (dss_get_dispc_clk_source() == DSS_CLK_SRC_FCK) r = dss_clk_get_rate(DSS_CLK_FCK); else #ifdef CONFIG_OMAP2_DSS_DSI @@ -2385,7 +2385,7 @@ void dispc_dump_clocks(struct seq_file *s) seq_printf(s, "- DISPC -\n"); seq_printf(s, "dispc fclk source = %s\n", - dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ? + dss_get_dispc_clk_source() == DSS_CLK_SRC_FCK ? "dss1_alwon_fclk" : "dsi1_pll_fclk"); seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate()); diff --git a/drivers/video/omap2/dss/dpi.c b/drivers/video/omap2/dss/dpi.c index 026702b921e5..1b2867dfeeb9 100644 --- a/drivers/video/omap2/dss/dpi.c +++ b/drivers/video/omap2/dss/dpi.c @@ -57,7 +57,7 @@ static int dpi_set_dsi_clk(struct omap_dss_device *dssdev, bool is_tft, if (r) return r; - dss_select_dispc_clk_source(DSS_SRC_DSI1_PLL_FCLK); + dss_select_dispc_clk_source(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC); r = dispc_set_clock_div(dssdev->manager->id, &dispc_cinfo); if (r) @@ -217,7 +217,7 @@ void omapdss_dpi_display_disable(struct omap_dss_device *dssdev) dssdev->manager->disable(dssdev->manager); #ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL - dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK); + dss_select_dispc_clk_source(DSS_CLK_SRC_FCK); dsi_pll_uninit(); dss_clk_disable(DSS_CLK_SYSCK); #endif diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c index 705599ad3166..df35aed828da 100644 --- a/drivers/video/omap2/dss/dsi.c +++ b/drivers/video/omap2/dss/dsi.c @@ -731,7 +731,7 @@ static unsigned long dsi_fclk_rate(void) { unsigned long r; - if (dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK) { + if (dss_get_dsi_clk_source() == DSS_CLK_SRC_FCK) { /* DSI FCLK source is DSS1_ALWON_FCK, which is dss1_fck */ r = dss_clk_get_rate(DSS_CLK_FCK); } else { @@ -1188,19 +1188,19 @@ void dsi_dump_clocks(struct seq_file *s) seq_printf(s, "dsi1_pll_fck\t%-16luregm3 %u\t(%s)\n", cinfo->dsi1_pll_fclk, cinfo->regm3, - dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ? + dss_get_dispc_clk_source() == DSS_CLK_SRC_FCK ? "off" : "on"); seq_printf(s, "dsi2_pll_fck\t%-16luregm4 %u\t(%s)\n", cinfo->dsi2_pll_fclk, cinfo->regm4, - dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ? + dss_get_dsi_clk_source() == DSS_CLK_SRC_FCK ? "off" : "on"); seq_printf(s, "- DSI -\n"); seq_printf(s, "dsi fclk source = %s\n", - dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ? + dss_get_dsi_clk_source() == DSS_CLK_SRC_FCK ? "dss1_alwon_fclk" : "dsi2_pll_fclk"); seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate()); @@ -3038,8 +3038,8 @@ static int dsi_display_init_dsi(struct omap_dss_device *dssdev) if (r) goto err1; - dss_select_dispc_clk_source(DSS_SRC_DSI1_PLL_FCLK); - dss_select_dsi_clk_source(DSS_SRC_DSI2_PLL_FCLK); + dss_select_dispc_clk_source(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC); + dss_select_dsi_clk_source(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI); DSSDBG("PLL OK\n"); @@ -3075,8 +3075,8 @@ static int dsi_display_init_dsi(struct omap_dss_device *dssdev) err3: dsi_complexio_uninit(); err2: - dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK); - dss_select_dsi_clk_source(DSS_SRC_DSS1_ALWON_FCLK); + dss_select_dispc_clk_source(DSS_CLK_SRC_FCK); + dss_select_dsi_clk_source(DSS_CLK_SRC_FCK); err1: dsi_pll_uninit(); err0: @@ -3092,8 +3092,8 @@ static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev) dsi_vc_enable(2, 0); dsi_vc_enable(3, 0); - dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK); - dss_select_dsi_clk_source(DSS_SRC_DSS1_ALWON_FCLK); + dss_select_dispc_clk_source(DSS_CLK_SRC_FCK); + dss_select_dsi_clk_source(DSS_CLK_SRC_FCK); dsi_complexio_uninit(); dsi_pll_uninit(); } diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c index 01be82a4f42f..998c188c8823 100644 --- a/drivers/video/omap2/dss/dss.c +++ b/drivers/video/omap2/dss/dss.c @@ -278,12 +278,12 @@ void dss_select_dispc_clk_source(enum dss_clk_source clk_src) { int b; - BUG_ON(clk_src != DSS_SRC_DSI1_PLL_FCLK && - clk_src != DSS_SRC_DSS1_ALWON_FCLK); + BUG_ON(clk_src != DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC && + clk_src != DSS_CLK_SRC_FCK); - b = clk_src == DSS_SRC_DSS1_ALWON_FCLK ? 0 : 1; + b = clk_src == DSS_CLK_SRC_FCK ? 0 : 1; - if (clk_src == DSS_SRC_DSI1_PLL_FCLK) + if (clk_src == DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC) dsi_wait_dsi1_pll_active(); REG_FLD_MOD(DSS_CONTROL, b, 0, 0); /* DISPC_CLK_SWITCH */ @@ -295,12 +295,12 @@ void dss_select_dsi_clk_source(enum dss_clk_source clk_src) { int b; - BUG_ON(clk_src != DSS_SRC_DSI2_PLL_FCLK && - clk_src != DSS_SRC_DSS1_ALWON_FCLK); + BUG_ON(clk_src != DSS_CLK_SRC_DSI_PLL_HSDIV_DSI && + clk_src != DSS_CLK_SRC_FCK); - b = clk_src == DSS_SRC_DSS1_ALWON_FCLK ? 0 : 1; + b = clk_src == DSS_CLK_SRC_FCK ? 0 : 1; - if (clk_src == DSS_SRC_DSI2_PLL_FCLK) + if (clk_src == DSS_CLK_SRC_DSI_PLL_HSDIV_DSI) dsi_wait_dsi2_pll_active(); REG_FLD_MOD(DSS_CONTROL, b, 1, 1); /* DSI_CLK_SWITCH */ @@ -601,8 +601,8 @@ static int dss_init(bool skip_init) } } - dss.dsi_clk_source = DSS_SRC_DSS1_ALWON_FCLK; - dss.dispc_clk_source = DSS_SRC_DSS1_ALWON_FCLK; + dss.dsi_clk_source = DSS_CLK_SRC_FCK; + dss.dispc_clk_source = DSS_CLK_SRC_FCK; dss_save_context(); diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h index 7fe32d1647f9..a166ff36ec90 100644 --- a/drivers/video/omap2/dss/dss.h +++ b/drivers/video/omap2/dss/dss.h @@ -118,9 +118,9 @@ enum dss_clock { }; enum dss_clk_source { - DSS_SRC_DSI1_PLL_FCLK, - DSS_SRC_DSI2_PLL_FCLK, - DSS_SRC_DSS1_ALWON_FCLK, + DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* DSI1_PLL_FCLK */ + DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* DSI2_PLL_FCLK */ + DSS_CLK_SRC_FCK, /* DSS1_ALWON_FCLK */ }; struct dss_clock_info { From 067a57e48e302863eb2d5ac0900ae9ae65dbc8c3 Mon Sep 17 00:00:00 2001 From: Archit Taneja Date: Wed, 2 Mar 2011 11:57:25 +0530 Subject: [PATCH 039/140] OMAP2PLUS: DSS2: Use dss features to get clock source names of current OMAP Clock source names vary across OMAP2/3 and OMAP4, the clock source enum names have been made generic in the driver, but for purposes of debugging and dumping clock sources, it is better to preserve the actual TRM name of the clock. Introduce a dss feature function 'dss_feat_get_clk_source_name()' which returns a string with the TRM clock name for the current OMAP in use. The OMAP specific name is printed along the generic name within brackets. Signed-off-by: Archit Taneja Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dispc.c | 7 +++-- drivers/video/omap2/dss/dsi.c | 42 ++++++++++++++++++-------- drivers/video/omap2/dss/dss.c | 19 ++++++++++-- drivers/video/omap2/dss/dss.h | 7 +++++ drivers/video/omap2/dss/dss_features.c | 23 ++++++++++++++ drivers/video/omap2/dss/dss_features.h | 1 + 6 files changed, 81 insertions(+), 18 deletions(-) diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c index a06b2ea41e98..2c82d9a3df4b 100644 --- a/drivers/video/omap2/dss/dispc.c +++ b/drivers/video/omap2/dss/dispc.c @@ -2379,14 +2379,15 @@ unsigned long dispc_pclk_rate(enum omap_channel channel) void dispc_dump_clocks(struct seq_file *s) { int lcd, pcd; + enum dss_clk_source dispc_clk_src = dss_get_dispc_clk_source(); enable_clocks(1); seq_printf(s, "- DISPC -\n"); - seq_printf(s, "dispc fclk source = %s\n", - dss_get_dispc_clk_source() == DSS_CLK_SRC_FCK ? - "dss1_alwon_fclk" : "dsi1_pll_fclk"); + seq_printf(s, "dispc fclk source = %s (%s)\n", + dss_get_generic_clk_source_name(dispc_clk_src), + dss_feat_get_clk_source_name(dispc_clk_src)); seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate()); diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c index df35aed828da..3ef94227bbe7 100644 --- a/drivers/video/omap2/dss/dsi.c +++ b/drivers/video/omap2/dss/dsi.c @@ -1022,10 +1022,14 @@ int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo) DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4); - DSSDBG("regm3 = %d, dsi1_pll_fclk = %lu\n", - cinfo->regm3, cinfo->dsi1_pll_fclk); - DSSDBG("regm4 = %d, dsi2_pll_fclk = %lu\n", - cinfo->regm4, cinfo->dsi2_pll_fclk); + DSSDBG("regm3 = %d, %s (%s) = %lu\n", cinfo->regm3, + dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC), + dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC), + cinfo->dsi1_pll_fclk); + DSSDBG("regm4 = %d, %s (%s) = %lu\n", cinfo->regm4, + dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI), + dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI), + cinfo->dsi2_pll_fclk); REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */ @@ -1169,6 +1173,10 @@ void dsi_dump_clocks(struct seq_file *s) { int clksel; struct dsi_clock_info *cinfo = &dsi.current_cinfo; + enum dss_clk_source dispc_clk_src, dsi_clk_src; + + dispc_clk_src = dss_get_dispc_clk_source(); + dsi_clk_src = dss_get_dsi_clk_source(); enable_clocks(1); @@ -1185,23 +1193,27 @@ void dsi_dump_clocks(struct seq_file *s) seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n", cinfo->clkin4ddr, cinfo->regm); - seq_printf(s, "dsi1_pll_fck\t%-16luregm3 %u\t(%s)\n", + seq_printf(s, "%s (%s)\t%-16luregm3 %u\t(%s)\n", + dss_get_generic_clk_source_name(dispc_clk_src), + dss_feat_get_clk_source_name(dispc_clk_src), cinfo->dsi1_pll_fclk, cinfo->regm3, - dss_get_dispc_clk_source() == DSS_CLK_SRC_FCK ? + dispc_clk_src == DSS_CLK_SRC_FCK ? "off" : "on"); - seq_printf(s, "dsi2_pll_fck\t%-16luregm4 %u\t(%s)\n", + seq_printf(s, "%s (%s)\t%-16luregm4 %u\t(%s)\n", + dss_get_generic_clk_source_name(dsi_clk_src), + dss_feat_get_clk_source_name(dsi_clk_src), cinfo->dsi2_pll_fclk, cinfo->regm4, - dss_get_dsi_clk_source() == DSS_CLK_SRC_FCK ? + dsi_clk_src == DSS_CLK_SRC_FCK ? "off" : "on"); seq_printf(s, "- DSI -\n"); - seq_printf(s, "dsi fclk source = %s\n", - dss_get_dsi_clk_source() == DSS_CLK_SRC_FCK ? - "dss1_alwon_fclk" : "dsi2_pll_fclk"); + seq_printf(s, "dsi fclk source = %s (%s)\n", + dss_get_generic_clk_source_name(dsi_clk_src), + dss_feat_get_clk_source_name(dsi_clk_src)); seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate()); @@ -3235,13 +3247,17 @@ int dsi_init_display(struct omap_dss_device *dssdev) void dsi_wait_dsi1_pll_active(void) { if (wait_for_bit_change(DSI_PLL_STATUS, 7, 1) != 1) - DSSERR("DSI1 PLL clock not active\n"); + DSSERR("%s (%s) not active\n", + dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC), + dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC)); } void dsi_wait_dsi2_pll_active(void) { if (wait_for_bit_change(DSI_PLL_STATUS, 8, 1) != 1) - DSSERR("DSI2 PLL clock not active\n"); + DSSERR("%s (%s) not active\n", + dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI), + dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI)); } static int dsi_init(struct platform_device *pdev) diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c index 998c188c8823..d049598bb412 100644 --- a/drivers/video/omap2/dss/dss.c +++ b/drivers/video/omap2/dss/dss.c @@ -81,6 +81,12 @@ static struct { u32 ctx[DSS_SZ_REGS / sizeof(u32)]; } dss; +static const struct dss_clk_source_name dss_generic_clk_source_names[] = { + { DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, "DSI_PLL_HSDIV_DISPC" }, + { DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, "DSI_PLL_HSDIV_DSI" }, + { DSS_CLK_SRC_FCK, "DSS_FCK" }, +}; + static void dss_clk_enable_all_no_ctx(void); static void dss_clk_disable_all_no_ctx(void); static void dss_clk_enable_no_ctx(enum dss_clock clks); @@ -223,6 +229,11 @@ void dss_sdi_disable(void) REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ } +const char *dss_get_generic_clk_source_name(enum dss_clk_source clk_src) +{ + return dss_generic_clk_source_names[clk_src].clksrc_name; +} + void dss_dump_clocks(struct seq_file *s) { unsigned long dpll4_ck_rate; @@ -238,12 +249,16 @@ void dss_dump_clocks(struct seq_file *s) seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate); if (cpu_is_omap3630()) - seq_printf(s, "dss1_alwon_fclk = %lu / %lu = %lu\n", + seq_printf(s, "%s (%s) = %lu / %lu = %lu\n", + dss_get_generic_clk_source_name(DSS_CLK_SRC_FCK), + dss_feat_get_clk_source_name(DSS_CLK_SRC_FCK), dpll4_ck_rate, dpll4_ck_rate / dpll4_m4_ck_rate, dss_clk_get_rate(DSS_CLK_FCK)); else - seq_printf(s, "dss1_alwon_fclk = %lu / %lu * 2 = %lu\n", + seq_printf(s, "%s (%s) = %lu / %lu * 2 = %lu\n", + dss_get_generic_clk_source_name(DSS_CLK_SRC_FCK), + dss_feat_get_clk_source_name(DSS_CLK_SRC_FCK), dpll4_ck_rate, dpll4_ck_rate / dpll4_m4_ck_rate, dss_clk_get_rate(DSS_CLK_FCK)); diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h index a166ff36ec90..42ca70f2bfd5 100644 --- a/drivers/video/omap2/dss/dss.h +++ b/drivers/video/omap2/dss/dss.h @@ -123,6 +123,12 @@ enum dss_clk_source { DSS_CLK_SRC_FCK, /* DSS1_ALWON_FCLK */ }; +/* Correlates clock source name and dss_clk_source member */ +struct dss_clk_source_name { + enum dss_clk_source clksrc; + const char *clksrc_name; +}; + struct dss_clock_info { /* rates that we get with dividers below */ unsigned long fck; @@ -215,6 +221,7 @@ void dss_clk_enable(enum dss_clock clks); void dss_clk_disable(enum dss_clock clks); unsigned long dss_clk_get_rate(enum dss_clock clk); int dss_need_ctx_restore(void); +const char *dss_get_generic_clk_source_name(enum dss_clk_source clk_src); void dss_dump_clocks(struct seq_file *s); void dss_dump_regs(struct seq_file *s); diff --git a/drivers/video/omap2/dss/dss_features.c b/drivers/video/omap2/dss/dss_features.c index 3ebe0d91afd2..ccae57b34f5c 100644 --- a/drivers/video/omap2/dss/dss_features.c +++ b/drivers/video/omap2/dss/dss_features.c @@ -25,6 +25,7 @@ #include #include +#include "dss.h" #include "dss_features.h" /* Defines a generic omap register field */ @@ -44,6 +45,7 @@ struct omap_dss_features { const unsigned long max_dss_fck; const enum omap_display_type *supported_displays; const enum omap_color_mode *supported_color_modes; + const struct dss_clk_source_name *clksrc_names; }; /* This struct is assigned to one of the below during initialization */ @@ -157,6 +159,18 @@ static const enum omap_color_mode omap3_dss_supported_color_modes[] = { OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32, }; +static const struct dss_clk_source_name omap2_dss_clk_source_names[] = { + { DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, "N/A" }, + { DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, "N/A" }, + { DSS_CLK_SRC_FCK, "DSS_FCLK1" }, +}; + +static const struct dss_clk_source_name omap3_dss_clk_source_names[] = { + { DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, "DSI1_PLL_FCLK" }, + { DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, "DSI2_PLL_FCLK" }, + { DSS_CLK_SRC_FCK, "DSS1_ALWON_FCLK" }, +}; + /* OMAP2 DSS Features */ static struct omap_dss_features omap2_dss_features = { .reg_fields = omap2_dss_reg_fields, @@ -172,6 +186,7 @@ static struct omap_dss_features omap2_dss_features = { .max_dss_fck = 173000000, .supported_displays = omap2_dss_supported_displays, .supported_color_modes = omap2_dss_supported_color_modes, + .clksrc_names = omap2_dss_clk_source_names, }; /* OMAP3 DSS Features */ @@ -190,6 +205,7 @@ static struct omap_dss_features omap3430_dss_features = { .max_dss_fck = 173000000, .supported_displays = omap3430_dss_supported_displays, .supported_color_modes = omap3_dss_supported_color_modes, + .clksrc_names = omap3_dss_clk_source_names, }; static struct omap_dss_features omap3630_dss_features = { @@ -208,6 +224,7 @@ static struct omap_dss_features omap3630_dss_features = { .max_dss_fck = 173000000, .supported_displays = omap3630_dss_supported_displays, .supported_color_modes = omap3_dss_supported_color_modes, + .clksrc_names = omap3_dss_clk_source_names, }; /* OMAP4 DSS Features */ @@ -224,6 +241,7 @@ static struct omap_dss_features omap4_dss_features = { .max_dss_fck = 186000000, .supported_displays = omap4_dss_supported_displays, .supported_color_modes = omap3_dss_supported_color_modes, + .clksrc_names = omap3_dss_clk_source_names, }; /* Functions returning values related to a DSS feature */ @@ -260,6 +278,11 @@ bool dss_feat_color_mode_supported(enum omap_plane plane, color_mode; } +const char *dss_feat_get_clk_source_name(enum dss_clk_source id) +{ + return omap_current_dss_features->clksrc_names[id].clksrc_name; +} + /* DSS has_feature check */ bool dss_has_feature(enum dss_feat_id id) { diff --git a/drivers/video/omap2/dss/dss_features.h b/drivers/video/omap2/dss/dss_features.h index 18ab19515817..65d6de7e0feb 100644 --- a/drivers/video/omap2/dss/dss_features.h +++ b/drivers/video/omap2/dss/dss_features.h @@ -57,6 +57,7 @@ enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane); bool dss_feat_color_mode_supported(enum omap_plane plane, enum omap_color_mode color_mode); +const char *dss_feat_get_clk_source_name(enum dss_clk_source id); bool dss_has_feature(enum dss_feat_id id); void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end); From 1bb478350670fadf708d3cbd6137c32dfbe3fd5f Mon Sep 17 00:00:00 2001 From: Archit Taneja Date: Thu, 24 Feb 2011 14:17:30 +0530 Subject: [PATCH 040/140] OMAP2PLUS: DSS2: DSI: Generalize DSI PLL Clock Naming DSI PLL output clock names have been made more generic. The clock name describes what the source of the clock and what clock is used for. Some of DSI PLL parameters like dividers and DSI PLL source have also been made more generic. dsi1_pll_fclk and dsi2_pll_fclk have been changed as dsi_pll_hsdiv_dispc_clk and dsi_pll_hsdiv_dsi_clk respectively. Also, the hsdividers are now named regm_dispc and regm_dsi instead of regm3 and regm4. Functions and macros named on the basis of these clock names have also been made generic. Signed-off-by: Archit Taneja Signed-off-by: Tomi Valkeinen --- arch/arm/plat-omap/include/plat/display.h | 4 +- drivers/video/omap2/dss/dispc.c | 2 +- drivers/video/omap2/dss/dpi.c | 4 +- drivers/video/omap2/dss/dsi.c | 134 +++++++++++----------- drivers/video/omap2/dss/dss.c | 4 +- drivers/video/omap2/dss/dss.h | 20 ++-- 6 files changed, 87 insertions(+), 81 deletions(-) diff --git a/arch/arm/plat-omap/include/plat/display.h b/arch/arm/plat-omap/include/plat/display.h index 4101bcd2133e..37658249e483 100644 --- a/arch/arm/plat-omap/include/plat/display.h +++ b/arch/arm/plat-omap/include/plat/display.h @@ -403,8 +403,8 @@ struct omap_dss_device { struct { u16 regn; u16 regm; - u16 regm3; - u16 regm4; + u16 regm_dispc; + u16 regm_dsi; u16 lp_clk_div; diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c index 2c82d9a3df4b..9fb11c17623f 100644 --- a/drivers/video/omap2/dss/dispc.c +++ b/drivers/video/omap2/dss/dispc.c @@ -2338,7 +2338,7 @@ unsigned long dispc_fclk_rate(void) r = dss_clk_get_rate(DSS_CLK_FCK); else #ifdef CONFIG_OMAP2_DSS_DSI - r = dsi_get_dsi1_pll_rate(); + r = dsi_get_pll_hsdiv_dispc_rate(); #else BUG(); #endif diff --git a/drivers/video/omap2/dss/dpi.c b/drivers/video/omap2/dss/dpi.c index 1b2867dfeeb9..08fed3080c0a 100644 --- a/drivers/video/omap2/dss/dpi.c +++ b/drivers/video/omap2/dss/dpi.c @@ -63,7 +63,7 @@ static int dpi_set_dsi_clk(struct omap_dss_device *dssdev, bool is_tft, if (r) return r; - *fck = dsi_cinfo.dsi1_pll_fclk; + *fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk; *lck_div = dispc_cinfo.lck_div; *pck_div = dispc_cinfo.pck_div; @@ -271,7 +271,7 @@ int dpi_check_timings(struct omap_dss_device *dssdev, if (r) return r; - fck = dsi_cinfo.dsi1_pll_fclk; + fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk; lck_div = dispc_cinfo.lck_div; pck_div = dispc_cinfo.pck_div; } diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c index 3ef94227bbe7..37ffbb6ecf69 100644 --- a/drivers/video/omap2/dss/dsi.c +++ b/drivers/video/omap2/dss/dsi.c @@ -189,8 +189,8 @@ struct dsi_reg { u16 idx; }; #define FINT_MIN 750000 #define REGN_MAX (1 << 7) #define REGM_MAX ((1 << 11) - 1) -#define REGM3_MAX (1 << 4) -#define REGM4_MAX (1 << 4) +#define REGM_DISPC_MAX (1 << 4) +#define REGM_DSI_MAX (1 << 4) #define LP_DIV_MAX ((1 << 13) - 1) enum fifo_size { @@ -642,7 +642,7 @@ static void dsi_vc_disable_bta_irq(int channel) dsi_write_reg(DSI_VC_IRQENABLE(channel), l); } -/* DSI func clock. this could also be DSI2_PLL_FCLK */ +/* DSI func clock. this could also be dsi_pll_hsdiv_dsi_clk */ static inline void enable_clocks(bool enable) { if (enable) @@ -712,14 +712,14 @@ static inline int dsi_if_enable(bool enable) return 0; } -unsigned long dsi_get_dsi1_pll_rate(void) +unsigned long dsi_get_pll_hsdiv_dispc_rate(void) { - return dsi.current_cinfo.dsi1_pll_fclk; + return dsi.current_cinfo.dsi_pll_hsdiv_dispc_clk; } -static unsigned long dsi_get_dsi2_pll_rate(void) +static unsigned long dsi_get_pll_hsdiv_dsi_rate(void) { - return dsi.current_cinfo.dsi2_pll_fclk; + return dsi.current_cinfo.dsi_pll_hsdiv_dsi_clk; } static unsigned long dsi_get_txbyteclkhs(void) @@ -732,11 +732,11 @@ static unsigned long dsi_fclk_rate(void) unsigned long r; if (dss_get_dsi_clk_source() == DSS_CLK_SRC_FCK) { - /* DSI FCLK source is DSS1_ALWON_FCK, which is dss1_fck */ + /* DSI FCLK source is DSS_CLK_FCK */ r = dss_clk_get_rate(DSS_CLK_FCK); } else { - /* DSI FCLK source is DSI2_PLL_FCLK */ - r = dsi_get_dsi2_pll_rate(); + /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */ + r = dsi_get_pll_hsdiv_dsi_rate(); } return r; @@ -806,16 +806,16 @@ static int dsi_calc_clock_rates(struct omap_dss_device *dssdev, if (cinfo->regm == 0 || cinfo->regm > REGM_MAX) return -EINVAL; - if (cinfo->regm3 > REGM3_MAX) + if (cinfo->regm_dispc > REGM_DISPC_MAX) return -EINVAL; - if (cinfo->regm4 > REGM4_MAX) + if (cinfo->regm_dsi > REGM_DSI_MAX) return -EINVAL; - if (cinfo->use_dss2_fck) { + if (cinfo->use_sys_clk) { cinfo->clkin = dss_clk_get_rate(DSS_CLK_SYSCK); /* XXX it is unclear if highfreq should be used - * with DSS2_FCK source also */ + * with DSS_SYS_CLK source also */ cinfo->highfreq = 0; } else { cinfo->clkin = dispc_pclk_rate(dssdev->manager->id); @@ -836,15 +836,17 @@ static int dsi_calc_clock_rates(struct omap_dss_device *dssdev, if (cinfo->clkin4ddr > 1800 * 1000 * 1000) return -EINVAL; - if (cinfo->regm3 > 0) - cinfo->dsi1_pll_fclk = cinfo->clkin4ddr / cinfo->regm3; + if (cinfo->regm_dispc > 0) + cinfo->dsi_pll_hsdiv_dispc_clk = + cinfo->clkin4ddr / cinfo->regm_dispc; else - cinfo->dsi1_pll_fclk = 0; + cinfo->dsi_pll_hsdiv_dispc_clk = 0; - if (cinfo->regm4 > 0) - cinfo->dsi2_pll_fclk = cinfo->clkin4ddr / cinfo->regm4; + if (cinfo->regm_dsi > 0) + cinfo->dsi_pll_hsdiv_dsi_clk = + cinfo->clkin4ddr / cinfo->regm_dsi; else - cinfo->dsi2_pll_fclk = 0; + cinfo->dsi_pll_hsdiv_dsi_clk = 0; return 0; } @@ -857,18 +859,18 @@ int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck, struct dispc_clock_info best_dispc; int min_fck_per_pck; int match = 0; - unsigned long dss_clk_fck2, max_dss_fck; + unsigned long dss_sys_clk, max_dss_fck; - dss_clk_fck2 = dss_clk_get_rate(DSS_CLK_SYSCK); + dss_sys_clk = dss_clk_get_rate(DSS_CLK_SYSCK); max_dss_fck = dss_feat_get_max_dss_fck(); if (req_pck == dsi.cache_req_pck && - dsi.cache_cinfo.clkin == dss_clk_fck2) { + dsi.cache_cinfo.clkin == dss_sys_clk) { DSSDBG("DSI clock info found from cache\n"); *dsi_cinfo = dsi.cache_cinfo; - dispc_find_clk_divs(is_tft, req_pck, dsi_cinfo->dsi1_pll_fclk, - dispc_cinfo); + dispc_find_clk_divs(is_tft, req_pck, + dsi_cinfo->dsi_pll_hsdiv_dispc_clk, dispc_cinfo); return 0; } @@ -889,8 +891,8 @@ retry: memset(&best_dispc, 0, sizeof(best_dispc)); memset(&cur, 0, sizeof(cur)); - cur.clkin = dss_clk_fck2; - cur.use_dss2_fck = 1; + cur.clkin = dss_sys_clk; + cur.use_sys_clk = 1; cur.highfreq = 0; /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */ @@ -916,30 +918,32 @@ retry: if (cur.clkin4ddr > 1800 * 1000 * 1000) break; - /* DSI1_PLL_FCLK(MHz) = DSIPHY(MHz) / regm3 < 173MHz */ - for (cur.regm3 = 1; cur.regm3 < REGM3_MAX; - ++cur.regm3) { + /* dsi_pll_hsdiv_dispc_clk(MHz) = + * DSIPHY(MHz) / regm_dispc < 173MHz/186Mhz */ + for (cur.regm_dispc = 1; cur.regm_dispc < REGM_DISPC_MAX; + ++cur.regm_dispc) { struct dispc_clock_info cur_dispc; - cur.dsi1_pll_fclk = cur.clkin4ddr / cur.regm3; + cur.dsi_pll_hsdiv_dispc_clk = + cur.clkin4ddr / cur.regm_dispc; /* this will narrow down the search a bit, * but still give pixclocks below what was * requested */ - if (cur.dsi1_pll_fclk < req_pck) + if (cur.dsi_pll_hsdiv_dispc_clk < req_pck) break; - if (cur.dsi1_pll_fclk > max_dss_fck) + if (cur.dsi_pll_hsdiv_dispc_clk > max_dss_fck) continue; if (min_fck_per_pck && - cur.dsi1_pll_fclk < + cur.dsi_pll_hsdiv_dispc_clk < req_pck * min_fck_per_pck) continue; match = 1; dispc_find_clk_divs(is_tft, req_pck, - cur.dsi1_pll_fclk, + cur.dsi_pll_hsdiv_dispc_clk, &cur_dispc); if (abs(cur_dispc.pck - req_pck) < @@ -968,9 +972,9 @@ found: return -EINVAL; } - /* DSI2_PLL_FCLK (regm4) is not used */ - best.regm4 = 0; - best.dsi2_pll_fclk = 0; + /* dsi_pll_hsdiv_dsi_clk (regm_dsi) is not used */ + best.regm_dsi = 0; + best.dsi_pll_hsdiv_dsi_clk = 0; if (dsi_cinfo) *dsi_cinfo = best; @@ -994,18 +998,20 @@ int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo) dsi.current_cinfo.fint = cinfo->fint; dsi.current_cinfo.clkin4ddr = cinfo->clkin4ddr; - dsi.current_cinfo.dsi1_pll_fclk = cinfo->dsi1_pll_fclk; - dsi.current_cinfo.dsi2_pll_fclk = cinfo->dsi2_pll_fclk; + dsi.current_cinfo.dsi_pll_hsdiv_dispc_clk = + cinfo->dsi_pll_hsdiv_dispc_clk; + dsi.current_cinfo.dsi_pll_hsdiv_dsi_clk = + cinfo->dsi_pll_hsdiv_dsi_clk; dsi.current_cinfo.regn = cinfo->regn; dsi.current_cinfo.regm = cinfo->regm; - dsi.current_cinfo.regm3 = cinfo->regm3; - dsi.current_cinfo.regm4 = cinfo->regm4; + dsi.current_cinfo.regm_dispc = cinfo->regm_dispc; + dsi.current_cinfo.regm_dsi = cinfo->regm_dsi; DSSDBG("DSI Fint %ld\n", cinfo->fint); DSSDBG("clkin (%s) rate %ld, highfreq %d\n", - cinfo->use_dss2_fck ? "dss2_fck" : "pclkfree", + cinfo->use_sys_clk ? "dss_sys_clk" : "pclkfree", cinfo->clkin, cinfo->highfreq); @@ -1022,14 +1028,14 @@ int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo) DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4); - DSSDBG("regm3 = %d, %s (%s) = %lu\n", cinfo->regm3, + DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo->regm_dispc, dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC), dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC), - cinfo->dsi1_pll_fclk); - DSSDBG("regm4 = %d, %s (%s) = %lu\n", cinfo->regm4, + cinfo->dsi_pll_hsdiv_dispc_clk); + DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo->regm_dsi, dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI), dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI), - cinfo->dsi2_pll_fclk); + cinfo->dsi_pll_hsdiv_dsi_clk); REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */ @@ -1037,9 +1043,9 @@ int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo) l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */ l = FLD_MOD(l, cinfo->regn - 1, 7, 1); /* DSI_PLL_REGN */ l = FLD_MOD(l, cinfo->regm, 18, 8); /* DSI_PLL_REGM */ - l = FLD_MOD(l, cinfo->regm3 > 0 ? cinfo->regm3 - 1 : 0, + l = FLD_MOD(l, cinfo->regm_dispc > 0 ? cinfo->regm_dispc - 1 : 0, 22, 19); /* DSI_CLOCK_DIV */ - l = FLD_MOD(l, cinfo->regm4 > 0 ? cinfo->regm4 - 1 : 0, + l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0, 26, 23); /* DSIPROTO_CLOCK_DIV */ dsi_write_reg(DSI_PLL_CONFIGURATION1, l); @@ -1057,7 +1063,7 @@ int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo) l = dsi_read_reg(DSI_PLL_CONFIGURATION2); l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */ - l = FLD_MOD(l, cinfo->use_dss2_fck ? 0 : 1, + l = FLD_MOD(l, cinfo->use_sys_clk ? 0 : 1, 11, 11); /* DSI_PLL_CLKSEL */ l = FLD_MOD(l, cinfo->highfreq, 12, 12); /* DSI_PLL_HIGHFREQ */ @@ -1186,26 +1192,26 @@ void dsi_dump_clocks(struct seq_file *s) seq_printf(s, "dsi pll source = %s\n", clksel == 0 ? - "dss2_alwon_fclk" : "pclkfree"); + "dss_sys_clk" : "pclkfree"); seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn); seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n", cinfo->clkin4ddr, cinfo->regm); - seq_printf(s, "%s (%s)\t%-16luregm3 %u\t(%s)\n", + seq_printf(s, "%s (%s)\t%-16luregm_dispc %u\t(%s)\n", dss_get_generic_clk_source_name(dispc_clk_src), dss_feat_get_clk_source_name(dispc_clk_src), - cinfo->dsi1_pll_fclk, - cinfo->regm3, + cinfo->dsi_pll_hsdiv_dispc_clk, + cinfo->regm_dispc, dispc_clk_src == DSS_CLK_SRC_FCK ? "off" : "on"); - seq_printf(s, "%s (%s)\t%-16luregm4 %u\t(%s)\n", + seq_printf(s, "%s (%s)\t%-16luregm_dsi %u\t(%s)\n", dss_get_generic_clk_source_name(dsi_clk_src), dss_feat_get_clk_source_name(dsi_clk_src), - cinfo->dsi2_pll_fclk, - cinfo->regm4, + cinfo->dsi_pll_hsdiv_dsi_clk, + cinfo->regm_dsi, dsi_clk_src == DSS_CLK_SRC_FCK ? "off" : "on"); @@ -2989,12 +2995,12 @@ static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev) struct dsi_clock_info cinfo; int r; - /* we always use DSS2_FCK as input clock */ - cinfo.use_dss2_fck = true; + /* we always use DSS_CLK_SYSCK as input clock */ + cinfo.use_sys_clk = true; cinfo.regn = dssdev->phy.dsi.div.regn; cinfo.regm = dssdev->phy.dsi.div.regm; - cinfo.regm3 = dssdev->phy.dsi.div.regm3; - cinfo.regm4 = dssdev->phy.dsi.div.regm4; + cinfo.regm_dispc = dssdev->phy.dsi.div.regm_dispc; + cinfo.regm_dsi = dssdev->phy.dsi.div.regm_dsi; r = dsi_calc_clock_rates(dssdev, &cinfo); if (r) { DSSERR("Failed to calc dsi clocks\n"); @@ -3016,7 +3022,7 @@ static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev) int r; unsigned long long fck; - fck = dsi_get_dsi1_pll_rate(); + fck = dsi_get_pll_hsdiv_dispc_rate(); dispc_cinfo.lck_div = dssdev->phy.dsi.div.lck_div; dispc_cinfo.pck_div = dssdev->phy.dsi.div.pck_div; @@ -3244,7 +3250,7 @@ int dsi_init_display(struct omap_dss_device *dssdev) return 0; } -void dsi_wait_dsi1_pll_active(void) +void dsi_wait_pll_hsdiv_dispc_active(void) { if (wait_for_bit_change(DSI_PLL_STATUS, 7, 1) != 1) DSSERR("%s (%s) not active\n", @@ -3252,7 +3258,7 @@ void dsi_wait_dsi1_pll_active(void) dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC)); } -void dsi_wait_dsi2_pll_active(void) +void dsi_wait_pll_hsdiv_dsi_active(void) { if (wait_for_bit_change(DSI_PLL_STATUS, 8, 1) != 1) DSSERR("%s (%s) not active\n", diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c index d049598bb412..5c6805b3362d 100644 --- a/drivers/video/omap2/dss/dss.c +++ b/drivers/video/omap2/dss/dss.c @@ -299,7 +299,7 @@ void dss_select_dispc_clk_source(enum dss_clk_source clk_src) b = clk_src == DSS_CLK_SRC_FCK ? 0 : 1; if (clk_src == DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC) - dsi_wait_dsi1_pll_active(); + dsi_wait_pll_hsdiv_dispc_active(); REG_FLD_MOD(DSS_CONTROL, b, 0, 0); /* DISPC_CLK_SWITCH */ @@ -316,7 +316,7 @@ void dss_select_dsi_clk_source(enum dss_clk_source clk_src) b = clk_src == DSS_CLK_SRC_FCK ? 0 : 1; if (clk_src == DSS_CLK_SRC_DSI_PLL_HSDIV_DSI) - dsi_wait_dsi2_pll_active(); + dsi_wait_pll_hsdiv_dsi_active(); REG_FLD_MOD(DSS_CONTROL, b, 1, 1); /* DSI_CLK_SWITCH */ diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h index 42ca70f2bfd5..20590fb53c91 100644 --- a/drivers/video/omap2/dss/dss.h +++ b/drivers/video/omap2/dss/dss.h @@ -152,21 +152,21 @@ struct dsi_clock_info { unsigned long fint; unsigned long clkin4ddr; unsigned long clkin; - unsigned long dsi1_pll_fclk; - unsigned long dsi2_pll_fclk; + unsigned long dsi_pll_hsdiv_dispc_clk; /* DSI1_PLL_CLK */ + unsigned long dsi_pll_hsdiv_dsi_clk; /* DSI2_PLL_CLK */ unsigned long lp_clk; /* dividers */ u16 regn; u16 regm; - u16 regm3; - u16 regm4; + u16 regm_dispc; /* REGM3 */ + u16 regm_dsi; /* REGM4 */ u16 lp_clk_div; u8 highfreq; - bool use_dss2_fck; + bool use_sys_clk; }; struct seq_file; @@ -278,7 +278,7 @@ void dsi_restore_context(void); int dsi_init_display(struct omap_dss_device *display); void dsi_irq_handler(void); -unsigned long dsi_get_dsi1_pll_rate(void); +unsigned long dsi_get_pll_hsdiv_dispc_rate(void); int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo); int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck, struct dsi_clock_info *cinfo, @@ -289,8 +289,8 @@ void dsi_pll_uninit(void); void dsi_get_overlay_fifo_thresholds(enum omap_plane plane, u32 fifo_size, enum omap_burst_size *burst_size, u32 *fifo_low, u32 *fifo_high); -void dsi_wait_dsi1_pll_active(void); -void dsi_wait_dsi2_pll_active(void); +void dsi_wait_pll_hsdiv_dispc_active(void); +void dsi_wait_pll_hsdiv_dsi_active(void); #else static inline int dsi_init_platform_driver(void) { @@ -299,10 +299,10 @@ static inline int dsi_init_platform_driver(void) static inline void dsi_uninit_platform_driver(void) { } -static inline void dsi_wait_dsi1_pll_active(void) +static inline void dsi_wait_pll_hsdiv_dispc_active(void) { } -static inline void dsi_wait_dsi2_pll_active(void) +static inline void dsi_wait_pll_hsdiv_dsi_active(void) { } #endif From 42c9dee82129d965bc8ca02170150817317c0135 Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Wed, 2 Mar 2011 12:29:27 +0200 Subject: [PATCH 041/140] OMAP: DSS2: Remove FB_OMAP_BOOTLOADER_INIT support FB_OMAP_BOOTLOADER_INIT does not work, and it was only partially implemented for SDI. This patch removes support for FB_OMAP_BOOTLOADER_INIT to clean up the code and to remove any assumptions that FB_OMAP_BOOTLOADER_INIT would work. Proper implementation is much more complex, requiring early boot time register and clock handling to keep the DSS running. Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/core.c | 8 +------ drivers/video/omap2/dss/dss.c | 37 ++++++++++++------------------- drivers/video/omap2/dss/dss.h | 4 ++-- drivers/video/omap2/dss/sdi.c | 40 ++++++++-------------------------- 4 files changed, 26 insertions(+), 63 deletions(-) diff --git a/drivers/video/omap2/dss/core.c b/drivers/video/omap2/dss/core.c index bcf69a462b5f..02db5f1269ee 100644 --- a/drivers/video/omap2/dss/core.c +++ b/drivers/video/omap2/dss/core.c @@ -166,7 +166,6 @@ static inline void dss_uninitialize_debugfs(void) static int omap_dss_probe(struct platform_device *pdev) { struct omap_dss_board_info *pdata = pdev->dev.platform_data; - int skip_init = 0; int r; int i; @@ -210,13 +209,8 @@ static int omap_dss_probe(struct platform_device *pdev) goto err_venc; } -#ifdef CONFIG_FB_OMAP_BOOTLOADER_INIT - /* DISPC_CONTROL */ - if (omap_readl(0x48050440) & 1) /* LCD enabled? */ - skip_init = 1; -#endif if (cpu_is_omap34xx()) { - r = sdi_init(skip_init); + r = sdi_init(); if (r) { DSSERR("Failed to initialize SDI\n"); goto err_sdi; diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c index 5c6805b3362d..4025a14c5bc1 100644 --- a/drivers/video/omap2/dss/dss.c +++ b/drivers/video/omap2/dss/dss.c @@ -559,7 +559,7 @@ void dss_set_dac_pwrdn_bgz(bool enable) REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */ } -static int dss_init(bool skip_init) +static int dss_init(void) { int r; u32 rev; @@ -578,22 +578,20 @@ static int dss_init(bool skip_init) goto fail0; } - if (!skip_init) { - /* disable LCD and DIGIT output. This seems to fix the synclost - * problem that we get, if the bootloader starts the DSS and - * the kernel resets it */ - omap_writel(omap_readl(0x48050440) & ~0x3, 0x48050440); + /* disable LCD and DIGIT output. This seems to fix the synclost + * problem that we get, if the bootloader starts the DSS and + * the kernel resets it */ + omap_writel(omap_readl(0x48050440) & ~0x3, 0x48050440); - /* We need to wait here a bit, otherwise we sometimes start to - * get synclost errors, and after that only power cycle will - * restore DSS functionality. I have no idea why this happens. - * And we have to wait _before_ resetting the DSS, but after - * enabling clocks. - */ - msleep(50); + /* We need to wait here a bit, otherwise we sometimes start to + * get synclost errors, and after that only power cycle will + * restore DSS functionality. I have no idea why this happens. + * And we have to wait _before_ resetting the DSS, but after + * enabling clocks. + */ + msleep(50); - _omap_dss_reset(); - } + _omap_dss_reset(); /* autoidle */ REG_FLD_MOD(DSS_SYSCONFIG, 1, 0, 0); @@ -954,7 +952,6 @@ void dss_debug_dump_clocks(struct seq_file *s) static int omap_dsshw_probe(struct platform_device *pdev) { int r; - int skip_init = 0; dss.pdev = pdev; @@ -967,13 +964,7 @@ static int omap_dsshw_probe(struct platform_device *pdev) dss.ctx_id = dss_get_ctx_id(); DSSDBG("initial ctx id %u\n", dss.ctx_id); -#ifdef CONFIG_FB_OMAP_BOOTLOADER_INIT - /* DISPC_CONTROL */ - if (omap_readl(0x48050440) & 1) /* LCD enabled? */ - skip_init = 1; -#endif - - r = dss_init(skip_init); + r = dss_init(); if (r) { DSSERR("Failed to initialize DSS\n"); goto err_dss; diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h index 20590fb53c91..069fcc72331c 100644 --- a/drivers/video/omap2/dss/dss.h +++ b/drivers/video/omap2/dss/dss.h @@ -251,11 +251,11 @@ int dss_calc_clock_div(bool is_tft, unsigned long req_pck, /* SDI */ #ifdef CONFIG_OMAP2_DSS_SDI -int sdi_init(bool skip_init); +int sdi_init(void); void sdi_exit(void); int sdi_init_display(struct omap_dss_device *display); #else -static inline int sdi_init(bool skip_init) +static inline int sdi_init(void) { return 0; } diff --git a/drivers/video/omap2/dss/sdi.c b/drivers/video/omap2/dss/sdi.c index 9f10a0d9e760..54a53e648180 100644 --- a/drivers/video/omap2/dss/sdi.c +++ b/drivers/video/omap2/dss/sdi.c @@ -30,7 +30,6 @@ #include "dss.h" static struct { - bool skip_init; bool update_enabled; struct regulator *vdds_sdi_reg; } sdi; @@ -68,9 +67,7 @@ int omapdss_sdi_display_enable(struct omap_dss_device *dssdev) if (r) goto err1; - /* In case of skip_init sdi_init has already enabled the clocks */ - if (!sdi.skip_init) - dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); + dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); sdi_basic_init(dssdev); @@ -80,14 +77,8 @@ int omapdss_sdi_display_enable(struct omap_dss_device *dssdev) dispc_set_pol_freq(dssdev->manager->id, dssdev->panel.config, dssdev->panel.acbi, dssdev->panel.acb); - if (!sdi.skip_init) { - r = dss_calc_clock_div(1, t->pixel_clock * 1000, - &dss_cinfo, &dispc_cinfo); - } else { - r = dss_get_clock_div(&dss_cinfo); - r = dispc_get_clock_div(dssdev->manager->id, &dispc_cinfo); - } - + r = dss_calc_clock_div(1, t->pixel_clock * 1000, + &dss_cinfo, &dispc_cinfo); if (r) goto err2; @@ -116,18 +107,14 @@ int omapdss_sdi_display_enable(struct omap_dss_device *dssdev) if (r) goto err2; - if (!sdi.skip_init) { - dss_sdi_init(dssdev->phy.sdi.datapairs); - r = dss_sdi_enable(); - if (r) - goto err1; - mdelay(2); - } + dss_sdi_init(dssdev->phy.sdi.datapairs); + r = dss_sdi_enable(); + if (r) + goto err1; + mdelay(2); dssdev->manager->enable(dssdev->manager); - sdi.skip_init = 0; - return 0; err2: dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); @@ -173,17 +160,8 @@ int sdi_init_display(struct omap_dss_device *dssdev) return 0; } -int sdi_init(bool skip_init) +int sdi_init(void) { - /* we store this for first display enable, then clear it */ - sdi.skip_init = skip_init; - - /* - * Enable clocks already here, otherwise there would be a toggle - * of them until sdi_display_enable is called. - */ - if (skip_init) - dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); return 0; } From 277b2881c3c0d97e214487fbd677b0590fb4acf3 Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Wed, 2 Mar 2011 12:32:48 +0200 Subject: [PATCH 042/140] OMAP: DSS2: Remove pdev argument from dpi_init dpi_init() does not use the pdev argument for anything. Remove it. Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/core.c | 2 +- drivers/video/omap2/dss/dpi.c | 2 +- drivers/video/omap2/dss/dss.h | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/video/omap2/dss/core.c b/drivers/video/omap2/dss/core.c index 02db5f1269ee..acefe50209fc 100644 --- a/drivers/video/omap2/dss/core.c +++ b/drivers/video/omap2/dss/core.c @@ -191,7 +191,7 @@ static int omap_dss_probe(struct platform_device *pdev) goto err_rfbi; } - r = dpi_init(pdev); + r = dpi_init(); if (r) { DSSERR("Failed to initialize dpi\n"); goto err_dpi; diff --git a/drivers/video/omap2/dss/dpi.c b/drivers/video/omap2/dss/dpi.c index 08fed3080c0a..2d3ca4ca4a05 100644 --- a/drivers/video/omap2/dss/dpi.c +++ b/drivers/video/omap2/dss/dpi.c @@ -319,7 +319,7 @@ int dpi_init_display(struct omap_dss_device *dssdev) return 0; } -int dpi_init(struct platform_device *pdev) +int dpi_init(void) { return 0; } diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h index 069fcc72331c..85d4141689c1 100644 --- a/drivers/video/omap2/dss/dss.h +++ b/drivers/video/omap2/dss/dss.h @@ -309,11 +309,11 @@ static inline void dsi_wait_pll_hsdiv_dsi_active(void) /* DPI */ #ifdef CONFIG_OMAP2_DSS_DPI -int dpi_init(struct platform_device *pdev); +int dpi_init(void); void dpi_exit(void); int dpi_init_display(struct omap_dss_device *dssdev); #else -static inline int dpi_init(struct platform_device *pdev) +static inline int dpi_init(void) { return 0; } From 587b5e8269fab583e4e9d2d6bbdc77b289ac78a7 Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Wed, 2 Mar 2011 12:47:54 +0200 Subject: [PATCH 043/140] OMAP: DSS2: Move DPI & SDI init into DSS plat driver DPI and SDI are different from the other interfaces as they are not hwmods and there is not platform driver for them. They could be said to be a part of DSS or DISPC modules, although it's not a clear definition. This patch moves DPI and SDI initialization into DSS platform driver, making the code more consistent: omap_dss_probe() only initializes platform drivers now. Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/core.c | 19 ------------------- drivers/video/omap2/dss/dss.c | 17 ++++++++++++++++- 2 files changed, 16 insertions(+), 20 deletions(-) diff --git a/drivers/video/omap2/dss/core.c b/drivers/video/omap2/dss/core.c index acefe50209fc..8cfedae98211 100644 --- a/drivers/video/omap2/dss/core.c +++ b/drivers/video/omap2/dss/core.c @@ -191,12 +191,6 @@ static int omap_dss_probe(struct platform_device *pdev) goto err_rfbi; } - r = dpi_init(); - if (r) { - DSSERR("Failed to initialize dpi\n"); - goto err_dpi; - } - r = dispc_init_platform_driver(); if (r) { DSSERR("Failed to initialize dispc platform driver\n"); @@ -210,12 +204,6 @@ static int omap_dss_probe(struct platform_device *pdev) } if (cpu_is_omap34xx()) { - r = sdi_init(); - if (r) { - DSSERR("Failed to initialize SDI\n"); - goto err_sdi; - } - r = dsi_init_platform_driver(); if (r) { DSSERR("Failed to initialize DSI platform driver\n"); @@ -255,15 +243,10 @@ err_debugfs: if (cpu_is_omap34xx()) dsi_uninit_platform_driver(); err_dsi: - if (cpu_is_omap34xx()) - sdi_exit(); -err_sdi: venc_uninit_platform_driver(); err_venc: dispc_uninit_platform_driver(); err_dispc: - dpi_exit(); -err_dpi: rfbi_uninit_platform_driver(); err_rfbi: dss_uninit_platform_driver(); @@ -281,11 +264,9 @@ static int omap_dss_remove(struct platform_device *pdev) venc_uninit_platform_driver(); dispc_uninit_platform_driver(); - dpi_exit(); rfbi_uninit_platform_driver(); if (cpu_is_omap34xx()) { dsi_uninit_platform_driver(); - sdi_exit(); } dss_uninit_platform_driver(); diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c index 4025a14c5bc1..e5da050bcf85 100644 --- a/drivers/video/omap2/dss/dss.c +++ b/drivers/video/omap2/dss/dss.c @@ -970,9 +970,24 @@ static int omap_dsshw_probe(struct platform_device *pdev) goto err_dss; } + r = dpi_init(); + if (r) { + DSSERR("Failed to initialize DPI\n"); + goto err_dpi; + } + + r = sdi_init(); + if (r) { + DSSERR("Failed to initialize SDI\n"); + goto err_sdi; + } + dss_clk_disable_all_no_ctx(); return 0; - +err_sdi: + dpi_exit(); +err_dpi: + dss_exit(); err_dss: dss_clk_disable_all_no_ctx(); dss_put_clocks(); From 0a5835185420160f4fe8a6e1d1e42cd7efa07dc7 Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Wed, 2 Mar 2011 12:48:35 +0200 Subject: [PATCH 044/140] OMAP: DSS2: Remove unneeded cpu_is_xxx checks cpu_is_omapxxx() was used previously to select the supported interfaces. Now that the interfaces are platform devices, we no longer need to do the check when registering the driver. Thus we can just remove the checks. Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/core.c | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/drivers/video/omap2/dss/core.c b/drivers/video/omap2/dss/core.c index 8cfedae98211..c2f930bf2844 100644 --- a/drivers/video/omap2/dss/core.c +++ b/drivers/video/omap2/dss/core.c @@ -203,12 +203,10 @@ static int omap_dss_probe(struct platform_device *pdev) goto err_venc; } - if (cpu_is_omap34xx()) { - r = dsi_init_platform_driver(); - if (r) { - DSSERR("Failed to initialize DSI platform driver\n"); - goto err_dsi; - } + r = dsi_init_platform_driver(); + if (r) { + DSSERR("Failed to initialize DSI platform driver\n"); + goto err_dsi; } r = dss_initialize_debugfs(); @@ -240,8 +238,7 @@ static int omap_dss_probe(struct platform_device *pdev) err_register: dss_uninitialize_debugfs(); err_debugfs: - if (cpu_is_omap34xx()) - dsi_uninit_platform_driver(); + dsi_uninit_platform_driver(); err_dsi: venc_uninit_platform_driver(); err_venc: @@ -265,10 +262,7 @@ static int omap_dss_remove(struct platform_device *pdev) venc_uninit_platform_driver(); dispc_uninit_platform_driver(); rfbi_uninit_platform_driver(); - if (cpu_is_omap34xx()) { - dsi_uninit_platform_driver(); - } - + dsi_uninit_platform_driver(); dss_uninit_platform_driver(); dss_uninit_overlays(pdev); From 5ee3c1445dd89342ca8498c14afef82d0f76c794 Mon Sep 17 00:00:00 2001 From: Archit Taneja Date: Wed, 2 Mar 2011 12:35:53 +0530 Subject: [PATCH 045/140] OMAP: DSS2: Functions to request/release DSI VCs Introduce functions which request and release VC's. This will be used in panel drivers in their probes. omap_dsi_request_vc() takes in the pointer to the omap_dss_device, the VC_ID parameter which goes into the header of the DSI packets, and returns a Virtual channel number (or virtual channel register set) which it can use. omap_dsi_set_vc_id() takes the omap_dss_device pointer, the Virtual Channel number and the VC_ID that needs to be set for the specifed Virtual Channel. omap_dsi_release_vc() takes the omap_dss_device pointer and the Virtual Channel number that needs to be made free. Initialisation of VC parameters is done in dsi_init(). Signed-off-by: Archit Taneja Signed-off-by: Tomi Valkeinen --- arch/arm/plat-omap/include/plat/display.h | 3 + drivers/video/omap2/dss/dsi.c | 67 +++++++++++++++++++++-- 2 files changed, 65 insertions(+), 5 deletions(-) diff --git a/arch/arm/plat-omap/include/plat/display.h b/arch/arm/plat-omap/include/plat/display.h index 37658249e483..e81ca66dfbb4 100644 --- a/arch/arm/plat-omap/include/plat/display.h +++ b/arch/arm/plat-omap/include/plat/display.h @@ -562,6 +562,9 @@ int omap_dsi_update(struct omap_dss_device *dssdev, int channel, u16 x, u16 y, u16 w, u16 h, void (*callback)(int, void *), void *data); +int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel); +int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id); +void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel); int omapdss_dsi_display_enable(struct omap_dss_device *dssdev); void omapdss_dsi_display_disable(struct omap_dss_device *dssdev); diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c index 37ffbb6ecf69..fe3578bbff7d 100644 --- a/drivers/video/omap2/dss/dsi.c +++ b/drivers/video/omap2/dss/dsi.c @@ -233,6 +233,7 @@ static struct enum dsi_vc_mode mode; struct omap_dss_device *dssdev; enum fifo_size fifo_size; + int vc_id; } vc[4]; struct mutex lock; @@ -1764,8 +1765,6 @@ static void dsi_vc_initial_config(int channel) r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */ dsi_write_reg(DSI_VC_CTRL(channel), r); - - dsi.vc[channel].mode = DSI_VC_MODE_L4; } static int dsi_vc_config_l4(int channel) @@ -1972,7 +1971,7 @@ static inline void dsi_vc_write_long_header(int channel, u8 data_type, WARN_ON(!dsi_bus_is_locked()); - data_id = data_type | channel << 6; + data_id = data_type | dsi.vc[channel].vc_id << 6; val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) | FLD_VAL(ecc, 31, 24); @@ -2075,7 +2074,7 @@ static int dsi_vc_send_short(int channel, u8 data_type, u16 data, u8 ecc) return -EINVAL; } - data_id = data_type | channel << 6; + data_id = data_type | dsi.vc[channel].vc_id << 6; r = (data_id << 0) | (data << 8) | (ecc << 24); @@ -3250,6 +3249,57 @@ int dsi_init_display(struct omap_dss_device *dssdev) return 0; } +int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(dsi.vc); i++) { + if (!dsi.vc[i].dssdev) { + dsi.vc[i].dssdev = dssdev; + *channel = i; + return 0; + } + } + + DSSERR("cannot get VC for display %s", dssdev->name); + return -ENOSPC; +} +EXPORT_SYMBOL(omap_dsi_request_vc); + +int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id) +{ + if (vc_id < 0 || vc_id > 3) { + DSSERR("VC ID out of range\n"); + return -EINVAL; + } + + if (channel < 0 || channel > 3) { + DSSERR("Virtual Channel out of range\n"); + return -EINVAL; + } + + if (dsi.vc[channel].dssdev != dssdev) { + DSSERR("Virtual Channel not allocated to display %s\n", + dssdev->name); + return -EINVAL; + } + + dsi.vc[channel].vc_id = vc_id; + + return 0; +} +EXPORT_SYMBOL(omap_dsi_set_vc_id); + +void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel) +{ + if ((channel >= 0 && channel <= 3) && + dsi.vc[channel].dssdev == dssdev) { + dsi.vc[channel].dssdev = NULL; + dsi.vc[channel].vc_id = 0; + } +} +EXPORT_SYMBOL(omap_dsi_release_vc); + void dsi_wait_pll_hsdiv_dispc_active(void) { if (wait_for_bit_change(DSI_PLL_STATUS, 7, 1) != 1) @@ -3269,7 +3319,7 @@ void dsi_wait_pll_hsdiv_dsi_active(void) static int dsi_init(struct platform_device *pdev) { u32 rev; - int r; + int r, i; struct resource *dsi_mem; spin_lock_init(&dsi.errors_lock); @@ -3323,6 +3373,13 @@ static int dsi_init(struct platform_device *pdev) goto err2; } + /* DSI VCs initialization */ + for (i = 0; i < ARRAY_SIZE(dsi.vc); i++) { + dsi.vc[i].mode = DSI_VC_MODE_L4; + dsi.vc[i].dssdev = NULL; + dsi.vc[i].vc_id = 0; + } + enable_clocks(1); rev = dsi_read_reg(DSI_REVISION); From bc6d4b1d3d9b7568fe88f5bb80d0266a7ef624cc Mon Sep 17 00:00:00 2001 From: Archit Taneja Date: Tue, 1 Mar 2011 13:59:46 +0530 Subject: [PATCH 046/140] OMAP: DSS2: Use request / release calls in Taal for DSI Virtual Channels. Taal driver used to take a hard coded Macro for Virtual Channel and the VC_ID. The Taal panel driver now requests for a Virtual channel through the omap_dsi_request_vc() call in taal_probe(). The channel number returned by the request_vc() call is used for sending command and data to the Panel. The DSI driver automatically configures the Virtual Channel's source to either Video Port or L4 Slave port based on what the panel driver is using it for. The driver uses omap_dsi_release_vc() to free the VC specified by the panel. taal_remove() or when a request_vc() call fails. Signed-off-by: Archit Taneja Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/displays/panel-taal.c | 123 +++++++++++++--------- drivers/video/omap2/dss/dsi.c | 3 - 2 files changed, 71 insertions(+), 55 deletions(-) diff --git a/drivers/video/omap2/displays/panel-taal.c b/drivers/video/omap2/displays/panel-taal.c index 61026f96ad20..abdfdd81001f 100644 --- a/drivers/video/omap2/displays/panel-taal.c +++ b/drivers/video/omap2/displays/panel-taal.c @@ -218,6 +218,8 @@ struct taal_data { u16 w; u16 h; } update_region; + int channel; + struct delayed_work te_timeout_work; bool use_dsi_bl; @@ -257,12 +259,12 @@ static void hw_guard_wait(struct taal_data *td) } } -static int taal_dcs_read_1(u8 dcs_cmd, u8 *data) +static int taal_dcs_read_1(struct taal_data *td, u8 dcs_cmd, u8 *data) { int r; u8 buf[1]; - r = dsi_vc_dcs_read(TCH, dcs_cmd, buf, 1); + r = dsi_vc_dcs_read(td->channel, dcs_cmd, buf, 1); if (r < 0) return r; @@ -272,17 +274,17 @@ static int taal_dcs_read_1(u8 dcs_cmd, u8 *data) return 0; } -static int taal_dcs_write_0(u8 dcs_cmd) +static int taal_dcs_write_0(struct taal_data *td, u8 dcs_cmd) { - return dsi_vc_dcs_write(TCH, &dcs_cmd, 1); + return dsi_vc_dcs_write(td->channel, &dcs_cmd, 1); } -static int taal_dcs_write_1(u8 dcs_cmd, u8 param) +static int taal_dcs_write_1(struct taal_data *td, u8 dcs_cmd, u8 param) { u8 buf[2]; buf[0] = dcs_cmd; buf[1] = param; - return dsi_vc_dcs_write(TCH, buf, 2); + return dsi_vc_dcs_write(td->channel, buf, 2); } static int taal_sleep_in(struct taal_data *td) @@ -294,7 +296,7 @@ static int taal_sleep_in(struct taal_data *td) hw_guard_wait(td); cmd = DCS_SLEEP_IN; - r = dsi_vc_dcs_write_nosync(TCH, &cmd, 1); + r = dsi_vc_dcs_write_nosync(td->channel, &cmd, 1); if (r) return r; @@ -312,7 +314,7 @@ static int taal_sleep_out(struct taal_data *td) hw_guard_wait(td); - r = taal_dcs_write_0(DCS_SLEEP_OUT); + r = taal_dcs_write_0(td, DCS_SLEEP_OUT); if (r) return r; @@ -324,30 +326,30 @@ static int taal_sleep_out(struct taal_data *td) return 0; } -static int taal_get_id(u8 *id1, u8 *id2, u8 *id3) +static int taal_get_id(struct taal_data *td, u8 *id1, u8 *id2, u8 *id3) { int r; - r = taal_dcs_read_1(DCS_GET_ID1, id1); + r = taal_dcs_read_1(td, DCS_GET_ID1, id1); if (r) return r; - r = taal_dcs_read_1(DCS_GET_ID2, id2); + r = taal_dcs_read_1(td, DCS_GET_ID2, id2); if (r) return r; - r = taal_dcs_read_1(DCS_GET_ID3, id3); + r = taal_dcs_read_1(td, DCS_GET_ID3, id3); if (r) return r; return 0; } -static int taal_set_addr_mode(u8 rotate, bool mirror) +static int taal_set_addr_mode(struct taal_data *td, u8 rotate, bool mirror) { int r; u8 mode; int b5, b6, b7; - r = taal_dcs_read_1(DCS_READ_MADCTL, &mode); + r = taal_dcs_read_1(td, DCS_READ_MADCTL, &mode); if (r) return r; @@ -381,10 +383,11 @@ static int taal_set_addr_mode(u8 rotate, bool mirror) mode &= ~((1<<7) | (1<<6) | (1<<5)); mode |= (b7 << 7) | (b6 << 6) | (b5 << 5); - return taal_dcs_write_1(DCS_MEM_ACC_CTRL, mode); + return taal_dcs_write_1(td, DCS_MEM_ACC_CTRL, mode); } -static int taal_set_update_window(u16 x, u16 y, u16 w, u16 h) +static int taal_set_update_window(struct taal_data *td, + u16 x, u16 y, u16 w, u16 h) { int r; u16 x1 = x; @@ -399,7 +402,7 @@ static int taal_set_update_window(u16 x, u16 y, u16 w, u16 h) buf[3] = (x2 >> 8) & 0xff; buf[4] = (x2 >> 0) & 0xff; - r = dsi_vc_dcs_write_nosync(TCH, buf, sizeof(buf)); + r = dsi_vc_dcs_write_nosync(td->channel, buf, sizeof(buf)); if (r) return r; @@ -409,11 +412,11 @@ static int taal_set_update_window(u16 x, u16 y, u16 w, u16 h) buf[3] = (y2 >> 8) & 0xff; buf[4] = (y2 >> 0) & 0xff; - r = dsi_vc_dcs_write_nosync(TCH, buf, sizeof(buf)); + r = dsi_vc_dcs_write_nosync(td->channel, buf, sizeof(buf)); if (r) return r; - dsi_vc_send_bta_sync(TCH); + dsi_vc_send_bta_sync(td->channel); return r; } @@ -439,7 +442,7 @@ static int taal_bl_update_status(struct backlight_device *dev) if (td->use_dsi_bl) { if (td->enabled) { dsi_bus_lock(); - r = taal_dcs_write_1(DCS_BRIGHTNESS, level); + r = taal_dcs_write_1(td, DCS_BRIGHTNESS, level); dsi_bus_unlock(); } else { r = 0; @@ -502,7 +505,7 @@ static ssize_t taal_num_errors_show(struct device *dev, if (td->enabled) { dsi_bus_lock(); - r = taal_dcs_read_1(DCS_READ_NUM_ERRORS, &errors); + r = taal_dcs_read_1(td, DCS_READ_NUM_ERRORS, &errors); dsi_bus_unlock(); } else { r = -ENODEV; @@ -528,7 +531,7 @@ static ssize_t taal_hw_revision_show(struct device *dev, if (td->enabled) { dsi_bus_lock(); - r = taal_get_id(&id1, &id2, &id3); + r = taal_get_id(td, &id1, &id2, &id3); dsi_bus_unlock(); } else { r = -ENODEV; @@ -590,7 +593,7 @@ static ssize_t store_cabc_mode(struct device *dev, if (td->enabled) { dsi_bus_lock(); if (!td->cabc_broken) - taal_dcs_write_1(DCS_WRITE_CABC, i); + taal_dcs_write_1(td, DCS_WRITE_CABC, i); dsi_bus_unlock(); } @@ -774,14 +777,29 @@ static int taal_probe(struct omap_dss_device *dssdev) dev_dbg(&dssdev->dev, "Using GPIO TE\n"); } + r = omap_dsi_request_vc(dssdev, &td->channel); + if (r) { + dev_err(&dssdev->dev, "failed to get virtual channel\n"); + goto err_req_vc; + } + + r = omap_dsi_set_vc_id(dssdev, td->channel, TCH); + if (r) { + dev_err(&dssdev->dev, "failed to set VC_ID\n"); + goto err_vc_id; + } + r = sysfs_create_group(&dssdev->dev.kobj, &taal_attr_group); if (r) { dev_err(&dssdev->dev, "failed to create sysfs files\n"); - goto err_sysfs; + goto err_vc_id; } return 0; -err_sysfs: + +err_vc_id: + omap_dsi_release_vc(dssdev, td->channel); +err_req_vc: if (panel_data->use_ext_te) free_irq(gpio_to_irq(panel_data->ext_te_gpio), dssdev); err_irq: @@ -808,6 +826,7 @@ static void taal_remove(struct omap_dss_device *dssdev) dev_dbg(&dssdev->dev, "remove\n"); sysfs_remove_group(&dssdev->dev.kobj, &taal_attr_group); + omap_dsi_release_vc(dssdev, td->channel); if (panel_data->use_ext_te) { int gpio = panel_data->ext_te_gpio; @@ -846,13 +865,13 @@ static int taal_power_on(struct omap_dss_device *dssdev) taal_hw_reset(dssdev); - omapdss_dsi_vc_enable_hs(TCH, false); + omapdss_dsi_vc_enable_hs(td->channel, false); r = taal_sleep_out(td); if (r) goto err; - r = taal_get_id(&id1, &id2, &id3); + r = taal_get_id(td, &id1, &id2, &id3); if (r) goto err; @@ -861,30 +880,30 @@ static int taal_power_on(struct omap_dss_device *dssdev) (id2 == 0x00 || id2 == 0xff || id2 == 0x81)) td->cabc_broken = true; - r = taal_dcs_write_1(DCS_BRIGHTNESS, 0xff); + r = taal_dcs_write_1(td, DCS_BRIGHTNESS, 0xff); if (r) goto err; - r = taal_dcs_write_1(DCS_CTRL_DISPLAY, + r = taal_dcs_write_1(td, DCS_CTRL_DISPLAY, (1<<2) | (1<<5)); /* BL | BCTRL */ if (r) goto err; - r = taal_dcs_write_1(DCS_PIXEL_FORMAT, 0x7); /* 24bit/pixel */ + r = taal_dcs_write_1(td, DCS_PIXEL_FORMAT, 0x7); /* 24bit/pixel */ if (r) goto err; - r = taal_set_addr_mode(td->rotate, td->mirror); + r = taal_set_addr_mode(td, td->rotate, td->mirror); if (r) goto err; if (!td->cabc_broken) { - r = taal_dcs_write_1(DCS_WRITE_CABC, td->cabc_mode); + r = taal_dcs_write_1(td, DCS_WRITE_CABC, td->cabc_mode); if (r) goto err; } - r = taal_dcs_write_0(DCS_DISPLAY_ON); + r = taal_dcs_write_0(td, DCS_DISPLAY_ON); if (r) goto err; @@ -903,7 +922,7 @@ static int taal_power_on(struct omap_dss_device *dssdev) td->intro_printed = true; } - omapdss_dsi_vc_enable_hs(TCH, true); + omapdss_dsi_vc_enable_hs(td->channel, true); return 0; err: @@ -921,7 +940,7 @@ static void taal_power_off(struct omap_dss_device *dssdev) struct taal_data *td = dev_get_drvdata(&dssdev->dev); int r; - r = taal_dcs_write_0(DCS_DISPLAY_OFF); + r = taal_dcs_write_0(td, DCS_DISPLAY_OFF); if (!r) { r = taal_sleep_in(td); /* HACK: wait a bit so that the message goes through */ @@ -1089,7 +1108,7 @@ static irqreturn_t taal_te_isr(int irq, void *data) if (old) { cancel_delayed_work(&td->te_timeout_work); - r = omap_dsi_update(dssdev, TCH, + r = omap_dsi_update(dssdev, td->channel, td->update_region.x, td->update_region.y, td->update_region.w, @@ -1139,7 +1158,7 @@ static int taal_update(struct omap_dss_device *dssdev, if (r) goto err; - r = taal_set_update_window(x, y, w, h); + r = taal_set_update_window(td, x, y, w, h); if (r) goto err; @@ -1153,7 +1172,7 @@ static int taal_update(struct omap_dss_device *dssdev, msecs_to_jiffies(250)); atomic_set(&td->do_update, 1); } else { - r = omap_dsi_update(dssdev, TCH, x, y, w, h, + r = omap_dsi_update(dssdev, td->channel, x, y, w, h, taal_framedone_cb, dssdev); if (r) goto err; @@ -1191,9 +1210,9 @@ static int _taal_enable_te(struct omap_dss_device *dssdev, bool enable) int r; if (enable) - r = taal_dcs_write_1(DCS_TEAR_ON, 0); + r = taal_dcs_write_1(td, DCS_TEAR_ON, 0); else - r = taal_dcs_write_0(DCS_TEAR_OFF); + r = taal_dcs_write_0(td, DCS_TEAR_OFF); if (!panel_data->use_ext_te) omapdss_dsi_enable_te(dssdev, enable); @@ -1263,7 +1282,7 @@ static int taal_rotate(struct omap_dss_device *dssdev, u8 rotate) dsi_bus_lock(); if (td->enabled) { - r = taal_set_addr_mode(rotate, td->mirror); + r = taal_set_addr_mode(td, rotate, td->mirror); if (r) goto err; } @@ -1306,7 +1325,7 @@ static int taal_mirror(struct omap_dss_device *dssdev, bool enable) dsi_bus_lock(); if (td->enabled) { - r = taal_set_addr_mode(td->rotate, enable); + r = taal_set_addr_mode(td, td->rotate, enable); if (r) goto err; } @@ -1350,13 +1369,13 @@ static int taal_run_test(struct omap_dss_device *dssdev, int test_num) dsi_bus_lock(); - r = taal_dcs_read_1(DCS_GET_ID1, &id1); + r = taal_dcs_read_1(td, DCS_GET_ID1, &id1); if (r) goto err2; - r = taal_dcs_read_1(DCS_GET_ID2, &id2); + r = taal_dcs_read_1(td, DCS_GET_ID2, &id2); if (r) goto err2; - r = taal_dcs_read_1(DCS_GET_ID3, &id3); + r = taal_dcs_read_1(td, DCS_GET_ID3, &id3); if (r) goto err2; @@ -1404,9 +1423,9 @@ static int taal_memory_read(struct omap_dss_device *dssdev, else plen = 2; - taal_set_update_window(x, y, w, h); + taal_set_update_window(td, x, y, w, h); - r = dsi_vc_set_max_rx_packet_size(TCH, plen); + r = dsi_vc_set_max_rx_packet_size(td->channel, plen); if (r) goto err2; @@ -1414,7 +1433,7 @@ static int taal_memory_read(struct omap_dss_device *dssdev, u8 dcs_cmd = first ? 0x2e : 0x3e; first = 0; - r = dsi_vc_dcs_read(TCH, dcs_cmd, + r = dsi_vc_dcs_read(td->channel, dcs_cmd, buf + buf_used, size - buf_used); if (r < 0) { @@ -1440,7 +1459,7 @@ static int taal_memory_read(struct omap_dss_device *dssdev, r = buf_used; err3: - dsi_vc_set_max_rx_packet_size(TCH, 1); + dsi_vc_set_max_rx_packet_size(td->channel, 1); err2: dsi_bus_unlock(); err1: @@ -1466,7 +1485,7 @@ static void taal_esd_work(struct work_struct *work) dsi_bus_lock(); - r = taal_dcs_read_1(DCS_RDDSDR, &state1); + r = taal_dcs_read_1(td, DCS_RDDSDR, &state1); if (r) { dev_err(&dssdev->dev, "failed to read Taal status\n"); goto err; @@ -1479,7 +1498,7 @@ static void taal_esd_work(struct work_struct *work) goto err; } - r = taal_dcs_read_1(DCS_RDDSDR, &state2); + r = taal_dcs_read_1(td, DCS_RDDSDR, &state2); if (r) { dev_err(&dssdev->dev, "failed to read Taal status\n"); goto err; @@ -1495,7 +1514,7 @@ static void taal_esd_work(struct work_struct *work) /* Self-diagnostics result is also shown on TE GPIO line. We need * to re-enable TE after self diagnostics */ if (td->te_enabled && panel_data->use_ext_te) { - r = taal_dcs_write_1(DCS_TEAR_ON, 0); + r = taal_dcs_write_1(td, DCS_TEAR_ON, 0); if (r) goto err; } diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c index fe3578bbff7d..44b667b55ab8 100644 --- a/drivers/video/omap2/dss/dsi.c +++ b/drivers/video/omap2/dss/dsi.c @@ -3230,9 +3230,6 @@ int dsi_init_display(struct omap_dss_device *dssdev) dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE | OMAP_DSS_DISPLAY_CAP_TEAR_ELIM; - dsi.vc[0].dssdev = dssdev; - dsi.vc[1].dssdev = dssdev; - if (dsi.vdds_dsi_reg == NULL) { struct regulator *vdds_dsi; From f2988ab9f4a2bf5e24f37d20eab1aad6862953d3 Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Wed, 2 Mar 2011 10:06:48 +0200 Subject: [PATCH 047/140] HACK: OMAP: DSS2: Fix OMAP2_DSS_USE_DSI_PLL When using OMAP2_DSS_USE_DSI_PLL, which selects DSI PLL as source clock for DISPC, the DSI needs the vdds_dsi regulator. Latest regulator changes broke this, causing the the code to not acquire the regulator when using OMAP2_DSS_USE_DSI_PLL. This patch acquires the vdds_dsi regulator in dsi_pll_init(), fixing the issue. This is is just a quick hack to get the OMAP2_DSS_USE_DSI_PLL option working. There shouldn't be any other downside in this solution than some extra lines of code. OMAP2_DSS_USE_DSI_PLL is itself a big hack, and should be removed, and the feature itself should be implemented in a more sane way. However, the solution is not trivial, and people are using DSI PLL to get more exact pixel clocks, so this hack is an acceptable temporary solution for the time being. Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dsi.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c index 44b667b55ab8..be7694ff7ca7 100644 --- a/drivers/video/omap2/dss/dsi.c +++ b/drivers/video/omap2/dss/dsi.c @@ -1119,6 +1119,26 @@ int dsi_pll_init(struct omap_dss_device *dssdev, bool enable_hsclk, DSSDBG("PLL init\n"); +#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL + /* + * HACK: this is just a quick hack to get the USE_DSI_PLL + * option working. USE_DSI_PLL is itself a big hack, and + * should be removed. + */ + if (dsi.vdds_dsi_reg == NULL) { + struct regulator *vdds_dsi; + + vdds_dsi = regulator_get(&dsi.pdev->dev, "vdds_dsi"); + + if (IS_ERR(vdds_dsi)) { + DSSERR("can't get VDDS_DSI regulator\n"); + return PTR_ERR(vdds_dsi); + } + + dsi.vdds_dsi_reg = vdds_dsi; + } +#endif + enable_clocks(1); dsi_enable_pll_clock(1); From 85604b0a247615157cedfec46b9cbfde2884f80f Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Thu, 3 Mar 2011 13:16:23 +0200 Subject: [PATCH 048/140] HACK: OMAP: DSS2: add delay after enabling clocks On omap4 the registers may not be accessible right after enabling the clocks. At some point this will be handled by pm_runtime, but, for the time begin, adding a small delay after clk_enable() should make things work. Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dss.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c index e5da050bcf85..2be4d03ece43 100644 --- a/drivers/video/omap2/dss/dss.c +++ b/drivers/video/omap2/dss/dss.c @@ -850,6 +850,14 @@ void dss_clk_enable(enum dss_clock clks) dss_clk_enable_no_ctx(clks); + /* + * HACK: On omap4 the registers may not be accessible right after + * enabling the clocks. At some point this will be handled by + * pm_runtime, but for the time begin this should make things work. + */ + if (cpu_is_omap44xx() && check_ctx) + udelay(10); + if (check_ctx && cpu_is_omap34xx() && dss_need_ctx_restore()) restore_all_ctx(); } From 5c6366e14d9d4466ae34a1ccbc08dd8738909c1f Mon Sep 17 00:00:00 2001 From: "Murthy, Raghuveer" Date: Thu, 3 Mar 2011 09:27:58 -0600 Subject: [PATCH 049/140] OMAP: DSS2: Adding dss_features for independent core clk divider In OMAP3xxx DISPC_DIVISOR register has a logical clock divisor (lcd_div) field. The lcd_div is common, for deciding the DISPC core functional clock frequency, and the final pixel clock frequency for LCD display. In OMAP4, there are 2 LCD channels, hence two divisor registers, DISPC_DIVISOR1 and DISPC_DIVISOR2. Also, there is a third register DISPC_DIVISOR. The DISPC_DIVISOR in OMAP4 is used to configure lcd_div exclusively for core functional clock configuration. For pixel clock configuration of primary and secondary LCDs, lcd_div of DISPC_DIVISOR1 and DISPC_DIVISOR2 are used respectively Signed-off-by: Archit Taneja Signed-off-by: Raghuveer Murthy Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dss_features.c | 3 ++- drivers/video/omap2/dss/dss_features.h | 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/video/omap2/dss/dss_features.c b/drivers/video/omap2/dss/dss_features.c index ccae57b34f5c..dc170ad079f2 100644 --- a/drivers/video/omap2/dss/dss_features.c +++ b/drivers/video/omap2/dss/dss_features.c @@ -234,7 +234,8 @@ static struct omap_dss_features omap4_dss_features = { .has_feature = FEAT_GLOBAL_ALPHA | FEAT_PRE_MULT_ALPHA | - FEAT_MGR_LCD2 | FEAT_GLOBAL_ALPHA_VID1, + FEAT_MGR_LCD2 | FEAT_GLOBAL_ALPHA_VID1 | + FEAT_CORE_CLK_DIV, .num_mgrs = 3, .num_ovls = 3, diff --git a/drivers/video/omap2/dss/dss_features.h b/drivers/video/omap2/dss/dss_features.h index 65d6de7e0feb..569d1b295edd 100644 --- a/drivers/video/omap2/dss/dss_features.h +++ b/drivers/video/omap2/dss/dss_features.h @@ -36,6 +36,8 @@ enum dss_feat_id { FEAT_LINEBUFFERSPLIT = 1 << 8, FEAT_ROWREPEATENABLE = 1 << 9, FEAT_RESIZECONF = 1 << 10, + /* Independent core clk divider */ + FEAT_CORE_CLK_DIV = 1 << 11, }; /* DSS register field id */ From ce7fa5eb1e815e79e4dd5db42d0d1f8c9d96925b Mon Sep 17 00:00:00 2001 From: "Murthy, Raghuveer" Date: Thu, 3 Mar 2011 09:27:59 -0600 Subject: [PATCH 050/140] OMAP: DSS2: Renaming register macro DISPC_DIVISOR(ch) The OMAP4 DISPC_DIVISOR1 is backward compatible to OMAP3xxx DISPC_DIVISOR. However DISPC_DIVISOR is also provided in OMAP4, to control DISPC_CORE_CLK independent of Primary and Secondary display clocks. Renamed DISPC_DIVISOR(ch) to DISPC_DIVISORo(ch), to facilitate introduction of DISPC_DIVISOR register, which is specific for OMAP4. OMAP4 has 3 registers DISPC_DIVISOR, DISPC_DIVISOR1 and DISPC_DIVISOR2. Also updated, all the usages of DISPC_DIVISOR(ch) to DISPC_DIVISORo(ch). Use DISPC_DIVISORo(ch) when DISPC_DIVISOR1 or DISPC_DIVISOR2 has to be configured OMAP4 TRM uses DISPC_DIVISORo generically to refer to DISPC_DIVISOR1 and DISPC_DIVISOR2 Signed-off-by: Raghuveer Murthy Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dispc.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c index 9fb11c17623f..a3dff5ffdcbb 100644 --- a/drivers/video/omap2/dss/dispc.c +++ b/drivers/video/omap2/dss/dispc.c @@ -73,7 +73,7 @@ struct dispc_reg { u16 idx; }; #define DISPC_TIMING_H(ch) DISPC_REG(ch != 2 ? 0x0064 : 0x0400) #define DISPC_TIMING_V(ch) DISPC_REG(ch != 2 ? 0x0068 : 0x0404) #define DISPC_POL_FREQ(ch) DISPC_REG(ch != 2 ? 0x006C : 0x0408) -#define DISPC_DIVISOR(ch) DISPC_REG(ch != 2 ? 0x0070 : 0x040C) +#define DISPC_DIVISORo(ch) DISPC_REG(ch != 2 ? 0x0070 : 0x040C) #define DISPC_GLOBAL_ALPHA DISPC_REG(0x0074) #define DISPC_SIZE_DIG DISPC_REG(0x0078) #define DISPC_SIZE_LCD(ch) DISPC_REG(ch != 2 ? 0x007C : 0x03CC) @@ -128,6 +128,7 @@ struct dispc_reg { u16 idx; }; #define DISPC_VID_PRELOAD(n) DISPC_REG(0x230 + (n)*0x04) +#define DISPC_DIVISOR DISPC_REG(0x0804) #define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \ DISPC_IRQ_OCP_ERR | \ @@ -231,7 +232,7 @@ void dispc_save_context(void) SR(TIMING_H(0)); SR(TIMING_V(0)); SR(POL_FREQ(0)); - SR(DIVISOR(0)); + SR(DIVISORo(0)); SR(GLOBAL_ALPHA); SR(SIZE_DIG); SR(SIZE_LCD(0)); @@ -243,7 +244,7 @@ void dispc_save_context(void) SR(TIMING_H(2)); SR(TIMING_V(2)); SR(POL_FREQ(2)); - SR(DIVISOR(2)); + SR(DIVISORo(2)); SR(CONFIG2); } @@ -390,7 +391,7 @@ void dispc_restore_context(void) RR(TIMING_H(0)); RR(TIMING_V(0)); RR(POL_FREQ(0)); - RR(DIVISOR(0)); + RR(DIVISORo(0)); RR(GLOBAL_ALPHA); RR(SIZE_DIG); RR(SIZE_LCD(0)); @@ -401,7 +402,7 @@ void dispc_restore_context(void) RR(TIMING_H(2)); RR(TIMING_V(2)); RR(POL_FREQ(2)); - RR(DIVISOR(2)); + RR(DIVISORo(2)); RR(CONFIG2); } @@ -2316,7 +2317,7 @@ static void dispc_set_lcd_divisor(enum omap_channel channel, u16 lck_div, BUG_ON(pck_div < 2); enable_clocks(1); - dispc_write_reg(DISPC_DIVISOR(channel), + dispc_write_reg(DISPC_DIVISORo(channel), FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0)); enable_clocks(0); } @@ -2325,7 +2326,7 @@ static void dispc_get_lcd_divisor(enum omap_channel channel, int *lck_div, int *pck_div) { u32 l; - l = dispc_read_reg(DISPC_DIVISOR(channel)); + l = dispc_read_reg(DISPC_DIVISORo(channel)); *lck_div = FLD_GET(l, 23, 16); *pck_div = FLD_GET(l, 7, 0); } @@ -2351,7 +2352,7 @@ unsigned long dispc_lclk_rate(enum omap_channel channel) unsigned long r; u32 l; - l = dispc_read_reg(DISPC_DIVISOR(channel)); + l = dispc_read_reg(DISPC_DIVISORo(channel)); lcd = FLD_GET(l, 23, 16); @@ -2366,7 +2367,7 @@ unsigned long dispc_pclk_rate(enum omap_channel channel) unsigned long r; u32 l; - l = dispc_read_reg(DISPC_DIVISOR(channel)); + l = dispc_read_reg(DISPC_DIVISORo(channel)); lcd = FLD_GET(l, 23, 16); pcd = FLD_GET(l, 7, 0); @@ -2483,7 +2484,7 @@ void dispc_dump_regs(struct seq_file *s) DUMPREG(DISPC_TIMING_H(0)); DUMPREG(DISPC_TIMING_V(0)); DUMPREG(DISPC_POL_FREQ(0)); - DUMPREG(DISPC_DIVISOR(0)); + DUMPREG(DISPC_DIVISORo(0)); DUMPREG(DISPC_GLOBAL_ALPHA); DUMPREG(DISPC_SIZE_DIG); DUMPREG(DISPC_SIZE_LCD(0)); @@ -2495,7 +2496,7 @@ void dispc_dump_regs(struct seq_file *s) DUMPREG(DISPC_TIMING_H(2)); DUMPREG(DISPC_TIMING_V(2)); DUMPREG(DISPC_POL_FREQ(2)); - DUMPREG(DISPC_DIVISOR(2)); + DUMPREG(DISPC_DIVISORo(2)); DUMPREG(DISPC_SIZE_LCD(2)); } @@ -2737,8 +2738,8 @@ int dispc_get_clock_div(enum omap_channel channel, fck = dispc_fclk_rate(); - cinfo->lck_div = REG_GET(DISPC_DIVISOR(channel), 23, 16); - cinfo->pck_div = REG_GET(DISPC_DIVISOR(channel), 7, 0); + cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16); + cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0); cinfo->lck = fck / cinfo->lck_div; cinfo->pck = cinfo->lck / cinfo->pck_div; From 0cf35df353e8c36d4be0da2d7483896de599f397 Mon Sep 17 00:00:00 2001 From: "Murthy, Raghuveer" Date: Thu, 3 Mar 2011 09:28:00 -0600 Subject: [PATCH 051/140] OMAP4: DSS2: Using dss_features to set independent core clock divider Using dss_features to select independent core clock divider and setting it. Added the register used, to DISPC context save and restore group ----------------------------------------------------------------------- In OMAP4, the minimum DISPC_CORE_CLK required can be expressed as: DISPC_CORE_CLK >= max(PCLK1*HSCALE1, PCLK2*HSCALE2, ...) Where PCLKi is the pixel clock generated by MANAGERi and HSCALEi is the maximum horizontal downscaling done through MANAGERi Based on the usecase, core clk can be increased or decreased at runtime to save power. Such mechanism are not yet implemented. Hence, we set the core clock divisor to 1, to support maximum range of resolutions ------------------------------------------------------------------------ Signed-off-by: Raghuveer Murthy Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dispc.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c index a3dff5ffdcbb..dae9686fb437 100644 --- a/drivers/video/omap2/dss/dispc.c +++ b/drivers/video/omap2/dss/dispc.c @@ -375,6 +375,9 @@ void dispc_save_context(void) SR(VID_FIR_COEF_V(1, 7)); SR(VID_PRELOAD(1)); + + if (dss_has_feature(FEAT_CORE_CLK_DIV)) + SR(DIVISOR); } void dispc_restore_context(void) @@ -534,6 +537,9 @@ void dispc_restore_context(void) RR(VID_PRELOAD(1)); + if (dss_has_feature(FEAT_CORE_CLK_DIV)) + RR(DIVISOR); + /* enable last, because LCD & DIGIT enable are here */ RR(CONTROL); if (dss_has_feature(FEAT_MGR_LCD2)) @@ -2380,6 +2386,7 @@ unsigned long dispc_pclk_rate(enum omap_channel channel) void dispc_dump_clocks(struct seq_file *s) { int lcd, pcd; + u32 l; enum dss_clk_source dispc_clk_src = dss_get_dispc_clk_source(); enable_clocks(1); @@ -2392,6 +2399,14 @@ void dispc_dump_clocks(struct seq_file *s) seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate()); + if (dss_has_feature(FEAT_CORE_CLK_DIV)) { + seq_printf(s, "- DISPC-CORE-CLK -\n"); + l = dispc_read_reg(DISPC_DIVISOR); + lcd = FLD_GET(l, 23, 16); + + seq_printf(s, "lck\t\t%-16lulck div\t%u\n", + (dispc_fclk_rate()/lcd), lcd); + } seq_printf(s, "- LCD1 -\n"); dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd); @@ -3287,6 +3302,15 @@ static void _omap_dispc_initial_config(void) l = FLD_MOD(l, 1, 0, 0); /* AUTOIDLE */ dispc_write_reg(DISPC_SYSCONFIG, l); + /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */ + if (dss_has_feature(FEAT_CORE_CLK_DIV)) { + l = dispc_read_reg(DISPC_DIVISOR); + /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */ + l = FLD_MOD(l, 1, 0, 0); + l = FLD_MOD(l, 1, 23, 16); + dispc_write_reg(DISPC_DIVISOR, l); + } + /* FUNCGATED */ if (dss_has_feature(FEAT_FUNCGATED)) REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9); From b9cb0984a6e6a09a4bcdc11ebc9f0eb71e5b6c85 Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Fri, 4 Mar 2011 18:19:54 +0200 Subject: [PATCH 052/140] OMAP: DSS2: fix omap_dispc_register_isr() fail path Fix handling of error in omap_dispc_register_isr() in case there are no free isr slots available. Reported-by: Ben Tucker Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dispc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c index dae9686fb437..4a368c47700e 100644 --- a/drivers/video/omap2/dss/dispc.c +++ b/drivers/video/omap2/dss/dispc.c @@ -2831,6 +2831,9 @@ int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask) break; } + if (ret) + goto err; + _omap_dispc_set_irqs(); spin_unlock_irqrestore(&dispc.irq_lock, flags); From 7654b4d3f4d2e2bc5b60990fc121891b95b33be5 Mon Sep 17 00:00:00 2001 From: Steve Sakoman Date: Sat, 5 Mar 2011 07:58:38 -0600 Subject: [PATCH 053/140] OMAP: DSS2: Add support for LG Philips LB035Q02 panel This patch adds support for the Gumstix Palo35 expansion board which utilizes the 320 x 240 pixel LG.Philips LB035Q02 LCD Panel Signed-off-by: Steve Sakoman Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/displays/Kconfig | 6 + drivers/video/omap2/displays/Makefile | 1 + .../omap2/displays/panel-lgphilips-lb035q02.c | 279 ++++++++++++++++++ 3 files changed, 286 insertions(+) create mode 100644 drivers/video/omap2/displays/panel-lgphilips-lb035q02.c diff --git a/drivers/video/omap2/displays/Kconfig b/drivers/video/omap2/displays/Kconfig index 940cab394c2e..d18ad6b2372a 100644 --- a/drivers/video/omap2/displays/Kconfig +++ b/drivers/video/omap2/displays/Kconfig @@ -9,6 +9,12 @@ config PANEL_GENERIC_DPI Supports LCD Panel used in TI SDP3430 and EVM boards, OMAP3517 EVM boards and CM-T35. +config PANEL_LGPHILIPS_LB035Q02 + tristate "LG.Philips LB035Q02 LCD Panel" + depends on OMAP2_DSS && SPI + help + LCD Panel used on the Gumstix Overo Palo35 + config PANEL_SHARP_LS037V7DW01 tristate "Sharp LS037V7DW01 LCD Panel" depends on OMAP2_DSS diff --git a/drivers/video/omap2/displays/Makefile b/drivers/video/omap2/displays/Makefile index 861f0255ec6b..0f601ab3abf4 100644 --- a/drivers/video/omap2/displays/Makefile +++ b/drivers/video/omap2/displays/Makefile @@ -1,4 +1,5 @@ obj-$(CONFIG_PANEL_GENERIC_DPI) += panel-generic-dpi.o +obj-$(CONFIG_PANEL_LGPHILIPS_LB035Q02) += panel-lgphilips-lb035q02.o obj-$(CONFIG_PANEL_SHARP_LS037V7DW01) += panel-sharp-ls037v7dw01.o obj-$(CONFIG_PANEL_NEC_NL8048HL11_01B) += panel-nec-nl8048hl11-01b.o diff --git a/drivers/video/omap2/displays/panel-lgphilips-lb035q02.c b/drivers/video/omap2/displays/panel-lgphilips-lb035q02.c new file mode 100644 index 000000000000..271324db2436 --- /dev/null +++ b/drivers/video/omap2/displays/panel-lgphilips-lb035q02.c @@ -0,0 +1,279 @@ +/* + * LCD panel driver for LG.Philips LB035Q02 + * + * Author: Steve Sakoman + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include +#include +#include +#include + +#include + +struct lb035q02_data { + struct mutex lock; +}; + +static struct omap_video_timings lb035q02_timings = { + .x_res = 320, + .y_res = 240, + + .pixel_clock = 6500, + + .hsw = 2, + .hfp = 20, + .hbp = 68, + + .vsw = 2, + .vfp = 4, + .vbp = 18, +}; + +static int lb035q02_panel_power_on(struct omap_dss_device *dssdev) +{ + int r; + + if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) + return 0; + + r = omapdss_dpi_display_enable(dssdev); + if (r) + goto err0; + + if (dssdev->platform_enable) { + r = dssdev->platform_enable(dssdev); + if (r) + goto err1; + } + + return 0; +err1: + omapdss_dpi_display_disable(dssdev); +err0: + return r; +} + +static void lb035q02_panel_power_off(struct omap_dss_device *dssdev) +{ + if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE) + return; + + if (dssdev->platform_disable) + dssdev->platform_disable(dssdev); + + omapdss_dpi_display_disable(dssdev); +} + +static int lb035q02_panel_probe(struct omap_dss_device *dssdev) +{ + struct lb035q02_data *ld; + int r; + + dssdev->panel.config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS | + OMAP_DSS_LCD_IHS; + dssdev->panel.timings = lb035q02_timings; + + ld = kzalloc(sizeof(*ld), GFP_KERNEL); + if (!ld) { + r = -ENOMEM; + goto err; + } + mutex_init(&ld->lock); + dev_set_drvdata(&dssdev->dev, ld); + return 0; +err: + return r; +} + +static void lb035q02_panel_remove(struct omap_dss_device *dssdev) +{ + struct lb035q02_data *ld = dev_get_drvdata(&dssdev->dev); + + kfree(ld); +} + +static int lb035q02_panel_enable(struct omap_dss_device *dssdev) +{ + struct lb035q02_data *ld = dev_get_drvdata(&dssdev->dev); + int r; + + mutex_lock(&ld->lock); + + r = lb035q02_panel_power_on(dssdev); + if (r) + goto err; + dssdev->state = OMAP_DSS_DISPLAY_ACTIVE; + + mutex_unlock(&ld->lock); + return 0; +err: + mutex_unlock(&ld->lock); + return r; +} + +static void lb035q02_panel_disable(struct omap_dss_device *dssdev) +{ + struct lb035q02_data *ld = dev_get_drvdata(&dssdev->dev); + + mutex_lock(&ld->lock); + + lb035q02_panel_power_off(dssdev); + dssdev->state = OMAP_DSS_DISPLAY_DISABLED; + + mutex_unlock(&ld->lock); +} + +static int lb035q02_panel_suspend(struct omap_dss_device *dssdev) +{ + struct lb035q02_data *ld = dev_get_drvdata(&dssdev->dev); + + mutex_lock(&ld->lock); + + lb035q02_panel_power_off(dssdev); + dssdev->state = OMAP_DSS_DISPLAY_SUSPENDED; + + mutex_unlock(&ld->lock); + return 0; +} + +static int lb035q02_panel_resume(struct omap_dss_device *dssdev) +{ + struct lb035q02_data *ld = dev_get_drvdata(&dssdev->dev); + int r; + + mutex_lock(&ld->lock); + + r = lb035q02_panel_power_on(dssdev); + if (r) + goto err; + dssdev->state = OMAP_DSS_DISPLAY_ACTIVE; + + mutex_unlock(&ld->lock); + return 0; +err: + mutex_unlock(&ld->lock); + return r; +} + +static struct omap_dss_driver lb035q02_driver = { + .probe = lb035q02_panel_probe, + .remove = lb035q02_panel_remove, + + .enable = lb035q02_panel_enable, + .disable = lb035q02_panel_disable, + .suspend = lb035q02_panel_suspend, + .resume = lb035q02_panel_resume, + + .driver = { + .name = "lgphilips_lb035q02_panel", + .owner = THIS_MODULE, + }, +}; + +static int lb035q02_write_reg(struct spi_device *spi, u8 reg, u16 val) +{ + struct spi_message msg; + struct spi_transfer index_xfer = { + .len = 3, + .cs_change = 1, + }; + struct spi_transfer value_xfer = { + .len = 3, + }; + u8 buffer[16]; + + spi_message_init(&msg); + + /* register index */ + buffer[0] = 0x70; + buffer[1] = 0x00; + buffer[2] = reg & 0x7f; + index_xfer.tx_buf = buffer; + spi_message_add_tail(&index_xfer, &msg); + + /* register value */ + buffer[4] = 0x72; + buffer[5] = val >> 8; + buffer[6] = val; + value_xfer.tx_buf = buffer + 4; + spi_message_add_tail(&value_xfer, &msg); + + return spi_sync(spi, &msg); +} + +static void init_lb035q02_panel(struct spi_device *spi) +{ + /* Init sequence from page 28 of the lb035q02 spec */ + lb035q02_write_reg(spi, 0x01, 0x6300); + lb035q02_write_reg(spi, 0x02, 0x0200); + lb035q02_write_reg(spi, 0x03, 0x0177); + lb035q02_write_reg(spi, 0x04, 0x04c7); + lb035q02_write_reg(spi, 0x05, 0xffc0); + lb035q02_write_reg(spi, 0x06, 0xe806); + lb035q02_write_reg(spi, 0x0a, 0x4008); + lb035q02_write_reg(spi, 0x0b, 0x0000); + lb035q02_write_reg(spi, 0x0d, 0x0030); + lb035q02_write_reg(spi, 0x0e, 0x2800); + lb035q02_write_reg(spi, 0x0f, 0x0000); + lb035q02_write_reg(spi, 0x16, 0x9f80); + lb035q02_write_reg(spi, 0x17, 0x0a0f); + lb035q02_write_reg(spi, 0x1e, 0x00c1); + lb035q02_write_reg(spi, 0x30, 0x0300); + lb035q02_write_reg(spi, 0x31, 0x0007); + lb035q02_write_reg(spi, 0x32, 0x0000); + lb035q02_write_reg(spi, 0x33, 0x0000); + lb035q02_write_reg(spi, 0x34, 0x0707); + lb035q02_write_reg(spi, 0x35, 0x0004); + lb035q02_write_reg(spi, 0x36, 0x0302); + lb035q02_write_reg(spi, 0x37, 0x0202); + lb035q02_write_reg(spi, 0x3a, 0x0a0d); + lb035q02_write_reg(spi, 0x3b, 0x0806); +} + +static int __devinit lb035q02_panel_spi_probe(struct spi_device *spi) +{ + init_lb035q02_panel(spi); + return omap_dss_register_driver(&lb035q02_driver); +} + +static int __devexit lb035q02_panel_spi_remove(struct spi_device *spi) +{ + omap_dss_unregister_driver(&lb035q02_driver); + return 0; +} + +static struct spi_driver lb035q02_spi_driver = { + .driver = { + .name = "lgphilips_lb035q02_panel-spi", + .owner = THIS_MODULE, + }, + .probe = lb035q02_panel_spi_probe, + .remove = __devexit_p(lb035q02_panel_spi_remove), +}; + +static int __init lb035q02_panel_drv_init(void) +{ + return spi_register_driver(&lb035q02_spi_driver); +} + +static void __exit lb035q02_panel_drv_exit(void) +{ + spi_unregister_driver(&lb035q02_spi_driver); +} + +module_init(lb035q02_panel_drv_init); +module_exit(lb035q02_panel_drv_exit); +MODULE_LICENSE("GPL"); From 7b12d7b66bac4ff51aeea0029734b7a921cbe817 Mon Sep 17 00:00:00 2001 From: Steve Sakoman Date: Sat, 5 Mar 2011 07:58:39 -0600 Subject: [PATCH 054/140] OMAP: DSS2: Add DSS2 support for Overo This patch adds DSS2 support for DVI, S-video, the 480x272 Samsung LTE430WQ-F0C panel, and the 320x240 LG.Philips LB035Q02 panel. Signed-off-by: Steve Sakoman Signed-off-by: Tomi Valkeinen --- arch/arm/mach-omap2/board-overo.c | 237 +++++++++++++++++++++++++----- 1 file changed, 200 insertions(+), 37 deletions(-) diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index 60f8db31763c..d621ee8fec0c 100644 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include @@ -41,10 +42,14 @@ #include #include +#include +#include #include #include #include #include +#include +#include #include #include "mux.h" @@ -68,8 +73,6 @@ #if defined(CONFIG_TOUCHSCREEN_ADS7846) || \ defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) -#include -#include #include static struct omap2_mcspi_device_config ads7846_mcspi_config = { @@ -94,18 +97,6 @@ static struct ads7846_platform_data ads7846_config = { .keep_vref_on = 1, }; -static struct spi_board_info overo_spi_board_info[] __initdata = { - { - .modalias = "ads7846", - .bus_num = 1, - .chip_select = 0, - .max_speed_hz = 1500000, - .controller_data = &ads7846_mcspi_config, - .irq = OMAP_GPIO_IRQ(OVERO_GPIO_PENDOWN), - .platform_data = &ads7846_config, - } -}; - static void __init overo_ads7846_init(void) { if ((gpio_request(OVERO_GPIO_PENDOWN, "ADS7846_PENDOWN") == 0) && @@ -115,9 +106,6 @@ static void __init overo_ads7846_init(void) printk(KERN_ERR "could not obtain gpio for ADS7846_PENDOWN\n"); return; } - - spi_register_board_info(overo_spi_board_info, - ARRAY_SIZE(overo_spi_board_info)); } #else @@ -233,6 +221,137 @@ static inline void __init overo_init_smsc911x(void) static inline void __init overo_init_smsc911x(void) { return; } #endif +/* DSS */ +static int lcd_enabled; +static int dvi_enabled; + +#define OVERO_GPIO_LCD_EN 144 +#define OVERO_GPIO_LCD_BL 145 + +static void __init overo_display_init(void) +{ + if ((gpio_request(OVERO_GPIO_LCD_EN, "OVERO_GPIO_LCD_EN") == 0) && + (gpio_direction_output(OVERO_GPIO_LCD_EN, 1) == 0)) + gpio_export(OVERO_GPIO_LCD_EN, 0); + else + printk(KERN_ERR "could not obtain gpio for " + "OVERO_GPIO_LCD_EN\n"); + + if ((gpio_request(OVERO_GPIO_LCD_BL, "OVERO_GPIO_LCD_BL") == 0) && + (gpio_direction_output(OVERO_GPIO_LCD_BL, 1) == 0)) + gpio_export(OVERO_GPIO_LCD_BL, 0); + else + printk(KERN_ERR "could not obtain gpio for " + "OVERO_GPIO_LCD_BL\n"); +} + +static int overo_panel_enable_dvi(struct omap_dss_device *dssdev) +{ + if (lcd_enabled) { + printk(KERN_ERR "cannot enable DVI, LCD is enabled\n"); + return -EINVAL; + } + dvi_enabled = 1; + + return 0; +} + +static void overo_panel_disable_dvi(struct omap_dss_device *dssdev) +{ + dvi_enabled = 0; +} + +static struct panel_generic_dpi_data dvi_panel = { + .name = "generic", + .platform_enable = overo_panel_enable_dvi, + .platform_disable = overo_panel_disable_dvi, +}; + +static struct omap_dss_device overo_dvi_device = { + .name = "dvi", + .type = OMAP_DISPLAY_TYPE_DPI, + .driver_name = "generic_dpi_panel", + .data = &dvi_panel, + .phy.dpi.data_lines = 24, +}; + +static struct omap_dss_device overo_tv_device = { + .name = "tv", + .driver_name = "venc", + .type = OMAP_DISPLAY_TYPE_VENC, + .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, +}; + +static int overo_panel_enable_lcd(struct omap_dss_device *dssdev) +{ + if (dvi_enabled) { + printk(KERN_ERR "cannot enable LCD, DVI is enabled\n"); + return -EINVAL; + } + + gpio_set_value(OVERO_GPIO_LCD_EN, 1); + gpio_set_value(OVERO_GPIO_LCD_BL, 1); + lcd_enabled = 1; + return 0; +} + +static void overo_panel_disable_lcd(struct omap_dss_device *dssdev) +{ + gpio_set_value(OVERO_GPIO_LCD_EN, 0); + gpio_set_value(OVERO_GPIO_LCD_BL, 0); + lcd_enabled = 0; +} + +static struct panel_generic_dpi_data lcd43_panel = { + .name = "samsung_lte430wq_f0c", + .platform_enable = overo_panel_enable_lcd, + .platform_disable = overo_panel_disable_lcd, +}; + +static struct omap_dss_device overo_lcd43_device = { + .name = "lcd43", + .type = OMAP_DISPLAY_TYPE_DPI, + .driver_name = "generic_dpi_panel", + .data = &lcd43_panel, + .phy.dpi.data_lines = 24, +}; + +#if defined(CONFIG_PANEL_LGPHILIPS_LB035Q02) || \ + defined(CONFIG_PANEL_LGPHILIPS_LB035Q02_MODULE) +static struct omap_dss_device overo_lcd35_device = { + .type = OMAP_DISPLAY_TYPE_DPI, + .name = "lcd35", + .driver_name = "lgphilips_lb035q02_panel", + .phy.dpi.data_lines = 24, + .platform_enable = overo_panel_enable_lcd, + .platform_disable = overo_panel_disable_lcd, +}; +#endif + +static struct omap_dss_device *overo_dss_devices[] = { + &overo_dvi_device, + &overo_tv_device, +#if defined(CONFIG_PANEL_LGPHILIPS_LB035Q02) || \ + defined(CONFIG_PANEL_LGPHILIPS_LB035Q02_MODULE) + &overo_lcd35_device, +#endif + &overo_lcd43_device, +}; + +static struct omap_dss_board_info overo_dss_data = { + .num_devices = ARRAY_SIZE(overo_dss_devices), + .devices = overo_dss_devices, + .default_device = &overo_dvi_device, +}; + +static struct regulator_consumer_supply overo_vdda_dac_supply = + REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"); + +static struct regulator_consumer_supply overo_vdds_dsi_supply[] = { + REGULATOR_SUPPLY("vdds_dsi", "omapdss"), + REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), +}; + static struct mtd_partition overo_nand_partitions[] = { { .name = "xloader", @@ -358,6 +477,35 @@ static struct regulator_init_data overo_vmmc1 = { .consumer_supplies = &overo_vmmc1_supply, }; +/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */ +static struct regulator_init_data overo_vdac = { + .constraints = { + .min_uV = 1800000, + .max_uV = 1800000, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &overo_vdda_dac_supply, +}; + +/* VPLL2 for digital video outputs */ +static struct regulator_init_data overo_vpll2 = { + .constraints = { + .name = "VDVI", + .min_uV = 1800000, + .max_uV = 1800000, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(overo_vdds_dsi_supply), + .consumer_supplies = overo_vdds_dsi_supply, +}; + static struct twl4030_codec_audio_data overo_audio_data; static struct twl4030_codec_data overo_codec_data = { @@ -365,8 +513,6 @@ static struct twl4030_codec_data overo_codec_data = { .audio = &overo_audio_data, }; -/* mmc2 (WLAN) and Bluetooth don't use twl4030 regulators */ - static struct twl4030_platform_data overo_twldata = { .irq_base = TWL4030_IRQ_BASE, .irq_end = TWL4030_IRQ_END, @@ -374,6 +520,8 @@ static struct twl4030_platform_data overo_twldata = { .usb = &overo_usb_data, .codec = &overo_codec_data, .vmmc1 = &overo_vmmc1, + .vdac = &overo_vdac, + .vpll2 = &overo_vpll2, }; static struct i2c_board_info __initdata overo_i2c_boardinfo[] = { @@ -394,18 +542,38 @@ static int __init overo_i2c_init(void) return 0; } -static struct platform_device overo_lcd_device = { - .name = "overo_lcd", - .id = -1, +static struct spi_board_info overo_spi_board_info[] __initdata = { +#if defined(CONFIG_TOUCHSCREEN_ADS7846) || \ + defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) + { + .modalias = "ads7846", + .bus_num = 1, + .chip_select = 0, + .max_speed_hz = 1500000, + .controller_data = &ads7846_mcspi_config, + .irq = OMAP_GPIO_IRQ(OVERO_GPIO_PENDOWN), + .platform_data = &ads7846_config, + }, +#endif +#if defined(CONFIG_PANEL_LGPHILIPS_LB035Q02) || \ + defined(CONFIG_PANEL_LGPHILIPS_LB035Q02_MODULE) + { + .modalias = "lgphilips_lb035q02_panel-spi", + .bus_num = 1, + .chip_select = 1, + .max_speed_hz = 500000, + .mode = SPI_MODE_3, + }, +#endif }; -static struct omap_lcd_config overo_lcd_config __initdata = { - .ctrl_name = "internal", -}; - -static struct omap_board_config_kernel overo_config[] __initdata = { - { OMAP_TAG_LCD, &overo_lcd_config }, -}; +static int __init overo_spi_init(void) +{ + overo_ads7846_init(); + spi_register_board_info(overo_spi_board_info, + ARRAY_SIZE(overo_spi_board_info)); + return 0; +} static void __init overo_init_early(void) { @@ -414,10 +582,6 @@ static void __init overo_init_early(void) mt46h32m32lf6_sdrc_params); } -static struct platform_device *overo_devices[] __initdata = { - &overo_lcd_device, -}; - static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { .port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN, .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, @@ -444,16 +608,15 @@ static struct omap_musb_board_data musb_board_data = { static void __init overo_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); - omap_board_config = overo_config; - omap_board_config_size = ARRAY_SIZE(overo_config); overo_i2c_init(); - platform_add_devices(overo_devices, ARRAY_SIZE(overo_devices)); + omap_display_init(&overo_dss_data); omap_serial_init(); overo_flash_init(); usb_musb_init(&musb_board_data); usb_ehci_init(&ehci_pdata); - overo_ads7846_init(); + overo_spi_init(); overo_init_smsc911x(); + overo_display_init(); /* Ensure SDRC pins are mux'd for self-refresh */ omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); From 66534e8e936a0b926863df90054dc59826d70528 Mon Sep 17 00:00:00 2001 From: "Taneja, Archit" Date: Tue, 8 Mar 2011 05:50:34 -0600 Subject: [PATCH 055/140] OMAP2PLUS: DSS2: Cleanup clock source related code Clean up some of the DSS functions which select/get clock sources, use switch to select the clock source members since more clock sources will be introduced later on. Remove the use of macro CONFIG_OMAP2_DSS_DSI in dispc_fclk_rate, use a dummy inline for function for dsi_get_pll_hsdiv_dispc_rate() instead for code clarity. Signed-off-by: Archit Taneja Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dispc.c | 15 +++++++++------ drivers/video/omap2/dss/dss.c | 32 ++++++++++++++++++++------------ drivers/video/omap2/dss/dss.h | 5 +++++ 3 files changed, 34 insertions(+), 18 deletions(-) diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c index 4a368c47700e..28b690f2447f 100644 --- a/drivers/video/omap2/dss/dispc.c +++ b/drivers/video/omap2/dss/dispc.c @@ -2341,14 +2341,17 @@ unsigned long dispc_fclk_rate(void) { unsigned long r = 0; - if (dss_get_dispc_clk_source() == DSS_CLK_SRC_FCK) + switch (dss_get_dispc_clk_source()) { + case DSS_CLK_SRC_FCK: r = dss_clk_get_rate(DSS_CLK_FCK); - else -#ifdef CONFIG_OMAP2_DSS_DSI + break; + case DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: r = dsi_get_pll_hsdiv_dispc_rate(); -#else - BUG(); -#endif + break; + default: + BUG(); + } + return r; } diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c index 2be4d03ece43..93813fd626be 100644 --- a/drivers/video/omap2/dss/dss.c +++ b/drivers/video/omap2/dss/dss.c @@ -293,13 +293,17 @@ void dss_select_dispc_clk_source(enum dss_clk_source clk_src) { int b; - BUG_ON(clk_src != DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC && - clk_src != DSS_CLK_SRC_FCK); - - b = clk_src == DSS_CLK_SRC_FCK ? 0 : 1; - - if (clk_src == DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC) + switch (clk_src) { + case DSS_CLK_SRC_FCK: + b = 0; + break; + case DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: + b = 1; dsi_wait_pll_hsdiv_dispc_active(); + break; + default: + BUG(); + } REG_FLD_MOD(DSS_CONTROL, b, 0, 0); /* DISPC_CLK_SWITCH */ @@ -310,13 +314,17 @@ void dss_select_dsi_clk_source(enum dss_clk_source clk_src) { int b; - BUG_ON(clk_src != DSS_CLK_SRC_DSI_PLL_HSDIV_DSI && - clk_src != DSS_CLK_SRC_FCK); - - b = clk_src == DSS_CLK_SRC_FCK ? 0 : 1; - - if (clk_src == DSS_CLK_SRC_DSI_PLL_HSDIV_DSI) + switch (clk_src) { + case DSS_CLK_SRC_FCK: + b = 0; + break; + case DSS_CLK_SRC_DSI_PLL_HSDIV_DSI: + b = 1; dsi_wait_pll_hsdiv_dsi_active(); + break; + default: + BUG(); + } REG_FLD_MOD(DSS_CONTROL, b, 1, 1); /* DSI_CLK_SWITCH */ diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h index 85d4141689c1..fc41b3f0c27e 100644 --- a/drivers/video/omap2/dss/dss.h +++ b/drivers/video/omap2/dss/dss.h @@ -299,6 +299,11 @@ static inline int dsi_init_platform_driver(void) static inline void dsi_uninit_platform_driver(void) { } +static inline unsigned long dsi_get_pll_hsdiv_dispc_rate(void) +{ + WARN("%s: DSI not compiled in, returning rate as 0\n", __func__); + return 0; +} static inline void dsi_wait_pll_hsdiv_dispc_active(void) { } From ea75159ee6f00bd809f57a58e5505dc362382cc8 Mon Sep 17 00:00:00 2001 From: "Taneja, Archit" Date: Tue, 8 Mar 2011 05:50:35 -0600 Subject: [PATCH 056/140] OMAP4: DSS2: Clock source changes for OMAP4 On OMAP3, the pixel clock for the LCD manager was derived through DISPC_FCLK as: Lcd Pixel clock = DISPC_FCLK / lcd / pcd Where lcd and pcd are divisors in the DISPC_DIVISOR register. On OMAP4, the pixel clocks for LCD1 and LCD2 managers are derived from 2 new clocks named LCD1_CLK and LCD2_CLK. The pixel clocks are calculated as: Lcd_o Pixel clock = LCDo_CLK / lcdo /pcdo, o = 1, 2 Where lcdo and pcdo registers are divisors in DISPC_DIVISORo registers. LCD1_CLK and LCD2_CLK can have DSS_FCLK, and the M4 divider clocks of DSI1 PLL and DSI2 PLL as clock sources respectively. Introduce functions to select and get the clock source for these new clocks. Modify DISPC functions get the correct lck and pck rates based on the clock source of these clocks. Since OMAP2/3 don't have these clocks, force OMAP2/3 to always have the LCD_CLK source as DSS_CLK_SRC_FCK by introducing a dss feature. Introduce clock source names for OMAP4 and some register field changes in DSS_CTRL on OMAP4. Currently, LCD2_CLK can only have DSS_FCLK as its clock source as DSI2 PLL functionality hasn't been introduced yet. BUG for now if DSI2 PLL is selected as clock. Signed-off-by: Archit Taneja Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dispc.c | 31 ++++++++++++++++--- drivers/video/omap2/dss/dss.c | 42 +++++++++++++++++++++++++- drivers/video/omap2/dss/dss.h | 26 ++++++++++------ drivers/video/omap2/dss/dss_features.c | 13 ++++++-- drivers/video/omap2/dss/dss_features.h | 3 ++ 5 files changed, 98 insertions(+), 17 deletions(-) diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c index 28b690f2447f..b8c576a0bc02 100644 --- a/drivers/video/omap2/dss/dispc.c +++ b/drivers/video/omap2/dss/dispc.c @@ -2365,25 +2365,33 @@ unsigned long dispc_lclk_rate(enum omap_channel channel) lcd = FLD_GET(l, 23, 16); - r = dispc_fclk_rate(); + switch (dss_get_lcd_clk_source(channel)) { + case DSS_CLK_SRC_FCK: + r = dss_clk_get_rate(DSS_CLK_FCK); + break; + case DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: + r = dsi_get_pll_hsdiv_dispc_rate(); + break; + default: + BUG(); + } return r / lcd; } unsigned long dispc_pclk_rate(enum omap_channel channel) { - int lcd, pcd; + int pcd; unsigned long r; u32 l; l = dispc_read_reg(DISPC_DIVISORo(channel)); - lcd = FLD_GET(l, 23, 16); pcd = FLD_GET(l, 7, 0); - r = dispc_fclk_rate(); + r = dispc_lclk_rate(channel); - return r / lcd / pcd; + return r / pcd; } void dispc_dump_clocks(struct seq_file *s) @@ -2391,6 +2399,7 @@ void dispc_dump_clocks(struct seq_file *s) int lcd, pcd; u32 l; enum dss_clk_source dispc_clk_src = dss_get_dispc_clk_source(); + enum dss_clk_source lcd_clk_src; enable_clocks(1); @@ -2412,6 +2421,12 @@ void dispc_dump_clocks(struct seq_file *s) } seq_printf(s, "- LCD1 -\n"); + lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD); + + seq_printf(s, "lcd1_clk source = %s (%s)\n", + dss_get_generic_clk_source_name(lcd_clk_src), + dss_feat_get_clk_source_name(lcd_clk_src)); + dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd); seq_printf(s, "lck\t\t%-16lulck div\t%u\n", @@ -2421,6 +2436,12 @@ void dispc_dump_clocks(struct seq_file *s) if (dss_has_feature(FEAT_MGR_LCD2)) { seq_printf(s, "- LCD2 -\n"); + lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD2); + + seq_printf(s, "lcd2_clk source = %s (%s)\n", + dss_get_generic_clk_source_name(lcd_clk_src), + dss_feat_get_clk_source_name(lcd_clk_src)); + dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd); seq_printf(s, "lck\t\t%-16lulck div\t%u\n", diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c index 93813fd626be..aed9345e8ada 100644 --- a/drivers/video/omap2/dss/dss.c +++ b/drivers/video/omap2/dss/dss.c @@ -77,6 +77,7 @@ static struct { enum dss_clk_source dsi_clk_source; enum dss_clk_source dispc_clk_source; + enum dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS]; u32 ctx[DSS_SZ_REGS / sizeof(u32)]; } dss; @@ -292,6 +293,7 @@ void dss_dump_regs(struct seq_file *s) void dss_select_dispc_clk_source(enum dss_clk_source clk_src) { int b; + u8 start, end; switch (clk_src) { case DSS_CLK_SRC_FCK: @@ -305,7 +307,9 @@ void dss_select_dispc_clk_source(enum dss_clk_source clk_src) BUG(); } - REG_FLD_MOD(DSS_CONTROL, b, 0, 0); /* DISPC_CLK_SWITCH */ + dss_feat_get_reg_field(FEAT_REG_DISPC_CLK_SWITCH, &start, &end); + + REG_FLD_MOD(DSS_CONTROL, b, start, end); /* DISPC_CLK_SWITCH */ dss.dispc_clk_source = clk_src; } @@ -331,6 +335,34 @@ void dss_select_dsi_clk_source(enum dss_clk_source clk_src) dss.dsi_clk_source = clk_src; } +void dss_select_lcd_clk_source(enum omap_channel channel, + enum dss_clk_source clk_src) +{ + int b, ix, pos; + + if (!dss_has_feature(FEAT_LCD_CLK_SRC)) + return; + + switch (clk_src) { + case DSS_CLK_SRC_FCK: + b = 0; + break; + case DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: + BUG_ON(channel != OMAP_DSS_CHANNEL_LCD); + b = 1; + dsi_wait_pll_hsdiv_dispc_active(); + break; + default: + BUG(); + } + + pos = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 12; + REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* LCDx_CLK_SWITCH */ + + ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 1; + dss.lcd_clk_source[ix] = clk_src; +} + enum dss_clk_source dss_get_dispc_clk_source(void) { return dss.dispc_clk_source; @@ -341,6 +373,12 @@ enum dss_clk_source dss_get_dsi_clk_source(void) return dss.dsi_clk_source; } +enum dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel) +{ + int ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 1; + return dss.lcd_clk_source[ix]; +} + /* calculate clock rates using dividers in cinfo */ int dss_calc_clock_rates(struct dss_clock_info *cinfo) { @@ -624,6 +662,8 @@ static int dss_init(void) dss.dsi_clk_source = DSS_CLK_SRC_FCK; dss.dispc_clk_source = DSS_CLK_SRC_FCK; + dss.lcd_clk_source[0] = DSS_CLK_SRC_FCK; + dss.lcd_clk_source[1] = DSS_CLK_SRC_FCK; dss_save_context(); diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h index fc41b3f0c27e..b845468d9706 100644 --- a/drivers/video/omap2/dss/dss.h +++ b/drivers/video/omap2/dss/dss.h @@ -118,9 +118,12 @@ enum dss_clock { }; enum dss_clk_source { - DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* DSI1_PLL_FCLK */ - DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* DSI2_PLL_FCLK */ - DSS_CLK_SRC_FCK, /* DSS1_ALWON_FCLK */ + DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK + * OMAP4: PLL1_CLK1 */ + DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK + * OMAP4: PLL1_CLK2 */ + DSS_CLK_SRC_FCK, /* OMAP2/3: DSS1_ALWON_FCLK + * OMAP4: DSS_FCLK */ }; /* Correlates clock source name and dss_clk_source member */ @@ -152,17 +155,19 @@ struct dsi_clock_info { unsigned long fint; unsigned long clkin4ddr; unsigned long clkin; - unsigned long dsi_pll_hsdiv_dispc_clk; /* DSI1_PLL_CLK */ - unsigned long dsi_pll_hsdiv_dsi_clk; /* DSI2_PLL_CLK */ - + unsigned long dsi_pll_hsdiv_dispc_clk; /* OMAP3: DSI1_PLL_CLK + * OMAP4: PLLx_CLK1 */ + unsigned long dsi_pll_hsdiv_dsi_clk; /* OMAP3: DSI2_PLL_CLK + * OMAP4: PLLx_CLK2 */ unsigned long lp_clk; /* dividers */ u16 regn; u16 regm; - u16 regm_dispc; /* REGM3 */ - u16 regm_dsi; /* REGM4 */ - + u16 regm_dispc; /* OMAP3: REGM3 + * OMAP4: REGM4 */ + u16 regm_dsi; /* OMAP3: REGM4 + * OMAP4: REGM5 */ u16 lp_clk_div; u8 highfreq; @@ -235,8 +240,11 @@ void dss_sdi_disable(void); void dss_select_dispc_clk_source(enum dss_clk_source clk_src); void dss_select_dsi_clk_source(enum dss_clk_source clk_src); +void dss_select_lcd_clk_source(enum omap_channel channel, + enum dss_clk_source clk_src); enum dss_clk_source dss_get_dispc_clk_source(void); enum dss_clk_source dss_get_dsi_clk_source(void); +enum dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel); void dss_set_venc_output(enum omap_dss_venc_type type); void dss_set_dac_pwrdn_bgz(bool enable); diff --git a/drivers/video/omap2/dss/dss_features.c b/drivers/video/omap2/dss/dss_features.c index dc170ad079f2..6eb6ec62a000 100644 --- a/drivers/video/omap2/dss/dss_features.c +++ b/drivers/video/omap2/dss/dss_features.c @@ -59,6 +59,7 @@ static const struct dss_reg_field omap2_dss_reg_fields[] = { { FEAT_REG_FIFOSIZE, 8, 0 }, { FEAT_REG_HORIZONTALACCU, 9, 0 }, { FEAT_REG_VERTICALACCU, 25, 16 }, + { FEAT_REG_DISPC_CLK_SWITCH, 0, 0 }, }; static const struct dss_reg_field omap3_dss_reg_fields[] = { @@ -69,6 +70,7 @@ static const struct dss_reg_field omap3_dss_reg_fields[] = { { FEAT_REG_FIFOSIZE, 10, 0 }, { FEAT_REG_HORIZONTALACCU, 9, 0 }, { FEAT_REG_VERTICALACCU, 25, 16 }, + { FEAT_REG_DISPC_CLK_SWITCH, 0, 0 }, }; static const struct dss_reg_field omap4_dss_reg_fields[] = { @@ -79,6 +81,7 @@ static const struct dss_reg_field omap4_dss_reg_fields[] = { { FEAT_REG_FIFOSIZE, 15, 0 }, { FEAT_REG_HORIZONTALACCU, 10, 0 }, { FEAT_REG_VERTICALACCU, 26, 16 }, + { FEAT_REG_DISPC_CLK_SWITCH, 9, 8 }, }; static const enum omap_display_type omap2_dss_supported_displays[] = { @@ -171,6 +174,12 @@ static const struct dss_clk_source_name omap3_dss_clk_source_names[] = { { DSS_CLK_SRC_FCK, "DSS1_ALWON_FCLK" }, }; +static const struct dss_clk_source_name omap4_dss_clk_source_names[] = { + { DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, "PLL1_CLK1" }, + { DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, "PLL1_CLK2" }, + { DSS_CLK_SRC_FCK, "DSS_FCLK" }, +}; + /* OMAP2 DSS Features */ static struct omap_dss_features omap2_dss_features = { .reg_fields = omap2_dss_reg_fields, @@ -235,14 +244,14 @@ static struct omap_dss_features omap4_dss_features = { .has_feature = FEAT_GLOBAL_ALPHA | FEAT_PRE_MULT_ALPHA | FEAT_MGR_LCD2 | FEAT_GLOBAL_ALPHA_VID1 | - FEAT_CORE_CLK_DIV, + FEAT_CORE_CLK_DIV | FEAT_LCD_CLK_SRC, .num_mgrs = 3, .num_ovls = 3, .max_dss_fck = 186000000, .supported_displays = omap4_dss_supported_displays, .supported_color_modes = omap3_dss_supported_color_modes, - .clksrc_names = omap3_dss_clk_source_names, + .clksrc_names = omap4_dss_clk_source_names, }; /* Functions returning values related to a DSS feature */ diff --git a/drivers/video/omap2/dss/dss_features.h b/drivers/video/omap2/dss/dss_features.h index 569d1b295edd..729b5f19fa2e 100644 --- a/drivers/video/omap2/dss/dss_features.h +++ b/drivers/video/omap2/dss/dss_features.h @@ -22,6 +22,7 @@ #define MAX_DSS_MANAGERS 3 #define MAX_DSS_OVERLAYS 3 +#define MAX_DSS_LCD_MANAGERS 2 /* DSS has feature id */ enum dss_feat_id { @@ -38,6 +39,7 @@ enum dss_feat_id { FEAT_RESIZECONF = 1 << 10, /* Independent core clk divider */ FEAT_CORE_CLK_DIV = 1 << 11, + FEAT_LCD_CLK_SRC = 1 << 12, }; /* DSS register field id */ @@ -49,6 +51,7 @@ enum dss_feat_reg_field { FEAT_REG_FIFOSIZE, FEAT_REG_HORIZONTALACCU, FEAT_REG_VERTICALACCU, + FEAT_REG_DISPC_CLK_SWITCH, }; /* DSS Feature Functions */ From ca0a6a6473f69f1773c97755840587262d841883 Mon Sep 17 00:00:00 2001 From: Steve Sakoman Date: Sat, 5 Mar 2011 10:12:26 -0600 Subject: [PATCH 057/140] omap: overo: Add regulator for ads7846 The ads7846 driver now requires a regulator. This patch adds the necessary regulator to the overo board file. Without it, the following error occurs (and the touchscreen will not function): ads7846 spi1.0: unable to get regulator: -19 Signed-off-by: Steve Sakoman Acked-by: Tony Lindgren Signed-off-by: Tomi Valkeinen --- arch/arm/mach-omap2/board-overo.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index d621ee8fec0c..4278ecb799a2 100644 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include @@ -97,6 +98,34 @@ static struct ads7846_platform_data ads7846_config = { .keep_vref_on = 1, }; +/* fixed regulator for ads7846 */ +static struct regulator_consumer_supply ads7846_supply = + REGULATOR_SUPPLY("vcc", "spi1.0"); + +static struct regulator_init_data vads7846_regulator = { + .constraints = { + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &ads7846_supply, +}; + +static struct fixed_voltage_config vads7846 = { + .supply_name = "vads7846", + .microvolts = 3300000, /* 3.3V */ + .gpio = -EINVAL, + .startup_delay = 0, + .init_data = &vads7846_regulator, +}; + +static struct platform_device vads7846_device = { + .name = "reg-fixed-voltage", + .id = 1, + .dev = { + .platform_data = &vads7846, + }, +}; + static void __init overo_ads7846_init(void) { if ((gpio_request(OVERO_GPIO_PENDOWN, "ADS7846_PENDOWN") == 0) && @@ -106,6 +135,8 @@ static void __init overo_ads7846_init(void) printk(KERN_ERR "could not obtain gpio for ADS7846_PENDOWN\n"); return; } + + platform_device_register(&vads7846_device); } #else From 7c94f68d7b490c7787c6b97c5b2d6d56d57b071c Mon Sep 17 00:00:00 2001 From: Steve Sakoman Date: Wed, 9 Mar 2011 18:08:05 -0600 Subject: [PATCH 058/140] OMAP: Add gpio-leds support for Overo This patch adds support for the standard LEDs on the Overo COM and expansion boards Signed-off-by: Steve Sakoman Acked-by: Tony Lindgren Signed-off-by: Tomi Valkeinen --- arch/arm/mach-omap2/board-overo.c | 53 +++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index 4278ecb799a2..e694ebd2636c 100644 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c @@ -473,6 +473,52 @@ static struct regulator_consumer_supply overo_vmmc1_supply = { .supply = "vmmc", }; +#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) +#include + +static struct gpio_led gpio_leds[] = { + { + .name = "overo:red:gpio21", + .default_trigger = "heartbeat", + .gpio = 21, + .active_low = true, + }, + { + .name = "overo:blue:gpio22", + .default_trigger = "none", + .gpio = 22, + .active_low = true, + }, + { + .name = "overo:blue:COM", + .default_trigger = "mmc0", + .gpio = -EINVAL, /* gets replaced */ + .active_low = true, + }, +}; + +static struct gpio_led_platform_data gpio_leds_pdata = { + .leds = gpio_leds, + .num_leds = ARRAY_SIZE(gpio_leds), +}; + +static struct platform_device gpio_leds_device = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &gpio_leds_pdata, + }, +}; + +static void __init overo_init_led(void) +{ + platform_device_register(&gpio_leds_device); +} + +#else +static inline void __init overo_init_led(void) { return; } +#endif + static int overo_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned ngpio) { @@ -480,6 +526,11 @@ static int overo_twl_gpio_setup(struct device *dev, overo_vmmc1_supply.dev = mmc[0].dev; +#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) + /* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */ + gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1; +#endif + return 0; } @@ -487,6 +538,7 @@ static struct twl4030_gpio_platform_data overo_gpio_data = { .gpio_base = OMAP_MAX_GPIO_LINES, .irq_base = TWL4030_GPIO_IRQ_BASE, .irq_end = TWL4030_GPIO_IRQ_END, + .use_leds = true, .setup = overo_twl_gpio_setup, }; @@ -648,6 +700,7 @@ static void __init overo_init(void) overo_spi_init(); overo_init_smsc911x(); overo_display_init(); + overo_init_led(); /* Ensure SDRC pins are mux'd for self-refresh */ omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); From cce18a947967ed028e5301bce84cbaff395489a6 Mon Sep 17 00:00:00 2001 From: Steve Sakoman Date: Wed, 9 Mar 2011 18:08:06 -0600 Subject: [PATCH 059/140] OMAP: Add gpio-keys support for Overo This patch adds support for the standard push buttons available on Overo expansion boards. Signed-off-by: Steve Sakoman Acked-by: Tony Lindgren Signed-off-by: Tomi Valkeinen --- arch/arm/mach-omap2/board-overo.c | 42 +++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index e694ebd2636c..1e17061649e5 100644 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c @@ -519,6 +519,47 @@ static void __init overo_init_led(void) static inline void __init overo_init_led(void) { return; } #endif +#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) +#include +#include + +static struct gpio_keys_button gpio_buttons[] = { + { + .code = BTN_0, + .gpio = 23, + .desc = "button0", + .wakeup = 1, + }, + { + .code = BTN_1, + .gpio = 14, + .desc = "button1", + .wakeup = 1, + }, +}; + +static struct gpio_keys_platform_data gpio_keys_pdata = { + .buttons = gpio_buttons, + .nbuttons = ARRAY_SIZE(gpio_buttons), +}; + +static struct platform_device gpio_keys_device = { + .name = "gpio-keys", + .id = -1, + .dev = { + .platform_data = &gpio_keys_pdata, + }, +}; + +static void __init overo_init_keys(void) +{ + platform_device_register(&gpio_keys_device); +} + +#else +static inline void __init overo_init_keys(void) { return; } +#endif + static int overo_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned ngpio) { @@ -701,6 +742,7 @@ static void __init overo_init(void) overo_init_smsc911x(); overo_display_init(); overo_init_led(); + overo_init_keys(); /* Ensure SDRC pins are mux'd for self-refresh */ omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); From ba02fa37de80bea10d706f39f076dd848348320a Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Fri, 11 Mar 2011 09:28:06 +0200 Subject: [PATCH 060/140] HACK: OMAP: DSS2: VENC: disable VENC on OMAP4 to prevent crash Something seems to be wrong with OMAP4 & VENC, and register access fails in omap_venchw_probe(). This patch skips venc driver registration on OMAP4, thus circumventing the problem for now. Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/venc.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/video/omap2/dss/venc.c b/drivers/video/omap2/dss/venc.c index 43009e57cd3e..8e35a5bae429 100644 --- a/drivers/video/omap2/dss/venc.c +++ b/drivers/video/omap2/dss/venc.c @@ -769,10 +769,16 @@ static struct platform_driver omap_venchw_driver = { int venc_init_platform_driver(void) { + if (cpu_is_omap44xx()) + return 0; + return platform_driver_register(&omap_venchw_driver); } void venc_uninit_platform_driver(void) { + if (cpu_is_omap44xx()) + return; + return platform_driver_unregister(&omap_venchw_driver); } From 235e7dba0264d4c6e56ee217fc7ef6d80da5eb67 Mon Sep 17 00:00:00 2001 From: "Taneja, Archit" Date: Mon, 14 Mar 2011 23:28:21 -0500 Subject: [PATCH 061/140] OMAP2PLUS: DSS2: FEATURES: Fix usage of dss_reg_field and dss_clk_source_name The structures dss_reg_field and dss_clk_source_name have enum members which specify the register field and the clock source respectively. These members are not used to choose the correct result in the corresponding feature functions. Remove these members and change the features array declaration to incorporate these enums. The structure dss_clk_source_name without the enum member is just a pointer to an string. Remove the structure and use a character pointer directly. Signed-off-by: Archit Taneja Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dss.c | 10 ++-- drivers/video/omap2/dss/dss.h | 6 -- drivers/video/omap2/dss/dss_features.c | 77 +++++++++++++------------- 3 files changed, 43 insertions(+), 50 deletions(-) diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c index aed9345e8ada..06ad31290853 100644 --- a/drivers/video/omap2/dss/dss.c +++ b/drivers/video/omap2/dss/dss.c @@ -82,10 +82,10 @@ static struct { u32 ctx[DSS_SZ_REGS / sizeof(u32)]; } dss; -static const struct dss_clk_source_name dss_generic_clk_source_names[] = { - { DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, "DSI_PLL_HSDIV_DISPC" }, - { DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, "DSI_PLL_HSDIV_DSI" }, - { DSS_CLK_SRC_FCK, "DSS_FCK" }, +static const char * const dss_generic_clk_source_names[] = { + [DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "DSI_PLL_HSDIV_DISPC", + [DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "DSI_PLL_HSDIV_DSI", + [DSS_CLK_SRC_FCK] = "DSS_FCK", }; static void dss_clk_enable_all_no_ctx(void); @@ -232,7 +232,7 @@ void dss_sdi_disable(void) const char *dss_get_generic_clk_source_name(enum dss_clk_source clk_src) { - return dss_generic_clk_source_names[clk_src].clksrc_name; + return dss_generic_clk_source_names[clk_src]; } void dss_dump_clocks(struct seq_file *s) diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h index b845468d9706..26a43c93e489 100644 --- a/drivers/video/omap2/dss/dss.h +++ b/drivers/video/omap2/dss/dss.h @@ -126,12 +126,6 @@ enum dss_clk_source { * OMAP4: DSS_FCLK */ }; -/* Correlates clock source name and dss_clk_source member */ -struct dss_clk_source_name { - enum dss_clk_source clksrc; - const char *clksrc_name; -}; - struct dss_clock_info { /* rates that we get with dividers below */ unsigned long fck; diff --git a/drivers/video/omap2/dss/dss_features.c b/drivers/video/omap2/dss/dss_features.c index 6eb6ec62a000..8de3344842d7 100644 --- a/drivers/video/omap2/dss/dss_features.c +++ b/drivers/video/omap2/dss/dss_features.c @@ -30,7 +30,6 @@ /* Defines a generic omap register field */ struct dss_reg_field { - enum dss_feat_reg_field id; u8 start, end; }; @@ -45,43 +44,43 @@ struct omap_dss_features { const unsigned long max_dss_fck; const enum omap_display_type *supported_displays; const enum omap_color_mode *supported_color_modes; - const struct dss_clk_source_name *clksrc_names; + const char * const *clksrc_names; }; /* This struct is assigned to one of the below during initialization */ static struct omap_dss_features *omap_current_dss_features; static const struct dss_reg_field omap2_dss_reg_fields[] = { - { FEAT_REG_FIRHINC, 11, 0 }, - { FEAT_REG_FIRVINC, 27, 16 }, - { FEAT_REG_FIFOLOWTHRESHOLD, 8, 0 }, - { FEAT_REG_FIFOHIGHTHRESHOLD, 24, 16 }, - { FEAT_REG_FIFOSIZE, 8, 0 }, - { FEAT_REG_HORIZONTALACCU, 9, 0 }, - { FEAT_REG_VERTICALACCU, 25, 16 }, - { FEAT_REG_DISPC_CLK_SWITCH, 0, 0 }, + [FEAT_REG_FIRHINC] = { 11, 0 }, + [FEAT_REG_FIRVINC] = { 27, 16 }, + [FEAT_REG_FIFOLOWTHRESHOLD] = { 8, 0 }, + [FEAT_REG_FIFOHIGHTHRESHOLD] = { 24, 16 }, + [FEAT_REG_FIFOSIZE] = { 8, 0 }, + [FEAT_REG_HORIZONTALACCU] = { 9, 0 }, + [FEAT_REG_VERTICALACCU] = { 25, 16 }, + [FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 }, }; static const struct dss_reg_field omap3_dss_reg_fields[] = { - { FEAT_REG_FIRHINC, 12, 0 }, - { FEAT_REG_FIRVINC, 28, 16 }, - { FEAT_REG_FIFOLOWTHRESHOLD, 11, 0 }, - { FEAT_REG_FIFOHIGHTHRESHOLD, 27, 16 }, - { FEAT_REG_FIFOSIZE, 10, 0 }, - { FEAT_REG_HORIZONTALACCU, 9, 0 }, - { FEAT_REG_VERTICALACCU, 25, 16 }, - { FEAT_REG_DISPC_CLK_SWITCH, 0, 0 }, + [FEAT_REG_FIRHINC] = { 12, 0 }, + [FEAT_REG_FIRVINC] = { 28, 16 }, + [FEAT_REG_FIFOLOWTHRESHOLD] = { 11, 0 }, + [FEAT_REG_FIFOHIGHTHRESHOLD] = { 27, 16 }, + [FEAT_REG_FIFOSIZE] = { 10, 0 }, + [FEAT_REG_HORIZONTALACCU] = { 9, 0 }, + [FEAT_REG_VERTICALACCU] = { 25, 16 }, + [FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 }, }; static const struct dss_reg_field omap4_dss_reg_fields[] = { - { FEAT_REG_FIRHINC, 12, 0 }, - { FEAT_REG_FIRVINC, 28, 16 }, - { FEAT_REG_FIFOLOWTHRESHOLD, 15, 0 }, - { FEAT_REG_FIFOHIGHTHRESHOLD, 31, 16 }, - { FEAT_REG_FIFOSIZE, 15, 0 }, - { FEAT_REG_HORIZONTALACCU, 10, 0 }, - { FEAT_REG_VERTICALACCU, 26, 16 }, - { FEAT_REG_DISPC_CLK_SWITCH, 9, 8 }, + [FEAT_REG_FIRHINC] = { 12, 0 }, + [FEAT_REG_FIRVINC] = { 28, 16 }, + [FEAT_REG_FIFOLOWTHRESHOLD] = { 15, 0 }, + [FEAT_REG_FIFOHIGHTHRESHOLD] = { 31, 16 }, + [FEAT_REG_FIFOSIZE] = { 15, 0 }, + [FEAT_REG_HORIZONTALACCU] = { 10, 0 }, + [FEAT_REG_VERTICALACCU] = { 26, 16 }, + [FEAT_REG_DISPC_CLK_SWITCH] = { 9, 8 }, }; static const enum omap_display_type omap2_dss_supported_displays[] = { @@ -162,22 +161,22 @@ static const enum omap_color_mode omap3_dss_supported_color_modes[] = { OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32, }; -static const struct dss_clk_source_name omap2_dss_clk_source_names[] = { - { DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, "N/A" }, - { DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, "N/A" }, - { DSS_CLK_SRC_FCK, "DSS_FCLK1" }, +static const char * const omap2_dss_clk_source_names[] = { + [DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "N/A", + [DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "N/A", + [DSS_CLK_SRC_FCK] = "DSS_FCLK1", }; -static const struct dss_clk_source_name omap3_dss_clk_source_names[] = { - { DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, "DSI1_PLL_FCLK" }, - { DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, "DSI2_PLL_FCLK" }, - { DSS_CLK_SRC_FCK, "DSS1_ALWON_FCLK" }, +static const char * const omap3_dss_clk_source_names[] = { + [DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "DSI1_PLL_FCLK", + [DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "DSI2_PLL_FCLK", + [DSS_CLK_SRC_FCK] = "DSS1_ALWON_FCLK", }; -static const struct dss_clk_source_name omap4_dss_clk_source_names[] = { - { DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, "PLL1_CLK1" }, - { DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, "PLL1_CLK2" }, - { DSS_CLK_SRC_FCK, "DSS_FCLK" }, +static const char * const omap4_dss_clk_source_names[] = { + [DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "PLL1_CLK1", + [DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "PLL1_CLK2", + [DSS_CLK_SRC_FCK] = "DSS_FCLK", }; /* OMAP2 DSS Features */ @@ -290,7 +289,7 @@ bool dss_feat_color_mode_supported(enum omap_plane plane, const char *dss_feat_get_clk_source_name(enum dss_clk_source id) { - return omap_current_dss_features->clksrc_names[id].clksrc_name; + return omap_current_dss_features->clksrc_names[id]; } /* DSS has_feature check */ From 31ef82377f1e0f1bc7d308ae4312e6cc5a431885 Mon Sep 17 00:00:00 2001 From: "Taneja, Archit" Date: Mon, 14 Mar 2011 23:28:22 -0500 Subject: [PATCH 062/140] OMAP: DSS2: FEATURES: Functions to return min and max values of parameters Create 2 functions dss_feat_get_param_min() and dss_feat_get_param_max() which return the minimum and maximum value of a parameter. Introduce a enum in dss_features called dss_range_param which contains parameters whose ranges we are interested in. Replace this with dss_feat_get_max_dss_fck() which is specific to the parameter DSS_FCK. Signed-off-by: Archit Taneja Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dsi.c | 2 +- drivers/video/omap2/dss/dss.c | 2 +- drivers/video/omap2/dss/dss_features.c | 36 ++++++++++++++++++++------ drivers/video/omap2/dss/dss_features.h | 7 ++++- 4 files changed, 36 insertions(+), 11 deletions(-) diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c index be7694ff7ca7..6e7f46828148 100644 --- a/drivers/video/omap2/dss/dsi.c +++ b/drivers/video/omap2/dss/dsi.c @@ -864,7 +864,7 @@ int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck, dss_sys_clk = dss_clk_get_rate(DSS_CLK_SYSCK); - max_dss_fck = dss_feat_get_max_dss_fck(); + max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK); if (req_pck == dsi.cache_req_pck && dsi.cache_cinfo.clkin == dss_sys_clk) { diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c index 06ad31290853..562d8d28d4f2 100644 --- a/drivers/video/omap2/dss/dss.c +++ b/drivers/video/omap2/dss/dss.c @@ -457,7 +457,7 @@ int dss_calc_clock_div(bool is_tft, unsigned long req_pck, prate = dss_get_dpll4_rate(); - max_dss_fck = dss_feat_get_max_dss_fck(); + max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK); fck = dss_clk_get_rate(DSS_CLK_FCK); if (req_pck == dss.cache_req_pck && diff --git a/drivers/video/omap2/dss/dss_features.c b/drivers/video/omap2/dss/dss_features.c index 8de3344842d7..4c8b32af496c 100644 --- a/drivers/video/omap2/dss/dss_features.c +++ b/drivers/video/omap2/dss/dss_features.c @@ -33,6 +33,10 @@ struct dss_reg_field { u8 start, end; }; +struct dss_param_range { + int min, max; +}; + struct omap_dss_features { const struct dss_reg_field *reg_fields; const int num_reg_fields; @@ -41,10 +45,10 @@ struct omap_dss_features { const int num_mgrs; const int num_ovls; - const unsigned long max_dss_fck; const enum omap_display_type *supported_displays; const enum omap_color_mode *supported_color_modes; const char * const *clksrc_names; + const struct dss_param_range *dss_params; }; /* This struct is assigned to one of the below during initialization */ @@ -179,6 +183,18 @@ static const char * const omap4_dss_clk_source_names[] = { [DSS_CLK_SRC_FCK] = "DSS_FCLK", }; +static const struct dss_param_range omap2_dss_param_range[] = { + [FEAT_PARAM_DSS_FCK] = { 0, 173000000 }, +}; + +static const struct dss_param_range omap3_dss_param_range[] = { + [FEAT_PARAM_DSS_FCK] = { 0, 173000000 }, +}; + +static const struct dss_param_range omap4_dss_param_range[] = { + [FEAT_PARAM_DSS_FCK] = { 0, 186000000 }, +}; + /* OMAP2 DSS Features */ static struct omap_dss_features omap2_dss_features = { .reg_fields = omap2_dss_reg_fields, @@ -191,10 +207,10 @@ static struct omap_dss_features omap2_dss_features = { .num_mgrs = 2, .num_ovls = 3, - .max_dss_fck = 173000000, .supported_displays = omap2_dss_supported_displays, .supported_color_modes = omap2_dss_supported_color_modes, .clksrc_names = omap2_dss_clk_source_names, + .dss_params = omap2_dss_param_range, }; /* OMAP3 DSS Features */ @@ -210,10 +226,10 @@ static struct omap_dss_features omap3430_dss_features = { .num_mgrs = 2, .num_ovls = 3, - .max_dss_fck = 173000000, .supported_displays = omap3430_dss_supported_displays, .supported_color_modes = omap3_dss_supported_color_modes, .clksrc_names = omap3_dss_clk_source_names, + .dss_params = omap3_dss_param_range, }; static struct omap_dss_features omap3630_dss_features = { @@ -229,10 +245,10 @@ static struct omap_dss_features omap3630_dss_features = { .num_mgrs = 2, .num_ovls = 3, - .max_dss_fck = 173000000, .supported_displays = omap3630_dss_supported_displays, .supported_color_modes = omap3_dss_supported_color_modes, .clksrc_names = omap3_dss_clk_source_names, + .dss_params = omap3_dss_param_range, }; /* OMAP4 DSS Features */ @@ -247,10 +263,10 @@ static struct omap_dss_features omap4_dss_features = { .num_mgrs = 3, .num_ovls = 3, - .max_dss_fck = 186000000, .supported_displays = omap4_dss_supported_displays, .supported_color_modes = omap3_dss_supported_color_modes, .clksrc_names = omap4_dss_clk_source_names, + .dss_params = omap4_dss_param_range, }; /* Functions returning values related to a DSS feature */ @@ -264,10 +280,14 @@ int dss_feat_get_num_ovls(void) return omap_current_dss_features->num_ovls; } -/* Max supported DSS FCK in Hz */ -unsigned long dss_feat_get_max_dss_fck(void) +unsigned long dss_feat_get_param_min(enum dss_range_param param) { - return omap_current_dss_features->max_dss_fck; + return omap_current_dss_features->dss_params[param].min; +} + +unsigned long dss_feat_get_param_max(enum dss_range_param param) +{ + return omap_current_dss_features->dss_params[param].max; } enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel) diff --git a/drivers/video/omap2/dss/dss_features.h b/drivers/video/omap2/dss/dss_features.h index 729b5f19fa2e..da63bbf38e90 100644 --- a/drivers/video/omap2/dss/dss_features.h +++ b/drivers/video/omap2/dss/dss_features.h @@ -54,10 +54,15 @@ enum dss_feat_reg_field { FEAT_REG_DISPC_CLK_SWITCH, }; +enum dss_range_param { + FEAT_PARAM_DSS_FCK, +}; + /* DSS Feature Functions */ int dss_feat_get_num_mgrs(void); int dss_feat_get_num_ovls(void); -unsigned long dss_feat_get_max_dss_fck(void); +unsigned long dss_feat_get_param_min(enum dss_range_param param); +unsigned long dss_feat_get_param_max(enum dss_range_param param); enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel); enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane); bool dss_feat_color_mode_supported(enum omap_plane plane, From 49641116392ad7522fa0efad53f7ed63f811bd88 Mon Sep 17 00:00:00 2001 From: "Taneja, Archit" Date: Mon, 14 Mar 2011 23:28:23 -0500 Subject: [PATCH 063/140] OMAP: DSS2: FEATURES: DSI PLL parameter cleanup The DSI PLL parameters (regm, regn, regm_dispc, regm_dsi, fint) have different fields and also different Max values on OMAP3 and OMAP4. Use dss features to calculate the register fields and min/max values based on current OMAP revision. Signed-off-by: Archit Taneja Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dsi.c | 69 ++++++++++++++------- drivers/video/omap2/dss/dss_features.c | 84 +++++++++++++++++--------- drivers/video/omap2/dss/dss_features.h | 10 +++ 3 files changed, 113 insertions(+), 50 deletions(-) diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c index 6e7f46828148..7a4b4404a976 100644 --- a/drivers/video/omap2/dss/dsi.c +++ b/drivers/video/omap2/dss/dsi.c @@ -185,14 +185,6 @@ struct dsi_reg { u16 idx; }; #define DSI_DT_RX_SHORT_READ_1 0x21 #define DSI_DT_RX_SHORT_READ_2 0x22 -#define FINT_MAX 2100000 -#define FINT_MIN 750000 -#define REGN_MAX (1 << 7) -#define REGM_MAX ((1 << 11) - 1) -#define REGM_DISPC_MAX (1 << 4) -#define REGM_DSI_MAX (1 << 4) -#define LP_DIV_MAX ((1 << 13) - 1) - enum fifo_size { DSI_FIFO_SIZE_0 = 0, DSI_FIFO_SIZE_32 = 1, @@ -277,6 +269,11 @@ static struct spinlock_t irq_stats_lock; struct dsi_irq_stats irq_stats; #endif + /* DSI PLL Parameter Ranges */ + unsigned long regm_max, regn_max; + unsigned long regm_dispc_max, regm_dsi_max; + unsigned long fint_min, fint_max; + unsigned long lpdiv_max; } dsi; #ifdef DEBUG @@ -751,7 +748,7 @@ static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev) lp_clk_div = dssdev->phy.dsi.div.lp_clk_div; - if (lp_clk_div == 0 || lp_clk_div > LP_DIV_MAX) + if (lp_clk_div == 0 || lp_clk_div > dsi.lpdiv_max) return -EINVAL; dsi_fclk = dsi_fclk_rate(); @@ -801,16 +798,16 @@ static int dsi_pll_power(enum dsi_pll_power_state state) static int dsi_calc_clock_rates(struct omap_dss_device *dssdev, struct dsi_clock_info *cinfo) { - if (cinfo->regn == 0 || cinfo->regn > REGN_MAX) + if (cinfo->regn == 0 || cinfo->regn > dsi.regn_max) return -EINVAL; - if (cinfo->regm == 0 || cinfo->regm > REGM_MAX) + if (cinfo->regm == 0 || cinfo->regm > dsi.regm_max) return -EINVAL; - if (cinfo->regm_dispc > REGM_DISPC_MAX) + if (cinfo->regm_dispc > dsi.regm_dispc_max) return -EINVAL; - if (cinfo->regm_dsi > REGM_DSI_MAX) + if (cinfo->regm_dsi > dsi.regm_dsi_max) return -EINVAL; if (cinfo->use_sys_clk) { @@ -829,7 +826,7 @@ static int dsi_calc_clock_rates(struct omap_dss_device *dssdev, cinfo->fint = cinfo->clkin / (cinfo->regn * (cinfo->highfreq ? 2 : 1)); - if (cinfo->fint > FINT_MAX || cinfo->fint < FINT_MIN) + if (cinfo->fint > dsi.fint_max || cinfo->fint < dsi.fint_min) return -EINVAL; cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint; @@ -899,17 +896,17 @@ retry: /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */ /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */ /* To reduce PLL lock time, keep Fint high (around 2 MHz) */ - for (cur.regn = 1; cur.regn < REGN_MAX; ++cur.regn) { + for (cur.regn = 1; cur.regn < dsi.regn_max; ++cur.regn) { if (cur.highfreq == 0) cur.fint = cur.clkin / cur.regn; else cur.fint = cur.clkin / (2 * cur.regn); - if (cur.fint > FINT_MAX || cur.fint < FINT_MIN) + if (cur.fint > dsi.fint_max || cur.fint < dsi.fint_min) continue; /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */ - for (cur.regm = 1; cur.regm < REGM_MAX; ++cur.regm) { + for (cur.regm = 1; cur.regm < dsi.regm_max; ++cur.regm) { unsigned long a, b; a = 2 * cur.regm * (cur.clkin/1000); @@ -921,7 +918,7 @@ retry: /* dsi_pll_hsdiv_dispc_clk(MHz) = * DSIPHY(MHz) / regm_dispc < 173MHz/186Mhz */ - for (cur.regm_dispc = 1; cur.regm_dispc < REGM_DISPC_MAX; + for (cur.regm_dispc = 1; cur.regm_dispc < dsi.regm_dispc_max; ++cur.regm_dispc) { struct dispc_clock_info cur_dispc; cur.dsi_pll_hsdiv_dispc_clk = @@ -994,6 +991,8 @@ int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo) int r = 0; u32 l; int f; + u8 regn_start, regn_end, regm_start, regm_end; + u8 regm_dispc_start, regm_dispc_end, regm_dsi_start, regm_dsi_end; DSSDBGF(); @@ -1038,19 +1037,30 @@ int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo) dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI), cinfo->dsi_pll_hsdiv_dsi_clk); + dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN, ®n_start, ®n_end); + dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM, ®m_start, ®m_end); + dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DISPC, ®m_dispc_start, + ®m_dispc_end); + dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DSI, ®m_dsi_start, + ®m_dsi_end); + REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */ l = dsi_read_reg(DSI_PLL_CONFIGURATION1); l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */ - l = FLD_MOD(l, cinfo->regn - 1, 7, 1); /* DSI_PLL_REGN */ - l = FLD_MOD(l, cinfo->regm, 18, 8); /* DSI_PLL_REGM */ + /* DSI_PLL_REGN */ + l = FLD_MOD(l, cinfo->regn - 1, regn_start, regn_end); + /* DSI_PLL_REGM */ + l = FLD_MOD(l, cinfo->regm, regm_start, regm_end); + /* DSI_CLOCK_DIV */ l = FLD_MOD(l, cinfo->regm_dispc > 0 ? cinfo->regm_dispc - 1 : 0, - 22, 19); /* DSI_CLOCK_DIV */ + regm_dispc_start, regm_dispc_end); + /* DSIPROTO_CLOCK_DIV */ l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0, - 26, 23); /* DSIPROTO_CLOCK_DIV */ + regm_dsi_start, regm_dsi_end); dsi_write_reg(DSI_PLL_CONFIGURATION1, l); - BUG_ON(cinfo->fint < 750000 || cinfo->fint > 2100000); + BUG_ON(cinfo->fint < dsi.fint_min || cinfo->fint > dsi.fint_max); if (cinfo->fint < 1000000) f = 0x3; else if (cinfo->fint < 1250000) @@ -3333,6 +3343,17 @@ void dsi_wait_pll_hsdiv_dsi_active(void) dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI)); } +static void dsi_calc_clock_param_ranges(void) +{ + dsi.regn_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN); + dsi.regm_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM); + dsi.regm_dispc_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC); + dsi.regm_dsi_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DSI); + dsi.fint_min = dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT); + dsi.fint_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT); + dsi.lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV); +} + static int dsi_init(struct platform_device *pdev) { u32 rev; @@ -3397,6 +3418,8 @@ static int dsi_init(struct platform_device *pdev) dsi.vc[i].vc_id = 0; } + dsi_calc_clock_param_ranges(); + enable_clocks(1); rev = dsi_read_reg(DSI_REVISION); diff --git a/drivers/video/omap2/dss/dss_features.c b/drivers/video/omap2/dss/dss_features.c index 4c8b32af496c..06b18f73449b 100644 --- a/drivers/video/omap2/dss/dss_features.c +++ b/drivers/video/omap2/dss/dss_features.c @@ -55,36 +55,48 @@ struct omap_dss_features { static struct omap_dss_features *omap_current_dss_features; static const struct dss_reg_field omap2_dss_reg_fields[] = { - [FEAT_REG_FIRHINC] = { 11, 0 }, - [FEAT_REG_FIRVINC] = { 27, 16 }, - [FEAT_REG_FIFOLOWTHRESHOLD] = { 8, 0 }, - [FEAT_REG_FIFOHIGHTHRESHOLD] = { 24, 16 }, - [FEAT_REG_FIFOSIZE] = { 8, 0 }, - [FEAT_REG_HORIZONTALACCU] = { 9, 0 }, - [FEAT_REG_VERTICALACCU] = { 25, 16 }, - [FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 }, + [FEAT_REG_FIRHINC] = { 11, 0 }, + [FEAT_REG_FIRVINC] = { 27, 16 }, + [FEAT_REG_FIFOLOWTHRESHOLD] = { 8, 0 }, + [FEAT_REG_FIFOHIGHTHRESHOLD] = { 24, 16 }, + [FEAT_REG_FIFOSIZE] = { 8, 0 }, + [FEAT_REG_HORIZONTALACCU] = { 9, 0 }, + [FEAT_REG_VERTICALACCU] = { 25, 16 }, + [FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 }, + [FEAT_REG_DSIPLL_REGN] = { 0, 0 }, + [FEAT_REG_DSIPLL_REGM] = { 0, 0 }, + [FEAT_REG_DSIPLL_REGM_DISPC] = { 0, 0 }, + [FEAT_REG_DSIPLL_REGM_DSI] = { 0, 0 }, }; static const struct dss_reg_field omap3_dss_reg_fields[] = { - [FEAT_REG_FIRHINC] = { 12, 0 }, - [FEAT_REG_FIRVINC] = { 28, 16 }, - [FEAT_REG_FIFOLOWTHRESHOLD] = { 11, 0 }, - [FEAT_REG_FIFOHIGHTHRESHOLD] = { 27, 16 }, - [FEAT_REG_FIFOSIZE] = { 10, 0 }, - [FEAT_REG_HORIZONTALACCU] = { 9, 0 }, - [FEAT_REG_VERTICALACCU] = { 25, 16 }, - [FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 }, + [FEAT_REG_FIRHINC] = { 12, 0 }, + [FEAT_REG_FIRVINC] = { 28, 16 }, + [FEAT_REG_FIFOLOWTHRESHOLD] = { 11, 0 }, + [FEAT_REG_FIFOHIGHTHRESHOLD] = { 27, 16 }, + [FEAT_REG_FIFOSIZE] = { 10, 0 }, + [FEAT_REG_HORIZONTALACCU] = { 9, 0 }, + [FEAT_REG_VERTICALACCU] = { 25, 16 }, + [FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 }, + [FEAT_REG_DSIPLL_REGN] = { 7, 1 }, + [FEAT_REG_DSIPLL_REGM] = { 18, 8 }, + [FEAT_REG_DSIPLL_REGM_DISPC] = { 22, 19 }, + [FEAT_REG_DSIPLL_REGM_DSI] = { 26, 23 }, }; static const struct dss_reg_field omap4_dss_reg_fields[] = { - [FEAT_REG_FIRHINC] = { 12, 0 }, - [FEAT_REG_FIRVINC] = { 28, 16 }, - [FEAT_REG_FIFOLOWTHRESHOLD] = { 15, 0 }, - [FEAT_REG_FIFOHIGHTHRESHOLD] = { 31, 16 }, - [FEAT_REG_FIFOSIZE] = { 15, 0 }, - [FEAT_REG_HORIZONTALACCU] = { 10, 0 }, - [FEAT_REG_VERTICALACCU] = { 26, 16 }, - [FEAT_REG_DISPC_CLK_SWITCH] = { 9, 8 }, + [FEAT_REG_FIRHINC] = { 12, 0 }, + [FEAT_REG_FIRVINC] = { 28, 16 }, + [FEAT_REG_FIFOLOWTHRESHOLD] = { 15, 0 }, + [FEAT_REG_FIFOHIGHTHRESHOLD] = { 31, 16 }, + [FEAT_REG_FIFOSIZE] = { 15, 0 }, + [FEAT_REG_HORIZONTALACCU] = { 10, 0 }, + [FEAT_REG_VERTICALACCU] = { 26, 16 }, + [FEAT_REG_DISPC_CLK_SWITCH] = { 9, 8 }, + [FEAT_REG_DSIPLL_REGN] = { 8, 1 }, + [FEAT_REG_DSIPLL_REGM] = { 20, 9 }, + [FEAT_REG_DSIPLL_REGM_DISPC] = { 25, 21 }, + [FEAT_REG_DSIPLL_REGM_DSI] = { 30, 26 }, }; static const enum omap_display_type omap2_dss_supported_displays[] = { @@ -184,15 +196,33 @@ static const char * const omap4_dss_clk_source_names[] = { }; static const struct dss_param_range omap2_dss_param_range[] = { - [FEAT_PARAM_DSS_FCK] = { 0, 173000000 }, + [FEAT_PARAM_DSS_FCK] = { 0, 173000000 }, + [FEAT_PARAM_DSIPLL_REGN] = { 0, 0 }, + [FEAT_PARAM_DSIPLL_REGM] = { 0, 0 }, + [FEAT_PARAM_DSIPLL_REGM_DISPC] = { 0, 0 }, + [FEAT_PARAM_DSIPLL_REGM_DSI] = { 0, 0 }, + [FEAT_PARAM_DSIPLL_FINT] = { 0, 0 }, + [FEAT_PARAM_DSIPLL_LPDIV] = { 0, 0 }, }; static const struct dss_param_range omap3_dss_param_range[] = { - [FEAT_PARAM_DSS_FCK] = { 0, 173000000 }, + [FEAT_PARAM_DSS_FCK] = { 0, 173000000 }, + [FEAT_PARAM_DSIPLL_REGN] = { 0, (1 << 7) - 1 }, + [FEAT_PARAM_DSIPLL_REGM] = { 0, (1 << 11) - 1 }, + [FEAT_PARAM_DSIPLL_REGM_DISPC] = { 0, (1 << 4) - 1 }, + [FEAT_PARAM_DSIPLL_REGM_DSI] = { 0, (1 << 4) - 1 }, + [FEAT_PARAM_DSIPLL_FINT] = { 750000, 2100000 }, + [FEAT_PARAM_DSIPLL_LPDIV] = { 1, (1 << 13) - 1}, }; static const struct dss_param_range omap4_dss_param_range[] = { - [FEAT_PARAM_DSS_FCK] = { 0, 186000000 }, + [FEAT_PARAM_DSS_FCK] = { 0, 186000000 }, + [FEAT_PARAM_DSIPLL_REGN] = { 0, (1 << 8) - 1 }, + [FEAT_PARAM_DSIPLL_REGM] = { 0, (1 << 12) - 1 }, + [FEAT_PARAM_DSIPLL_REGM_DISPC] = { 0, (1 << 5) - 1 }, + [FEAT_PARAM_DSIPLL_REGM_DSI] = { 0, (1 << 5) - 1 }, + [FEAT_PARAM_DSIPLL_FINT] = { 500000, 2500000 }, + [FEAT_PARAM_DSIPLL_LPDIV] = { 0, (1 << 13) - 1 }, }; /* OMAP2 DSS Features */ diff --git a/drivers/video/omap2/dss/dss_features.h b/drivers/video/omap2/dss/dss_features.h index da63bbf38e90..12e9c4ef0dec 100644 --- a/drivers/video/omap2/dss/dss_features.h +++ b/drivers/video/omap2/dss/dss_features.h @@ -52,10 +52,20 @@ enum dss_feat_reg_field { FEAT_REG_HORIZONTALACCU, FEAT_REG_VERTICALACCU, FEAT_REG_DISPC_CLK_SWITCH, + FEAT_REG_DSIPLL_REGN, + FEAT_REG_DSIPLL_REGM, + FEAT_REG_DSIPLL_REGM_DISPC, + FEAT_REG_DSIPLL_REGM_DSI, }; enum dss_range_param { FEAT_PARAM_DSS_FCK, + FEAT_PARAM_DSIPLL_REGN, + FEAT_PARAM_DSIPLL_REGM, + FEAT_PARAM_DSIPLL_REGM_DISPC, + FEAT_PARAM_DSIPLL_REGM_DSI, + FEAT_PARAM_DSIPLL_FINT, + FEAT_PARAM_DSIPLL_LPDIV, }; /* DSS Feature Functions */ From 69b281a61442f97e8df14babc9bb6a28624886b1 Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Wed, 2 Mar 2011 14:44:27 +0200 Subject: [PATCH 064/140] OMAP: DSS2: DSI: Restructure IRQ handler Clean up the IRQ handler a bit by separating collection of IRQ stats and handling of IRQ errors to separate functions. Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dsi.c | 127 ++++++++++++++++++++-------------- 1 file changed, 75 insertions(+), 52 deletions(-) diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c index 7a4b4404a976..b6c08a6f2da1 100644 --- a/drivers/video/omap2/dss/dsi.c +++ b/drivers/video/omap2/dss/dsi.c @@ -477,26 +477,33 @@ static void print_irq_status_cio(u32 status) printk("\n"); } -static int debug_irq; - -/* called from dss */ -static irqreturn_t omap_dsi_irq_handler(int irq, void *arg) +#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS +static void dsi_collect_irq_stats(u32 irqstatus, u32 *vcstatus, u32 ciostatus) { - u32 irqstatus, vcstatus, ciostatus; int i; - irqstatus = dsi_read_reg(DSI_IRQSTATUS); - - /* IRQ is not for us */ - if (!irqstatus) - return IRQ_NONE; - -#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS spin_lock(&dsi.irq_stats_lock); + dsi.irq_stats.irq_count++; dss_collect_irq_stats(irqstatus, dsi.irq_stats.dsi_irqs); + + for (i = 0; i < 4; ++i) + dss_collect_irq_stats(vcstatus[i], dsi.irq_stats.vc_irqs[i]); + + dss_collect_irq_stats(ciostatus, dsi.irq_stats.cio_irqs); + + spin_unlock(&dsi.irq_stats_lock); +} +#else +#define dsi_collect_irq_stats(irqstatus, vcstatus, ciostatus) #endif +static int debug_irq; + +static void dsi_handle_irq_errors(u32 irqstatus, u32 *vcstatus, u32 ciostatus) +{ + int i; + if (irqstatus & DSI_IRQ_ERROR_MASK) { DSSERR("DSI error, irqstatus %x\n", irqstatus); print_irq_status(irqstatus); @@ -507,37 +514,48 @@ static irqreturn_t omap_dsi_irq_handler(int irq, void *arg) print_irq_status(irqstatus); } -#ifdef DSI_CATCH_MISSING_TE - if (irqstatus & DSI_IRQ_TE_TRIGGER) - del_timer(&dsi.te_timer); -#endif + for (i = 0; i < 4; ++i) { + if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) { + DSSERR("DSI VC(%d) error, vc irqstatus %x\n", + i, vcstatus[i]); + print_irq_status_vc(i, vcstatus[i]); + } else if (debug_irq) { + print_irq_status_vc(i, vcstatus[i]); + } + } + + if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) { + DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus); + print_irq_status_cio(ciostatus); + } else if (debug_irq) { + print_irq_status_cio(ciostatus); + } +} + +static irqreturn_t omap_dsi_irq_handler(int irq, void *arg) +{ + u32 irqstatus, vcstatus[4], ciostatus; + int i; + + irqstatus = dsi_read_reg(DSI_IRQSTATUS); + + /* IRQ is not for us */ + if (!irqstatus) + return IRQ_NONE; + + dsi_write_reg(DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK); + /* flush posted write */ + dsi_read_reg(DSI_IRQSTATUS); for (i = 0; i < 4; ++i) { - if ((irqstatus & (1< Date: Wed, 2 Mar 2011 14:47:04 +0200 Subject: [PATCH 065/140] OMAP: DSS2: DSI: Add ISR support Add generic ISR support for DSI interrupts. ISRs can be used instead of custom hooks in the interrupt handler. Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dsi.c | 329 +++++++++++++++++++++++++++++++--- 1 file changed, 304 insertions(+), 25 deletions(-) diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c index b6c08a6f2da1..8613ec489410 100644 --- a/drivers/video/omap2/dss/dsi.c +++ b/drivers/video/omap2/dss/dsi.c @@ -185,6 +185,16 @@ struct dsi_reg { u16 idx; }; #define DSI_DT_RX_SHORT_READ_1 0x21 #define DSI_DT_RX_SHORT_READ_2 0x22 +typedef void (*omap_dsi_isr_t) (void *arg, u32 mask); + +#define DSI_MAX_NR_ISRS 2 + +struct dsi_isr_data { + omap_dsi_isr_t isr; + void *arg; + u32 mask; +}; + enum fifo_size { DSI_FIFO_SIZE_0 = 0, DSI_FIFO_SIZE_32 = 1, @@ -211,6 +221,12 @@ struct dsi_irq_stats { unsigned cio_irqs[32]; }; +struct dsi_isr_tables { + struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS]; + struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS]; + struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS]; +}; + static struct { struct platform_device *pdev; @@ -236,6 +252,11 @@ static struct struct completion bta_completion; void (*bta_callback)(void); + spinlock_t irq_lock; + struct dsi_isr_tables isr_tables; + /* space for a copy used by the interrupt handler */ + struct dsi_isr_tables isr_tables_copy; + int update_channel; struct dsi_update_region update_region; @@ -532,16 +553,56 @@ static void dsi_handle_irq_errors(u32 irqstatus, u32 *vcstatus, u32 ciostatus) } } +static void dsi_call_isrs(struct dsi_isr_data *isr_array, + unsigned isr_array_size, u32 irqstatus) +{ + struct dsi_isr_data *isr_data; + int i; + + for (i = 0; i < isr_array_size; i++) { + isr_data = &isr_array[i]; + if (isr_data->isr && isr_data->mask & irqstatus) + isr_data->isr(isr_data->arg, irqstatus); + } +} + +static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables, + u32 irqstatus, u32 *vcstatus, u32 ciostatus) +{ + int i; + + dsi_call_isrs(isr_tables->isr_table, + ARRAY_SIZE(isr_tables->isr_table), + irqstatus); + + for (i = 0; i < 4; ++i) { + if (vcstatus[i] == 0) + continue; + dsi_call_isrs(isr_tables->isr_table_vc[i], + ARRAY_SIZE(isr_tables->isr_table_vc[i]), + vcstatus[i]); + } + + if (ciostatus != 0) + dsi_call_isrs(isr_tables->isr_table_cio, + ARRAY_SIZE(isr_tables->isr_table_cio), + ciostatus); +} + static irqreturn_t omap_dsi_irq_handler(int irq, void *arg) { u32 irqstatus, vcstatus[4], ciostatus; int i; + spin_lock(&dsi.irq_lock); + irqstatus = dsi_read_reg(DSI_IRQSTATUS); /* IRQ is not for us */ - if (!irqstatus) + if (!irqstatus) { + spin_unlock(&dsi.irq_lock); return IRQ_NONE; + } dsi_write_reg(DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK); /* flush posted write */ @@ -587,6 +648,14 @@ static irqreturn_t omap_dsi_irq_handler(int irq, void *arg) } } + /* make a copy and unlock, so that isrs can unregister + * themselves */ + memcpy(&dsi.isr_tables_copy, &dsi.isr_tables, sizeof(dsi.isr_tables)); + + spin_unlock(&dsi.irq_lock); + + dsi_handle_isrs(&dsi.isr_tables_copy, irqstatus, vcstatus, ciostatus); + dsi_handle_irq_errors(irqstatus, vcstatus, ciostatus); dsi_collect_irq_stats(irqstatus, vcstatus, ciostatus); @@ -594,42 +663,251 @@ static irqreturn_t omap_dsi_irq_handler(int irq, void *arg) return IRQ_HANDLED; } -static void _dsi_initialize_irq(void) +/* dsi.irq_lock has to be locked by the caller */ +static void _omap_dsi_configure_irqs(struct dsi_isr_data *isr_array, + unsigned isr_array_size, u32 default_mask, + const struct dsi_reg enable_reg, + const struct dsi_reg status_reg) { - u32 l; + struct dsi_isr_data *isr_data; + u32 mask; + u32 old_mask; int i; - /* disable all interrupts */ - dsi_write_reg(DSI_IRQENABLE, 0); - for (i = 0; i < 4; ++i) - dsi_write_reg(DSI_VC_IRQENABLE(i), 0); - dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE, 0); + mask = default_mask; - /* clear interrupt status */ - l = dsi_read_reg(DSI_IRQSTATUS); - dsi_write_reg(DSI_IRQSTATUS, l & ~DSI_IRQ_CHANNEL_MASK); + for (i = 0; i < isr_array_size; i++) { + isr_data = &isr_array[i]; - for (i = 0; i < 4; ++i) { - l = dsi_read_reg(DSI_VC_IRQSTATUS(i)); - dsi_write_reg(DSI_VC_IRQSTATUS(i), l); + if (isr_data->isr == NULL) + continue; + + mask |= isr_data->mask; } - l = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS); - dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, l); + old_mask = dsi_read_reg(enable_reg); + /* clear the irqstatus for newly enabled irqs */ + dsi_write_reg(status_reg, (mask ^ old_mask) & mask); + dsi_write_reg(enable_reg, mask); - /* enable error irqs */ - l = DSI_IRQ_ERROR_MASK; + /* flush posted writes */ + dsi_read_reg(enable_reg); + dsi_read_reg(status_reg); +} + +/* dsi.irq_lock has to be locked by the caller */ +static void _omap_dsi_set_irqs(void) +{ + u32 mask = DSI_IRQ_ERROR_MASK; #ifdef DSI_CATCH_MISSING_TE - l |= DSI_IRQ_TE_TRIGGER; + mask |= DSI_IRQ_TE_TRIGGER; #endif - dsi_write_reg(DSI_IRQENABLE, l); + _omap_dsi_configure_irqs(dsi.isr_tables.isr_table, + ARRAY_SIZE(dsi.isr_tables.isr_table), mask, + DSI_IRQENABLE, DSI_IRQSTATUS); +} - l = DSI_VC_IRQ_ERROR_MASK; - for (i = 0; i < 4; ++i) - dsi_write_reg(DSI_VC_IRQENABLE(i), l); +/* dsi.irq_lock has to be locked by the caller */ +static void _omap_dsi_set_irqs_vc(int vc) +{ + _omap_dsi_configure_irqs(dsi.isr_tables.isr_table_vc[vc], + ARRAY_SIZE(dsi.isr_tables.isr_table_vc[vc]), + DSI_VC_IRQ_ERROR_MASK, + DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc)); +} - l = DSI_CIO_IRQ_ERROR_MASK; - dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE, l); +/* dsi.irq_lock has to be locked by the caller */ +static void _omap_dsi_set_irqs_cio(void) +{ + _omap_dsi_configure_irqs(dsi.isr_tables.isr_table_cio, + ARRAY_SIZE(dsi.isr_tables.isr_table_cio), + DSI_CIO_IRQ_ERROR_MASK, + DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS); +} + +static void _dsi_initialize_irq(void) +{ + unsigned long flags; + int vc; + + spin_lock_irqsave(&dsi.irq_lock, flags); + + memset(&dsi.isr_tables, 0, sizeof(dsi.isr_tables)); + + _omap_dsi_set_irqs(); + for (vc = 0; vc < 4; ++vc) + _omap_dsi_set_irqs_vc(vc); + _omap_dsi_set_irqs_cio(); + + spin_unlock_irqrestore(&dsi.irq_lock, flags); +} + +static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask, + struct dsi_isr_data *isr_array, unsigned isr_array_size) +{ + struct dsi_isr_data *isr_data; + int free_idx; + int i; + + BUG_ON(isr == NULL); + + /* check for duplicate entry and find a free slot */ + free_idx = -1; + for (i = 0; i < isr_array_size; i++) { + isr_data = &isr_array[i]; + + if (isr_data->isr == isr && isr_data->arg == arg && + isr_data->mask == mask) { + return -EINVAL; + } + + if (isr_data->isr == NULL && free_idx == -1) + free_idx = i; + } + + if (free_idx == -1) + return -EBUSY; + + isr_data = &isr_array[free_idx]; + isr_data->isr = isr; + isr_data->arg = arg; + isr_data->mask = mask; + + return 0; +} + +static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask, + struct dsi_isr_data *isr_array, unsigned isr_array_size) +{ + struct dsi_isr_data *isr_data; + int i; + + for (i = 0; i < isr_array_size; i++) { + isr_data = &isr_array[i]; + if (isr_data->isr != isr || isr_data->arg != arg || + isr_data->mask != mask) + continue; + + isr_data->isr = NULL; + isr_data->arg = NULL; + isr_data->mask = 0; + + return 0; + } + + return -EINVAL; +} + +static int dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask) +{ + unsigned long flags; + int r; + + spin_lock_irqsave(&dsi.irq_lock, flags); + + r = _dsi_register_isr(isr, arg, mask, dsi.isr_tables.isr_table, + ARRAY_SIZE(dsi.isr_tables.isr_table)); + + if (r == 0) + _omap_dsi_set_irqs(); + + spin_unlock_irqrestore(&dsi.irq_lock, flags); + + return r; +} + +static int dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask) +{ + unsigned long flags; + int r; + + spin_lock_irqsave(&dsi.irq_lock, flags); + + r = _dsi_unregister_isr(isr, arg, mask, dsi.isr_tables.isr_table, + ARRAY_SIZE(dsi.isr_tables.isr_table)); + + if (r == 0) + _omap_dsi_set_irqs(); + + spin_unlock_irqrestore(&dsi.irq_lock, flags); + + return r; +} + +static int dsi_register_isr_vc(int channel, omap_dsi_isr_t isr, void *arg, + u32 mask) +{ + unsigned long flags; + int r; + + spin_lock_irqsave(&dsi.irq_lock, flags); + + r = _dsi_register_isr(isr, arg, mask, + dsi.isr_tables.isr_table_vc[channel], + ARRAY_SIZE(dsi.isr_tables.isr_table_vc[channel])); + + if (r == 0) + _omap_dsi_set_irqs_vc(channel); + + spin_unlock_irqrestore(&dsi.irq_lock, flags); + + return r; +} + +static int dsi_unregister_isr_vc(int channel, omap_dsi_isr_t isr, void *arg, + u32 mask) +{ + unsigned long flags; + int r; + + spin_lock_irqsave(&dsi.irq_lock, flags); + + r = _dsi_unregister_isr(isr, arg, mask, + dsi.isr_tables.isr_table_vc[channel], + ARRAY_SIZE(dsi.isr_tables.isr_table_vc[channel])); + + if (r == 0) + _omap_dsi_set_irqs_vc(channel); + + spin_unlock_irqrestore(&dsi.irq_lock, flags); + + return r; +} + +static int dsi_register_isr_cio(omap_dsi_isr_t isr, void *arg, u32 mask) +{ + unsigned long flags; + int r; + + spin_lock_irqsave(&dsi.irq_lock, flags); + + r = _dsi_register_isr(isr, arg, mask, dsi.isr_tables.isr_table_cio, + ARRAY_SIZE(dsi.isr_tables.isr_table_cio)); + + if (r == 0) + _omap_dsi_set_irqs_cio(); + + spin_unlock_irqrestore(&dsi.irq_lock, flags); + + return r; +} + +static int dsi_unregister_isr_cio(omap_dsi_isr_t isr, void *arg, u32 mask) +{ + unsigned long flags; + int r; + + spin_lock_irqsave(&dsi.irq_lock, flags); + + r = _dsi_unregister_isr(isr, arg, mask, dsi.isr_tables.isr_table_cio, + ARRAY_SIZE(dsi.isr_tables.isr_table_cio)); + + if (r == 0) + _omap_dsi_set_irqs_cio(); + + spin_unlock_irqrestore(&dsi.irq_lock, flags); + + return r; } static u32 dsi_get_errors(void) @@ -3383,6 +3661,7 @@ static int dsi_init(struct platform_device *pdev) int r, i; struct resource *dsi_mem; + spin_lock_init(&dsi.irq_lock); spin_lock_init(&dsi.errors_lock); dsi.errors = 0; From f36a06e702ef804a99ce3a286514d84610a74db5 Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Wed, 2 Mar 2011 14:48:41 +0200 Subject: [PATCH 066/140] OMAP: DSS2: DSI: use ISR in send_bta_sync Remove bta_completion handling from the interrupt handler, and use ISR support instead. Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dsi.c | 32 ++++++++++++++++++-------------- 1 file changed, 18 insertions(+), 14 deletions(-) diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c index 8613ec489410..18b72521ee7e 100644 --- a/drivers/video/omap2/dss/dsi.c +++ b/drivers/video/omap2/dss/dsi.c @@ -249,7 +249,6 @@ static struct unsigned pll_locked; - struct completion bta_completion; void (*bta_callback)(void); spinlock_t irq_lock; @@ -338,6 +337,11 @@ static bool dsi_bus_is_locked(void) return dsi.bus_lock.count == 0; } +static void dsi_completion_handler(void *data, u32 mask) +{ + complete((struct completion *)data); +} + static inline int wait_for_bit_change(const struct dsi_reg idx, int bitnum, int value) { @@ -641,8 +645,6 @@ static irqreturn_t omap_dsi_irq_handler(int irq, void *arg) continue; if (vcstatus[i] & DSI_VC_IRQ_BTA) { - complete(&dsi.bta_completion); - if (dsi.bta_callback) dsi.bta_callback(); } @@ -2263,33 +2265,37 @@ static int dsi_vc_send_bta(int channel) int dsi_vc_send_bta_sync(int channel) { + DECLARE_COMPLETION_ONSTACK(completion); int r = 0; u32 err; - INIT_COMPLETION(dsi.bta_completion); - - dsi_vc_enable_bta_irq(channel); + r = dsi_register_isr_vc(channel, dsi_completion_handler, + &completion, DSI_VC_IRQ_BTA); + if (r) + goto err0; r = dsi_vc_send_bta(channel); if (r) - goto err; + goto err1; - if (wait_for_completion_timeout(&dsi.bta_completion, + if (wait_for_completion_timeout(&completion, msecs_to_jiffies(500)) == 0) { DSSERR("Failed to receive BTA\n"); r = -EIO; - goto err; + goto err1; } err = dsi_get_errors(); if (err) { DSSERR("Error while sending BTA: %x\n", err); r = -EIO; - goto err; + goto err1; } -err: - dsi_vc_disable_bta_irq(channel); +err1: + dsi_unregister_isr_vc(channel, dsi_completion_handler, + &completion, DSI_VC_IRQ_BTA); +err0: return r; } EXPORT_SYMBOL(dsi_vc_send_bta_sync); @@ -3670,8 +3676,6 @@ static int dsi_init(struct platform_device *pdev) dsi.irq_stats.last_reset = jiffies; #endif - init_completion(&dsi.bta_completion); - mutex_init(&dsi.lock); sema_init(&dsi.bus_lock, 1); From f34bd465cae57bcce11fb7f953cfcbb18222b99e Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Wed, 2 Mar 2011 14:52:48 +0200 Subject: [PATCH 067/140] OMAP: DSS2: DSI: use ISR for BTA in framedone Remove bta_callback from the interrupt handler, and use ISR support instead. Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dsi.c | 57 +++++++++-------------------------- 1 file changed, 15 insertions(+), 42 deletions(-) diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c index 18b72521ee7e..cd872e9d7989 100644 --- a/drivers/video/omap2/dss/dsi.c +++ b/drivers/video/omap2/dss/dsi.c @@ -249,8 +249,6 @@ static struct unsigned pll_locked; - void (*bta_callback)(void); - spinlock_t irq_lock; struct dsi_isr_tables isr_tables; /* space for a copy used by the interrupt handler */ @@ -640,16 +638,6 @@ static irqreturn_t omap_dsi_irq_handler(int irq, void *arg) del_timer(&dsi.te_timer); #endif - for (i = 0; i < 4; ++i) { - if (vcstatus[i] == 0) - continue; - - if (vcstatus[i] & DSI_VC_IRQ_BTA) { - if (dsi.bta_callback) - dsi.bta_callback(); - } - } - /* make a copy and unlock, so that isrs can unregister * themselves */ memcpy(&dsi.isr_tables_copy, &dsi.isr_tables, sizeof(dsi.isr_tables)); @@ -923,26 +911,6 @@ static u32 dsi_get_errors(void) return e; } -static void dsi_vc_enable_bta_irq(int channel) -{ - u32 l; - - dsi_write_reg(DSI_VC_IRQSTATUS(channel), DSI_VC_IRQ_BTA); - - l = dsi_read_reg(DSI_VC_IRQENABLE(channel)); - l |= DSI_VC_IRQ_BTA; - dsi_write_reg(DSI_VC_IRQENABLE(channel), l); -} - -static void dsi_vc_disable_bta_irq(int channel) -{ - u32 l; - - l = dsi_read_reg(DSI_VC_IRQENABLE(channel)); - l &= ~DSI_VC_IRQ_BTA; - dsi_write_reg(DSI_VC_IRQENABLE(channel), l); -} - /* DSI func clock. this could also be dsi_pll_hsdiv_dsi_clk */ static inline void enable_clocks(bool enable) { @@ -3109,19 +3077,20 @@ static void dsi_te_timeout(unsigned long arg) } #endif +static void dsi_framedone_bta_callback(void *data, u32 mask); + static void dsi_handle_framedone(int error) { const int channel = dsi.update_channel; - cancel_delayed_work(&dsi.framedone_timeout_work); + dsi_unregister_isr_vc(channel, dsi_framedone_bta_callback, + NULL, DSI_VC_IRQ_BTA); - dsi_vc_disable_bta_irq(channel); + cancel_delayed_work(&dsi.framedone_timeout_work); /* SIDLEMODE back to smart-idle */ dispc_enable_sidle(); - dsi.bta_callback = NULL; - if (dsi.te_enabled) { /* enable LP_RX_TO again after the TE */ REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */ @@ -3155,7 +3124,7 @@ static void dsi_framedone_timeout_work_callback(struct work_struct *work) dsi_handle_framedone(-ETIMEDOUT); } -static void dsi_framedone_bta_callback(void) +static void dsi_framedone_bta_callback(void *data, u32 mask) { dsi_handle_framedone(0); @@ -3195,15 +3164,19 @@ static void dsi_framedone_irq_callback(void *data, u32 mask) * asynchronously. * */ - dsi.bta_callback = dsi_framedone_bta_callback; - - barrier(); - - dsi_vc_enable_bta_irq(channel); + r = dsi_register_isr_vc(channel, dsi_framedone_bta_callback, + NULL, DSI_VC_IRQ_BTA); + if (r) { + DSSERR("Failed to register BTA ISR\n"); + dsi_handle_framedone(-EIO); + return; + } r = dsi_vc_send_bta(channel); if (r) { DSSERR("BTA after framedone failed\n"); + dsi_unregister_isr_vc(channel, dsi_framedone_bta_callback, + NULL, DSI_VC_IRQ_BTA); dsi_handle_framedone(-EIO); } } From 773b30b22f8c5ac4ccc52775c17809cc5826cb86 Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Fri, 8 Oct 2010 16:15:25 +0300 Subject: [PATCH 068/140] OMAP: DSS2: DSI: catch DSI errors in send_bta_sync dsi_vc_send_bta_sync() waits for BTA interrupt with a 500ms timeout. If a DSI error happens, no BTA is received and the timeout triggers. This could be handled much faster by listening to DSI errors also. This patch uses the ISR support to notice DSI errors while waiting for the BTA, thus speeding up the fail-path considerably. Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dsi.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c index cd872e9d7989..37226628bc0f 100644 --- a/drivers/video/omap2/dss/dsi.c +++ b/drivers/video/omap2/dss/dsi.c @@ -2242,24 +2242,31 @@ int dsi_vc_send_bta_sync(int channel) if (r) goto err0; - r = dsi_vc_send_bta(channel); + r = dsi_register_isr(dsi_completion_handler, &completion, + DSI_IRQ_ERROR_MASK); if (r) goto err1; + r = dsi_vc_send_bta(channel); + if (r) + goto err2; + if (wait_for_completion_timeout(&completion, msecs_to_jiffies(500)) == 0) { DSSERR("Failed to receive BTA\n"); r = -EIO; - goto err1; + goto err2; } err = dsi_get_errors(); if (err) { DSSERR("Error while sending BTA: %x\n", err); r = -EIO; - goto err1; + goto err2; } - +err2: + dsi_unregister_isr(dsi_completion_handler, &completion, + DSI_IRQ_ERROR_MASK); err1: dsi_unregister_isr_vc(channel, dsi_completion_handler, &completion, DSI_VC_IRQ_BTA); From d80d499ed926e70b429d309360f5910d5ad54788 Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Wed, 2 Mar 2011 15:53:07 +0200 Subject: [PATCH 069/140] OMAP: DSS2: DSI: fix IRQ debug prints print_irq_status functions can be called with empty irq status when full irq debugging is enabled. This patch makes print_irq_status functions return immediately when given an empty irq status to lessen the debug spam slightly. Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dsi.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c index 37226628bc0f..0a7f1a47f8e3 100644 --- a/drivers/video/omap2/dss/dsi.c +++ b/drivers/video/omap2/dss/dsi.c @@ -409,6 +409,9 @@ static void dsi_perf_show(const char *name) static void print_irq_status(u32 status) { + if (status == 0) + return; + #ifndef VERBOSE_IRQ if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0) return; @@ -444,6 +447,9 @@ static void print_irq_status(u32 status) static void print_irq_status_vc(int channel, u32 status) { + if (status == 0) + return; + #ifndef VERBOSE_IRQ if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0) return; @@ -470,6 +476,9 @@ static void print_irq_status_vc(int channel, u32 status) static void print_irq_status_cio(u32 status) { + if (status == 0) + return; + printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status); #define PIS(x) \ From b119601d4e226e42a067ff33116774d79dd9afbc Mon Sep 17 00:00:00 2001 From: Mythri P K Date: Tue, 8 Mar 2011 17:15:54 +0530 Subject: [PATCH 070/140] OMAP4: DSS2: Add display type HDMI to DSS2 Adding display type HDMI in dss_features, overlay and the manager so that HDMI type of display will be recognized. Signed-off-by: Mythri P K Signed-off-by: Tomi Valkeinen --- arch/arm/plat-omap/include/plat/display.h | 1 + drivers/video/omap2/dss/display.c | 2 ++ drivers/video/omap2/dss/dss_features.c | 2 +- drivers/video/omap2/dss/manager.c | 9 +++++++-- drivers/video/omap2/dss/overlay.c | 6 ++++-- 5 files changed, 15 insertions(+), 5 deletions(-) diff --git a/arch/arm/plat-omap/include/plat/display.h b/arch/arm/plat-omap/include/plat/display.h index e81ca66dfbb4..5e04ddc18fa8 100644 --- a/arch/arm/plat-omap/include/plat/display.h +++ b/arch/arm/plat-omap/include/plat/display.h @@ -58,6 +58,7 @@ enum omap_display_type { OMAP_DISPLAY_TYPE_SDI = 1 << 2, OMAP_DISPLAY_TYPE_DSI = 1 << 3, OMAP_DISPLAY_TYPE_VENC = 1 << 4, + OMAP_DISPLAY_TYPE_HDMI = 1 << 5, }; enum omap_plane { diff --git a/drivers/video/omap2/dss/display.c b/drivers/video/omap2/dss/display.c index 7d96b724c992..c40bcbd2e140 100644 --- a/drivers/video/omap2/dss/display.c +++ b/drivers/video/omap2/dss/display.c @@ -342,6 +342,7 @@ int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev) return 16; case OMAP_DISPLAY_TYPE_VENC: case OMAP_DISPLAY_TYPE_SDI: + case OMAP_DISPLAY_TYPE_HDMI: return 24; default: BUG(); @@ -368,6 +369,7 @@ bool dss_use_replication(struct omap_dss_device *dssdev, case OMAP_DISPLAY_TYPE_DPI: bpp = dssdev->phy.dpi.data_lines; break; + case OMAP_DISPLAY_TYPE_HDMI: case OMAP_DISPLAY_TYPE_VENC: case OMAP_DISPLAY_TYPE_SDI: bpp = 24; diff --git a/drivers/video/omap2/dss/dss_features.c b/drivers/video/omap2/dss/dss_features.c index 06b18f73449b..aa1622241d0d 100644 --- a/drivers/video/omap2/dss/dss_features.c +++ b/drivers/video/omap2/dss/dss_features.c @@ -130,7 +130,7 @@ static const enum omap_display_type omap4_dss_supported_displays[] = { OMAP_DISPLAY_TYPE_DBI | OMAP_DISPLAY_TYPE_DSI, /* OMAP_DSS_CHANNEL_DIGIT */ - OMAP_DISPLAY_TYPE_VENC, + OMAP_DISPLAY_TYPE_VENC | OMAP_DISPLAY_TYPE_HDMI, /* OMAP_DSS_CHANNEL_LCD2 */ OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI | diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c index 1f53bf20b6cb..bcd37ec86952 100644 --- a/drivers/video/omap2/dss/manager.c +++ b/drivers/video/omap2/dss/manager.c @@ -515,6 +515,8 @@ static int dss_mgr_wait_for_vsync(struct omap_overlay_manager *mgr) if (mgr->device->type == OMAP_DISPLAY_TYPE_VENC) { irq = DISPC_IRQ_EVSYNC_ODD; + } else if (mgr->device->type == OMAP_DISPLAY_TYPE_HDMI) { + irq = DISPC_IRQ_EVSYNC_EVEN; } else { if (mgr->id == OMAP_DSS_CHANNEL_LCD) irq = DISPC_IRQ_VSYNC; @@ -536,7 +538,8 @@ static int dss_mgr_wait_for_go(struct omap_overlay_manager *mgr) if (!dssdev || dssdev->state != OMAP_DSS_DISPLAY_ACTIVE) return 0; - if (dssdev->type == OMAP_DISPLAY_TYPE_VENC) { + if (dssdev->type == OMAP_DISPLAY_TYPE_VENC + || dssdev->type == OMAP_DISPLAY_TYPE_HDMI) { irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN; } else { if (dssdev->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE) { @@ -613,7 +616,8 @@ int dss_mgr_wait_for_go_ovl(struct omap_overlay *ovl) if (!dssdev || dssdev->state != OMAP_DSS_DISPLAY_ACTIVE) return 0; - if (dssdev->type == OMAP_DISPLAY_TYPE_VENC) { + if (dssdev->type == OMAP_DISPLAY_TYPE_VENC + || dssdev->type == OMAP_DISPLAY_TYPE_HDMI) { irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN; } else { if (dssdev->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE) { @@ -1377,6 +1381,7 @@ static int omap_dss_mgr_apply(struct omap_overlay_manager *mgr) case OMAP_DISPLAY_TYPE_DBI: case OMAP_DISPLAY_TYPE_SDI: case OMAP_DISPLAY_TYPE_VENC: + case OMAP_DISPLAY_TYPE_HDMI: default_get_overlay_fifo_thresholds(ovl->id, size, &oc->burst_size, &oc->fifo_low, &oc->fifo_high); diff --git a/drivers/video/omap2/dss/overlay.c b/drivers/video/omap2/dss/overlay.c index 996e9a4f6771..f1aca6d04011 100644 --- a/drivers/video/omap2/dss/overlay.c +++ b/drivers/video/omap2/dss/overlay.c @@ -679,7 +679,8 @@ void dss_recheck_connections(struct omap_dss_device *dssdev, bool force) lcd2_mgr->set_device(lcd2_mgr, dssdev); mgr = lcd2_mgr; } - } else if (dssdev->type != OMAP_DISPLAY_TYPE_VENC) { + } else if (dssdev->type != OMAP_DISPLAY_TYPE_VENC + && dssdev->type != OMAP_DISPLAY_TYPE_HDMI) { if (!lcd_mgr->device || force) { if (lcd_mgr->device) lcd_mgr->unset_device(lcd_mgr); @@ -688,7 +689,8 @@ void dss_recheck_connections(struct omap_dss_device *dssdev, bool force) } } - if (dssdev->type == OMAP_DISPLAY_TYPE_VENC) { + if (dssdev->type == OMAP_DISPLAY_TYPE_VENC + || dssdev->type == OMAP_DISPLAY_TYPE_HDMI) { if (!tv_mgr->device || force) { if (tv_mgr->device) tv_mgr->unset_device(tv_mgr); From 7ed024aa280cb38c8aa5c188d2d2c98f5daede10 Mon Sep 17 00:00:00 2001 From: Mythri P K Date: Wed, 9 Mar 2011 16:31:38 +0530 Subject: [PATCH 071/140] OMAP4: DSS2: HDMI: Select between HDMI VENC clock source. Adding function to select between HDMI or VENC clock source. Signed-off-by: Mythri P K Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dss.c | 5 +++++ drivers/video/omap2/dss/dss.h | 6 ++++++ 2 files changed, 11 insertions(+) diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c index 562d8d28d4f2..f1628bd850d1 100644 --- a/drivers/video/omap2/dss/dss.c +++ b/drivers/video/omap2/dss/dss.c @@ -605,6 +605,11 @@ void dss_set_dac_pwrdn_bgz(bool enable) REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */ } +void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select hdmi) +{ + REG_FLD_MOD(DSS_CONTROL, hdmi, 15, 15); /* VENC_HDMI_SWITCH */ +} + static int dss_init(void) { int r; diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h index 26a43c93e489..eb05d39ef17c 100644 --- a/drivers/video/omap2/dss/dss.h +++ b/drivers/video/omap2/dss/dss.h @@ -126,6 +126,11 @@ enum dss_clk_source { * OMAP4: DSS_FCLK */ }; +enum dss_hdmi_venc_clk_source_select { + DSS_VENC_TV_CLK = 0, + DSS_HDMI_M_PCLK = 1, +}; + struct dss_clock_info { /* rates that we get with dividers below */ unsigned long fck; @@ -214,6 +219,7 @@ void dss_recheck_connections(struct omap_dss_device *dssdev, bool force); int dss_init_platform_driver(void); void dss_uninit_platform_driver(void); +void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select); void dss_save_context(void); void dss_restore_context(void); void dss_clk_enable(enum dss_clock clks); From d3862610c95564a586951d5be291b9b0200d39fe Mon Sep 17 00:00:00 2001 From: Mythri P K Date: Fri, 11 Mar 2011 18:02:49 +0530 Subject: [PATCH 072/140] OMAP4: DSS2: HDMI: Dispc gamma enable set/reset function for TV. Adding function to reset/set gamma table bit for TV interface, currently only support for disabled is added. Signed-off-by: Mythri P K Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dispc.c | 14 ++++++++++++++ drivers/video/omap2/dss/dss.h | 1 + 2 files changed, 15 insertions(+) diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c index b8c576a0bc02..7804779c9da1 100644 --- a/drivers/video/omap2/dss/dispc.c +++ b/drivers/video/omap2/dss/dispc.c @@ -1008,6 +1008,20 @@ void dispc_set_burst_size(enum omap_plane plane, enable_clocks(0); } +void dispc_enable_gamma_table(bool enable) +{ + /* + * This is partially implemented to support only disabling of + * the gamma table. + */ + if (enable) { + DSSWARN("Gamma table enabling for TV not yet supported"); + return; + } + + REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9); +} + static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable) { u32 val; diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h index eb05d39ef17c..ab20270d761a 100644 --- a/drivers/video/omap2/dss/dss.h +++ b/drivers/video/omap2/dss/dss.h @@ -370,6 +370,7 @@ void dispc_set_plane_size(enum omap_plane plane, u16 width, u16 height); void dispc_set_channel_out(enum omap_plane plane, enum omap_channel channel_out); +void dispc_enable_gamma_table(bool enable); int dispc_setup_plane(enum omap_plane plane, u32 paddr, u16 screen_width, u16 pos_x, u16 pos_y, From 26adeece88ffe172db7e26f856b576cccfb0ec85 Mon Sep 17 00:00:00 2001 From: Mythri P K Date: Tue, 8 Mar 2011 17:27:56 +0530 Subject: [PATCH 073/140] OMAP4: DSS2: HDMI: HDMI driver header file addition Adding the hdmi interface driver header file (hdmi.h) to the dss driver. Register and structure declaration done here. Signed-off-by: Mythri P K Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/hdmi.h | 415 +++++++++++++++++++++++++++++++++ 1 file changed, 415 insertions(+) create mode 100644 drivers/video/omap2/dss/hdmi.h diff --git a/drivers/video/omap2/dss/hdmi.h b/drivers/video/omap2/dss/hdmi.h new file mode 100644 index 000000000000..9887ab96da3c --- /dev/null +++ b/drivers/video/omap2/dss/hdmi.h @@ -0,0 +1,415 @@ +/* + * hdmi.h + * + * HDMI driver definition for TI OMAP4 processors. + * + * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#ifndef _OMAP4_DSS_HDMI_H_ +#define _OMAP4_DSS_HDMI_H_ + +#include +#include + +#define HDMI_WP 0x0 +#define HDMI_CORE_SYS 0x400 +#define HDMI_CORE_AV 0x900 +#define HDMI_PLLCTRL 0x200 +#define HDMI_PHY 0x300 + +struct hdmi_reg { u16 idx; }; + +#define HDMI_REG(idx) ((const struct hdmi_reg) { idx }) + +/* HDMI Wrapper */ +#define HDMI_WP_REG(idx) HDMI_REG(HDMI_WP + idx) + +#define HDMI_WP_REVISION HDMI_WP_REG(0x0) +#define HDMI_WP_SYSCONFIG HDMI_WP_REG(0x10) +#define HDMI_WP_IRQSTATUS_RAW HDMI_WP_REG(0x24) +#define HDMI_WP_IRQSTATUS HDMI_WP_REG(0x28) +#define HDMI_WP_PWR_CTRL HDMI_WP_REG(0x40) +#define HDMI_WP_IRQENABLE_SET HDMI_WP_REG(0x2C) +#define HDMI_WP_VIDEO_CFG HDMI_WP_REG(0x50) +#define HDMI_WP_VIDEO_SIZE HDMI_WP_REG(0x60) +#define HDMI_WP_VIDEO_TIMING_H HDMI_WP_REG(0x68) +#define HDMI_WP_VIDEO_TIMING_V HDMI_WP_REG(0x6C) +#define HDMI_WP_WP_CLK HDMI_WP_REG(0x70) + +/* HDMI IP Core System */ +#define HDMI_CORE_SYS_REG(idx) HDMI_REG(HDMI_CORE_SYS + idx) + +#define HDMI_CORE_SYS_VND_IDL HDMI_CORE_SYS_REG(0x0) +#define HDMI_CORE_SYS_DEV_IDL HDMI_CORE_SYS_REG(0x8) +#define HDMI_CORE_SYS_DEV_IDH HDMI_CORE_SYS_REG(0xC) +#define HDMI_CORE_SYS_DEV_REV HDMI_CORE_SYS_REG(0x10) +#define HDMI_CORE_SYS_SRST HDMI_CORE_SYS_REG(0x14) +#define HDMI_CORE_CTRL1 HDMI_CORE_SYS_REG(0x20) +#define HDMI_CORE_SYS_SYS_STAT HDMI_CORE_SYS_REG(0x24) +#define HDMI_CORE_SYS_VID_ACEN HDMI_CORE_SYS_REG(0x124) +#define HDMI_CORE_SYS_VID_MODE HDMI_CORE_SYS_REG(0x128) +#define HDMI_CORE_SYS_INTR_STATE HDMI_CORE_SYS_REG(0x1C0) +#define HDMI_CORE_SYS_INTR1 HDMI_CORE_SYS_REG(0x1C4) +#define HDMI_CORE_SYS_INTR2 HDMI_CORE_SYS_REG(0x1C8) +#define HDMI_CORE_SYS_INTR3 HDMI_CORE_SYS_REG(0x1CC) +#define HDMI_CORE_SYS_INTR4 HDMI_CORE_SYS_REG(0x1D0) +#define HDMI_CORE_SYS_UMASK1 HDMI_CORE_SYS_REG(0x1D4) +#define HDMI_CORE_SYS_TMDS_CTRL HDMI_CORE_SYS_REG(0x208) +#define HDMI_CORE_SYS_DE_DLY HDMI_CORE_SYS_REG(0xC8) +#define HDMI_CORE_SYS_DE_CTRL HDMI_CORE_SYS_REG(0xCC) +#define HDMI_CORE_SYS_DE_TOP HDMI_CORE_SYS_REG(0xD0) +#define HDMI_CORE_SYS_DE_CNTL HDMI_CORE_SYS_REG(0xD8) +#define HDMI_CORE_SYS_DE_CNTH HDMI_CORE_SYS_REG(0xDC) +#define HDMI_CORE_SYS_DE_LINL HDMI_CORE_SYS_REG(0xE0) +#define HDMI_CORE_SYS_DE_LINH_1 HDMI_CORE_SYS_REG(0xE4) +#define HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC 0x1 +#define HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC 0x1 +#define HDMI_CORE_CTRL1_BSEL_24BITBUS 0x1 +#define HDMI_CORE_CTRL1_EDGE_RISINGEDGE 0x1 + +/* HDMI DDC E-DID */ +#define HDMI_CORE_DDC_CMD HDMI_CORE_SYS_REG(0x3CC) +#define HDMI_CORE_DDC_STATUS HDMI_CORE_SYS_REG(0x3C8) +#define HDMI_CORE_DDC_ADDR HDMI_CORE_SYS_REG(0x3B4) +#define HDMI_CORE_DDC_OFFSET HDMI_CORE_SYS_REG(0x3BC) +#define HDMI_CORE_DDC_COUNT1 HDMI_CORE_SYS_REG(0x3C0) +#define HDMI_CORE_DDC_COUNT2 HDMI_CORE_SYS_REG(0x3C4) +#define HDMI_CORE_DDC_DATA HDMI_CORE_SYS_REG(0x3D0) +#define HDMI_CORE_DDC_SEGM HDMI_CORE_SYS_REG(0x3B8) + +/* HDMI IP Core Audio Video */ +#define HDMI_CORE_AV_REG(idx) HDMI_REG(HDMI_CORE_AV + idx) + +#define HDMI_CORE_AV_HDMI_CTRL HDMI_CORE_AV_REG(0xBC) +#define HDMI_CORE_AV_DPD HDMI_CORE_AV_REG(0xF4) +#define HDMI_CORE_AV_PB_CTRL1 HDMI_CORE_AV_REG(0xF8) +#define HDMI_CORE_AV_PB_CTRL2 HDMI_CORE_AV_REG(0xFC) +#define HDMI_CORE_AV_AVI_TYPE HDMI_CORE_AV_REG(0x100) +#define HDMI_CORE_AV_AVI_VERS HDMI_CORE_AV_REG(0x104) +#define HDMI_CORE_AV_AVI_LEN HDMI_CORE_AV_REG(0x108) +#define HDMI_CORE_AV_AVI_CHSUM HDMI_CORE_AV_REG(0x10C) +#define HDMI_CORE_AV_AVI_DBYTE(n) HDMI_CORE_AV_REG(n * 4 + 0x110) +#define HDMI_CORE_AV_AVI_DBYTE_NELEMS HDMI_CORE_AV_REG(15) +#define HDMI_CORE_AV_SPD_DBYTE HDMI_CORE_AV_REG(0x190) +#define HDMI_CORE_AV_SPD_DBYTE_NELEMS HDMI_CORE_AV_REG(27) +#define HDMI_CORE_AV_MPEG_DBYTE HDMI_CORE_AV_REG(0x290) +#define HDMI_CORE_AV_MPEG_DBYTE_NELEMS HDMI_CORE_AV_REG(27) +#define HDMI_CORE_AV_GEN_DBYTE HDMI_CORE_AV_REG(0x300) +#define HDMI_CORE_AV_GEN_DBYTE_NELEMS HDMI_CORE_AV_REG(31) +#define HDMI_CORE_AV_GEN2_DBYTE HDMI_CORE_AV_REG(0x380) +#define HDMI_CORE_AV_GEN2_DBYTE_NELEMS HDMI_CORE_AV_REG(31) +#define HDMI_CORE_AV_ACR_CTRL HDMI_CORE_AV_REG(0x4) +#define HDMI_CORE_AV_FREQ_SVAL HDMI_CORE_AV_REG(0x8) +#define HDMI_CORE_AV_N_SVAL1 HDMI_CORE_AV_REG(0xC) +#define HDMI_CORE_AV_N_SVAL2 HDMI_CORE_AV_REG(0x10) +#define HDMI_CORE_AV_N_SVAL3 HDMI_CORE_AV_REG(0x14) +#define HDMI_CORE_AV_CTS_SVAL1 HDMI_CORE_AV_REG(0x18) +#define HDMI_CORE_AV_CTS_SVAL2 HDMI_CORE_AV_REG(0x1C) +#define HDMI_CORE_AV_CTS_SVAL3 HDMI_CORE_AV_REG(0x20) +#define HDMI_CORE_AV_CTS_HVAL1 HDMI_CORE_AV_REG(0x24) +#define HDMI_CORE_AV_CTS_HVAL2 HDMI_CORE_AV_REG(0x28) +#define HDMI_CORE_AV_CTS_HVAL3 HDMI_CORE_AV_REG(0x2C) +#define HDMI_CORE_AV_AUD_MODE HDMI_CORE_AV_REG(0x50) +#define HDMI_CORE_AV_SPDIF_CTRL HDMI_CORE_AV_REG(0x54) +#define HDMI_CORE_AV_HW_SPDIF_FS HDMI_CORE_AV_REG(0x60) +#define HDMI_CORE_AV_SWAP_I2S HDMI_CORE_AV_REG(0x64) +#define HDMI_CORE_AV_SPDIF_ERTH HDMI_CORE_AV_REG(0x6C) +#define HDMI_CORE_AV_I2S_IN_MAP HDMI_CORE_AV_REG(0x70) +#define HDMI_CORE_AV_I2S_IN_CTRL HDMI_CORE_AV_REG(0x74) +#define HDMI_CORE_AV_I2S_CHST0 HDMI_CORE_AV_REG(0x78) +#define HDMI_CORE_AV_I2S_CHST1 HDMI_CORE_AV_REG(0x7C) +#define HDMI_CORE_AV_I2S_CHST2 HDMI_CORE_AV_REG(0x80) +#define HDMI_CORE_AV_I2S_CHST4 HDMI_CORE_AV_REG(0x84) +#define HDMI_CORE_AV_I2S_CHST5 HDMI_CORE_AV_REG(0x88) +#define HDMI_CORE_AV_ASRC HDMI_CORE_AV_REG(0x8C) +#define HDMI_CORE_AV_I2S_IN_LEN HDMI_CORE_AV_REG(0x90) +#define HDMI_CORE_AV_HDMI_CTRL HDMI_CORE_AV_REG(0xBC) +#define HDMI_CORE_AV_AUDO_TXSTAT HDMI_CORE_AV_REG(0xC0) +#define HDMI_CORE_AV_AUD_PAR_BUSCLK_1 HDMI_CORE_AV_REG(0xCC) +#define HDMI_CORE_AV_AUD_PAR_BUSCLK_2 HDMI_CORE_AV_REG(0xD0) +#define HDMI_CORE_AV_AUD_PAR_BUSCLK_3 HDMI_CORE_AV_REG(0xD4) +#define HDMI_CORE_AV_TEST_TXCTRL HDMI_CORE_AV_REG(0xF0) +#define HDMI_CORE_AV_DPD HDMI_CORE_AV_REG(0xF4) +#define HDMI_CORE_AV_PB_CTRL1 HDMI_CORE_AV_REG(0xF8) +#define HDMI_CORE_AV_PB_CTRL2 HDMI_CORE_AV_REG(0xFC) +#define HDMI_CORE_AV_AVI_TYPE HDMI_CORE_AV_REG(0x100) +#define HDMI_CORE_AV_AVI_VERS HDMI_CORE_AV_REG(0x104) +#define HDMI_CORE_AV_AVI_LEN HDMI_CORE_AV_REG(0x108) +#define HDMI_CORE_AV_AVI_CHSUM HDMI_CORE_AV_REG(0x10C) +#define HDMI_CORE_AV_SPD_TYPE HDMI_CORE_AV_REG(0x180) +#define HDMI_CORE_AV_SPD_VERS HDMI_CORE_AV_REG(0x184) +#define HDMI_CORE_AV_SPD_LEN HDMI_CORE_AV_REG(0x188) +#define HDMI_CORE_AV_SPD_CHSUM HDMI_CORE_AV_REG(0x18C) +#define HDMI_CORE_AV_MPEG_TYPE HDMI_CORE_AV_REG(0x280) +#define HDMI_CORE_AV_MPEG_VERS HDMI_CORE_AV_REG(0x284) +#define HDMI_CORE_AV_MPEG_LEN HDMI_CORE_AV_REG(0x288) +#define HDMI_CORE_AV_MPEG_CHSUM HDMI_CORE_AV_REG(0x28C) +#define HDMI_CORE_AV_CP_BYTE1 HDMI_CORE_AV_REG(0x37C) +#define HDMI_CORE_AV_CEC_ADDR_ID HDMI_CORE_AV_REG(0x3FC) +#define HDMI_CORE_AV_SPD_DBYTE_ELSIZE 0x4 +#define HDMI_CORE_AV_GEN2_DBYTE_ELSIZE 0x4 +#define HDMI_CORE_AV_MPEG_DBYTE_ELSIZE 0x4 +#define HDMI_CORE_AV_GEN_DBYTE_ELSIZE 0x4 + +/* PLL */ +#define HDMI_PLL_REG(idx) HDMI_REG(HDMI_PLLCTRL + idx) + +#define PLLCTRL_PLL_CONTROL HDMI_PLL_REG(0x0) +#define PLLCTRL_PLL_STATUS HDMI_PLL_REG(0x4) +#define PLLCTRL_PLL_GO HDMI_PLL_REG(0x8) +#define PLLCTRL_CFG1 HDMI_PLL_REG(0xC) +#define PLLCTRL_CFG2 HDMI_PLL_REG(0x10) +#define PLLCTRL_CFG3 HDMI_PLL_REG(0x14) +#define PLLCTRL_CFG4 HDMI_PLL_REG(0x20) + +/* HDMI PHY */ +#define HDMI_PHY_REG(idx) HDMI_REG(HDMI_PHY + idx) + +#define HDMI_TXPHY_TX_CTRL HDMI_PHY_REG(0x0) +#define HDMI_TXPHY_DIGITAL_CTRL HDMI_PHY_REG(0x4) +#define HDMI_TXPHY_POWER_CTRL HDMI_PHY_REG(0x8) +#define HDMI_TXPHY_PAD_CFG_CTRL HDMI_PHY_REG(0xC) + +/* HDMI EDID Length */ +#define HDMI_EDID_MAX_LENGTH 256 +#define EDID_TIMING_DESCRIPTOR_SIZE 0x12 +#define EDID_DESCRIPTOR_BLOCK0_ADDRESS 0x36 +#define EDID_DESCRIPTOR_BLOCK1_ADDRESS 0x80 +#define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 4 +#define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 4 + +#define OMAP_HDMI_TIMINGS_NB 34 + +#define REG_FLD_MOD(idx, val, start, end) \ + hdmi_write_reg(idx, FLD_MOD(hdmi_read_reg(idx), val, start, end)) +#define REG_GET(idx, start, end) \ + FLD_GET(hdmi_read_reg(idx), start, end) + +/* HDMI timing structure */ +struct hdmi_timings { + struct omap_video_timings timings; + int vsync_pol; + int hsync_pol; +}; + +enum hdmi_phy_pwr { + HDMI_PHYPWRCMD_OFF = 0, + HDMI_PHYPWRCMD_LDOON = 1, + HDMI_PHYPWRCMD_TXON = 2 +}; + +enum hdmi_pll_pwr { + HDMI_PLLPWRCMD_ALLOFF = 0, + HDMI_PLLPWRCMD_PLLONLY = 1, + HDMI_PLLPWRCMD_BOTHON_ALLCLKS = 2, + HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3 +}; + +enum hdmi_clk_refsel { + HDMI_REFSEL_PCLK = 0, + HDMI_REFSEL_REF1 = 1, + HDMI_REFSEL_REF2 = 2, + HDMI_REFSEL_SYSCLK = 3 +}; + +enum hdmi_core_inputbus_width { + HDMI_INPUT_8BIT = 0, + HDMI_INPUT_10BIT = 1, + HDMI_INPUT_12BIT = 2 +}; + +enum hdmi_core_dither_trunc { + HDMI_OUTPUTTRUNCATION_8BIT = 0, + HDMI_OUTPUTTRUNCATION_10BIT = 1, + HDMI_OUTPUTTRUNCATION_12BIT = 2, + HDMI_OUTPUTDITHER_8BIT = 3, + HDMI_OUTPUTDITHER_10BIT = 4, + HDMI_OUTPUTDITHER_12BIT = 5 +}; + +enum hdmi_core_deepcolor_ed { + HDMI_DEEPCOLORPACKECTDISABLE = 0, + HDMI_DEEPCOLORPACKECTENABLE = 1 +}; + +enum hdmi_core_packet_mode { + HDMI_PACKETMODERESERVEDVALUE = 0, + HDMI_PACKETMODE24BITPERPIXEL = 4, + HDMI_PACKETMODE30BITPERPIXEL = 5, + HDMI_PACKETMODE36BITPERPIXEL = 6, + HDMI_PACKETMODE48BITPERPIXEL = 7 +}; + +enum hdmi_core_hdmi_dvi { + HDMI_DVI = 0, + HDMI_HDMI = 1 +}; + +enum hdmi_core_tclkselclkmult { + HDMI_FPLL05IDCK = 0, + HDMI_FPLL10IDCK = 1, + HDMI_FPLL20IDCK = 2, + HDMI_FPLL40IDCK = 3 +}; + +enum hdmi_core_packet_ctrl { + HDMI_PACKETENABLE = 1, + HDMI_PACKETDISABLE = 0, + HDMI_PACKETREPEATON = 1, + HDMI_PACKETREPEATOFF = 0 +}; + +/* INFOFRAME_AVI_ definitions */ +enum hdmi_core_infoframe { + HDMI_INFOFRAME_AVI_DB1Y_RGB = 0, + HDMI_INFOFRAME_AVI_DB1Y_YUV422 = 1, + HDMI_INFOFRAME_AVI_DB1Y_YUV444 = 2, + HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF = 0, + HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_ON = 1, + HDMI_INFOFRAME_AVI_DB1B_NO = 0, + HDMI_INFOFRAME_AVI_DB1B_VERT = 1, + HDMI_INFOFRAME_AVI_DB1B_HORI = 2, + HDMI_INFOFRAME_AVI_DB1B_VERTHORI = 3, + HDMI_INFOFRAME_AVI_DB1S_0 = 0, + HDMI_INFOFRAME_AVI_DB1S_1 = 1, + HDMI_INFOFRAME_AVI_DB1S_2 = 2, + HDMI_INFOFRAME_AVI_DB2C_NO = 0, + HDMI_INFOFRAME_AVI_DB2C_ITU601 = 1, + HDMI_INFOFRAME_AVI_DB2C_ITU709 = 2, + HDMI_INFOFRAME_AVI_DB2C_EC_EXTENDED = 3, + HDMI_INFOFRAME_AVI_DB2M_NO = 0, + HDMI_INFOFRAME_AVI_DB2M_43 = 1, + HDMI_INFOFRAME_AVI_DB2M_169 = 2, + HDMI_INFOFRAME_AVI_DB2R_SAME = 8, + HDMI_INFOFRAME_AVI_DB2R_43 = 9, + HDMI_INFOFRAME_AVI_DB2R_169 = 10, + HDMI_INFOFRAME_AVI_DB2R_149 = 11, + HDMI_INFOFRAME_AVI_DB3ITC_NO = 0, + HDMI_INFOFRAME_AVI_DB3ITC_YES = 1, + HDMI_INFOFRAME_AVI_DB3EC_XVYUV601 = 0, + HDMI_INFOFRAME_AVI_DB3EC_XVYUV709 = 1, + HDMI_INFOFRAME_AVI_DB3Q_DEFAULT = 0, + HDMI_INFOFRAME_AVI_DB3Q_LR = 1, + HDMI_INFOFRAME_AVI_DB3Q_FR = 2, + HDMI_INFOFRAME_AVI_DB3SC_NO = 0, + HDMI_INFOFRAME_AVI_DB3SC_HORI = 1, + HDMI_INFOFRAME_AVI_DB3SC_VERT = 2, + HDMI_INFOFRAME_AVI_DB3SC_HORIVERT = 3, + HDMI_INFOFRAME_AVI_DB5PR_NO = 0, + HDMI_INFOFRAME_AVI_DB5PR_2 = 1, + HDMI_INFOFRAME_AVI_DB5PR_3 = 2, + HDMI_INFOFRAME_AVI_DB5PR_4 = 3, + HDMI_INFOFRAME_AVI_DB5PR_5 = 4, + HDMI_INFOFRAME_AVI_DB5PR_6 = 5, + HDMI_INFOFRAME_AVI_DB5PR_7 = 6, + HDMI_INFOFRAME_AVI_DB5PR_8 = 7, + HDMI_INFOFRAME_AVI_DB5PR_9 = 8, + HDMI_INFOFRAME_AVI_DB5PR_10 = 9 +}; + +enum hdmi_packing_mode { + HDMI_PACK_10b_RGB_YUV444 = 0, + HDMI_PACK_24b_RGB_YUV444_YUV422 = 1, + HDMI_PACK_20b_YUV422 = 2, + HDMI_PACK_ALREADYPACKED = 7 +}; + +struct hdmi_core_video_config { + enum hdmi_core_inputbus_width ip_bus_width; + enum hdmi_core_dither_trunc op_dither_truc; + enum hdmi_core_deepcolor_ed deep_color_pkt; + enum hdmi_core_packet_mode pkt_mode; + enum hdmi_core_hdmi_dvi hdmi_dvi; + enum hdmi_core_tclkselclkmult tclk_sel_clkmult; +}; + +/* + * Refer to section 8.2 in HDMI 1.3 specification for + * details about infoframe databytes + */ +struct hdmi_core_infoframe_avi { + u8 db1_format; + /* Y0, Y1 rgb,yCbCr */ + u8 db1_active_info; + /* A0 Active information Present */ + u8 db1_bar_info_dv; + /* B0, B1 Bar info data valid */ + u8 db1_scan_info; + /* S0, S1 scan information */ + u8 db2_colorimetry; + /* C0, C1 colorimetry */ + u8 db2_aspect_ratio; + /* M0, M1 Aspect ratio (4:3, 16:9) */ + u8 db2_active_fmt_ar; + /* R0...R3 Active format aspect ratio */ + u8 db3_itc; + /* ITC IT content. */ + u8 db3_ec; + /* EC0, EC1, EC2 Extended colorimetry */ + u8 db3_q_range; + /* Q1, Q0 Quantization range */ + u8 db3_nup_scaling; + /* SC1, SC0 Non-uniform picture scaling */ + u8 db4_videocode; + /* VIC0..6 Video format identification */ + u8 db5_pixel_repeat; + /* PR0..PR3 Pixel repetition factor */ + u16 db6_7_line_eoftop; + /* Line number end of top bar */ + u16 db8_9_line_sofbottom; + /* Line number start of bottom bar */ + u16 db10_11_pixel_eofleft; + /* Pixel number end of left bar */ + u16 db12_13_pixel_sofright; + /* Pixel number start of right bar */ +}; + +struct hdmi_core_packet_enable_repeat { + u32 audio_pkt; + u32 audio_pkt_repeat; + u32 avi_infoframe; + u32 avi_infoframe_repeat; + u32 gen_cntrl_pkt; + u32 gen_cntrl_pkt_repeat; + u32 generic_pkt; + u32 generic_pkt_repeat; +}; + +struct hdmi_video_format { + enum hdmi_packing_mode packing_mode; + u32 y_res; /* Line per panel */ + u32 x_res; /* pixel per line */ +}; + +struct hdmi_video_interface { + int vsp; /* Vsync polarity */ + int hsp; /* Hsync polarity */ + int interlacing; + int tm; /* Timing mode */ +}; + +struct hdmi_cm { + int code; + int mode; +}; + +struct hdmi_config { + struct hdmi_timings timings; + u16 interlace; + struct hdmi_cm cm; +}; + +#endif From c3198a5e83121d6e3d01816f15164f158f4301d8 Mon Sep 17 00:00:00 2001 From: Mythri P K Date: Sat, 12 Mar 2011 12:04:27 +0530 Subject: [PATCH 074/140] OMAP4: DSS2: HDMI: HDMI driver addition in the DSS Adding the hdmi interface driver(hdmi.c) to the dss driver. It configures the audio and video portion of HDMI based on functionality called by the panel driver. Signed-off-by: Mythri P K Signed-off-by: Yong Zhi Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/display.c | 3 + drivers/video/omap2/dss/dss.h | 34 + drivers/video/omap2/dss/hdmi.c | 1332 +++++++++++++++++++++++++++++ 3 files changed, 1369 insertions(+) create mode 100644 drivers/video/omap2/dss/hdmi.c diff --git a/drivers/video/omap2/dss/display.c b/drivers/video/omap2/dss/display.c index c40bcbd2e140..a85a6f38b40c 100644 --- a/drivers/video/omap2/dss/display.c +++ b/drivers/video/omap2/dss/display.c @@ -418,6 +418,9 @@ void dss_init_device(struct platform_device *pdev, r = dsi_init_display(dssdev); break; #endif + case OMAP_DISPLAY_TYPE_HDMI: + r = hdmi_init_display(dssdev); + break; default: DSSERR("Support for display '%s' not compiled in.\n", dssdev->name); diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h index ab20270d761a..91ed3fa8e60d 100644 --- a/drivers/video/omap2/dss/dss.h +++ b/drivers/video/omap2/dss/dss.h @@ -173,6 +173,16 @@ struct dsi_clock_info { bool use_sys_clk; }; +/* HDMI PLL structure */ +struct hdmi_pll_info { + u16 regn; + u16 regm; + u32 regmf; + u16 regm2; + u16 regsd; + u16 dcofreq; +}; + struct seq_file; struct platform_device; @@ -444,6 +454,30 @@ static inline void venc_uninit_platform_driver(void) } #endif +/* HDMI */ +#ifdef CONFIG_OMAP4_DSS_HDMI +int hdmi_init_platform_driver(void); +void hdmi_uninit_platform_driver(void); +int hdmi_init_display(struct omap_dss_device *dssdev); +#else +static inline int hdmi_init_display(struct omap_dss_device *dssdev) +{ + return 0; +} +static inline int hdmi_init_platform_driver(void) +{ + return 0; +} +static inline void hdmi_uninit_platform_driver(void) +{ +} +#endif +int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev); +void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev); +void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev); +int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev, + struct omap_video_timings *timings); + /* RFBI */ #ifdef CONFIG_OMAP2_DSS_RFBI int rfbi_init_platform_driver(void); diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c new file mode 100644 index 000000000000..0d44f070ef36 --- /dev/null +++ b/drivers/video/omap2/dss/hdmi.c @@ -0,0 +1,1332 @@ +/* + * hdmi.c + * + * HDMI interface DSS driver setting for TI's OMAP4 family of processor. + * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/ + * Authors: Yong Zhi + * Mythri pk + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#define DSS_SUBSYS_NAME "HDMI" + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dss.h" +#include "hdmi.h" + +static struct { + struct mutex lock; + struct omap_display_platform_data *pdata; + struct platform_device *pdev; + void __iomem *base_wp; /* HDMI wrapper */ + int code; + int mode; + u8 edid[HDMI_EDID_MAX_LENGTH]; + u8 edid_set; + bool custom_set; + struct hdmi_config cfg; +} hdmi; + +/* + * Logic for the below structure : + * user enters the CEA or VESA timings by specifying the HDMI/DVI code. + * There is a correspondence between CEA/VESA timing and code, please + * refer to section 6.3 in HDMI 1.3 specification for timing code. + * + * In the below structure, cea_vesa_timings corresponds to all OMAP4 + * supported CEA and VESA timing values.code_cea corresponds to the CEA + * code, It is used to get the timing from cea_vesa_timing array.Similarly + * with code_vesa. Code_index is used for back mapping, that is once EDID + * is read from the TV, EDID is parsed to find the timing values and then + * map it to corresponding CEA or VESA index. + */ + +static const struct hdmi_timings cea_vesa_timings[OMAP_HDMI_TIMINGS_NB] = { + { {640, 480, 25200, 96, 16, 48, 2, 10, 33} , 0 , 0}, + { {1280, 720, 74250, 40, 440, 220, 5, 5, 20}, 1, 1}, + { {1280, 720, 74250, 40, 110, 220, 5, 5, 20}, 1, 1}, + { {720, 480, 27027, 62, 16, 60, 6, 9, 30}, 0, 0}, + { {2880, 576, 108000, 256, 48, 272, 5, 5, 39}, 0, 0}, + { {1440, 240, 27027, 124, 38, 114, 3, 4, 15}, 0, 0}, + { {1440, 288, 27000, 126, 24, 138, 3, 2, 19}, 0, 0}, + { {1920, 540, 74250, 44, 528, 148, 5, 2, 15}, 1, 1}, + { {1920, 540, 74250, 44, 88, 148, 5, 2, 15}, 1, 1}, + { {1920, 1080, 148500, 44, 88, 148, 5, 4, 36}, 1, 1}, + { {720, 576, 27000, 64, 12, 68, 5, 5, 39}, 0, 0}, + { {1440, 576, 54000, 128, 24, 136, 5, 5, 39}, 0, 0}, + { {1920, 1080, 148500, 44, 528, 148, 5, 4, 36}, 1, 1}, + { {2880, 480, 108108, 248, 64, 240, 6, 9, 30}, 0, 0}, + { {1920, 1080, 74250, 44, 638, 148, 5, 4, 36}, 1, 1}, + /* VESA From Here */ + { {640, 480, 25175, 96, 16, 48, 2 , 11, 31}, 0, 0}, + { {800, 600, 40000, 128, 40, 88, 4 , 1, 23}, 1, 1}, + { {848, 480, 33750, 112, 16, 112, 8 , 6, 23}, 1, 1}, + { {1280, 768, 79500, 128, 64, 192, 7 , 3, 20}, 1, 0}, + { {1280, 800, 83500, 128, 72, 200, 6 , 3, 22}, 1, 0}, + { {1360, 768, 85500, 112, 64, 256, 6 , 3, 18}, 1, 1}, + { {1280, 960, 108000, 112, 96, 312, 3 , 1, 36}, 1, 1}, + { {1280, 1024, 108000, 112, 48, 248, 3 , 1, 38}, 1, 1}, + { {1024, 768, 65000, 136, 24, 160, 6, 3, 29}, 0, 0}, + { {1400, 1050, 121750, 144, 88, 232, 4, 3, 32}, 1, 0}, + { {1440, 900, 106500, 152, 80, 232, 6, 3, 25}, 1, 0}, + { {1680, 1050, 146250, 176 , 104, 280, 6, 3, 30}, 1, 0}, + { {1366, 768, 85500, 143, 70, 213, 3, 3, 24}, 1, 1}, + { {1920, 1080, 148500, 44, 148, 80, 5, 4, 36}, 1, 1}, + { {1280, 768, 68250, 32, 48, 80, 7, 3, 12}, 0, 1}, + { {1400, 1050, 101000, 32, 48, 80, 4, 3, 23}, 0, 1}, + { {1680, 1050, 119000, 32, 48, 80, 6, 3, 21}, 0, 1}, + { {1280, 800, 79500, 32, 48, 80, 6, 3, 14}, 0, 1}, + { {1280, 720, 74250, 40, 110, 220, 5, 5, 20}, 1, 1} +}; + +/* + * This is a static mapping array which maps the timing values + * with corresponding CEA / VESA code + */ +static const int code_index[OMAP_HDMI_TIMINGS_NB] = { + 1, 19, 4, 2, 37, 6, 21, 20, 5, 16, 17, 29, 31, 35, 32, + /* <--15 CEA 17--> vesa*/ + 4, 9, 0xE, 0x17, 0x1C, 0x27, 0x20, 0x23, 0x10, 0x2A, + 0X2F, 0x3A, 0X51, 0X52, 0x16, 0x29, 0x39, 0x1B +}; + +/* + * This is reverse static mapping which maps the CEA / VESA code + * to the corresponding timing values + */ +static const int code_cea[39] = { + -1, 0, 3, 3, 2, 8, 5, 5, -1, -1, + -1, -1, -1, -1, -1, -1, 9, 10, 10, 1, + 7, 6, 6, -1, -1, -1, -1, -1, -1, 11, + 11, 12, 14, -1, -1, 13, 13, 4, 4 +}; + +static const int code_vesa[85] = { + -1, -1, -1, -1, 15, -1, -1, -1, -1, 16, + -1, -1, -1, -1, 17, -1, 23, -1, -1, -1, + -1, -1, 29, 18, -1, -1, -1, 32, 19, -1, + -1, -1, 21, -1, -1, 22, -1, -1, -1, 20, + -1, 30, 24, -1, -1, -1, -1, 25, -1, -1, + -1, -1, -1, -1, -1, -1, -1, 31, 26, -1, + -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, + -1, 27, 28, -1, 33}; + +static const u8 edid_header[8] = {0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0}; + +static inline void hdmi_write_reg(const struct hdmi_reg idx, u32 val) +{ + __raw_writel(val, hdmi.base_wp + idx.idx); +} + +static inline u32 hdmi_read_reg(const struct hdmi_reg idx) +{ + return __raw_readl(hdmi.base_wp + idx.idx); +} + +static inline int hdmi_wait_for_bit_change(const struct hdmi_reg idx, + int b2, int b1, u32 val) +{ + u32 t = 0; + while (val != REG_GET(idx, b2, b1)) { + udelay(1); + if (t++ > 10000) + return !val; + } + return val; +} + +int hdmi_init_display(struct omap_dss_device *dssdev) +{ + DSSDBG("init_display\n"); + + return 0; +} + +static int hdmi_pll_init(enum hdmi_clk_refsel refsel, int dcofreq, + struct hdmi_pll_info *fmt, u16 sd) +{ + u32 r; + + /* PLL start always use manual mode */ + REG_FLD_MOD(PLLCTRL_PLL_CONTROL, 0x0, 0, 0); + + r = hdmi_read_reg(PLLCTRL_CFG1); + r = FLD_MOD(r, fmt->regm, 20, 9); /* CFG1_PLL_REGM */ + r = FLD_MOD(r, fmt->regn, 8, 1); /* CFG1_PLL_REGN */ + + hdmi_write_reg(PLLCTRL_CFG1, r); + + r = hdmi_read_reg(PLLCTRL_CFG2); + + r = FLD_MOD(r, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */ + r = FLD_MOD(r, 0x1, 13, 13); /* PLL_REFEN */ + r = FLD_MOD(r, 0x0, 14, 14); /* PHY_CLKINEN de-assert during locking */ + + if (dcofreq) { + /* divider programming for frequency beyond 1000Mhz */ + REG_FLD_MOD(PLLCTRL_CFG3, sd, 17, 10); + r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */ + } else { + r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */ + } + + hdmi_write_reg(PLLCTRL_CFG2, r); + + r = hdmi_read_reg(PLLCTRL_CFG4); + r = FLD_MOD(r, fmt->regm2, 24, 18); + r = FLD_MOD(r, fmt->regmf, 17, 0); + + hdmi_write_reg(PLLCTRL_CFG4, r); + + /* go now */ + REG_FLD_MOD(PLLCTRL_PLL_GO, 0x1, 0, 0); + + /* wait for bit change */ + if (hdmi_wait_for_bit_change(PLLCTRL_PLL_GO, 0, 0, 1) != 1) { + DSSERR("PLL GO bit not set\n"); + return -ETIMEDOUT; + } + + /* Wait till the lock bit is set in PLL status */ + if (hdmi_wait_for_bit_change(PLLCTRL_PLL_STATUS, 1, 1, 1) != 1) { + DSSWARN("cannot lock PLL\n"); + DSSWARN("CFG1 0x%x\n", + hdmi_read_reg(PLLCTRL_CFG1)); + DSSWARN("CFG2 0x%x\n", + hdmi_read_reg(PLLCTRL_CFG2)); + DSSWARN("CFG4 0x%x\n", + hdmi_read_reg(PLLCTRL_CFG4)); + return -ETIMEDOUT; + } + + DSSDBG("PLL locked!\n"); + + return 0; +} + +/* PHY_PWR_CMD */ +static int hdmi_set_phy_pwr(enum hdmi_phy_pwr val) +{ + /* Command for power control of HDMI PHY */ + REG_FLD_MOD(HDMI_WP_PWR_CTRL, val, 7, 6); + + /* Status of the power control of HDMI PHY */ + if (hdmi_wait_for_bit_change(HDMI_WP_PWR_CTRL, 5, 4, val) != val) { + DSSERR("Failed to set PHY power mode to %d\n", val); + return -ETIMEDOUT; + } + + return 0; +} + +/* PLL_PWR_CMD */ +static int hdmi_set_pll_pwr(enum hdmi_pll_pwr val) +{ + /* Command for power control of HDMI PLL */ + REG_FLD_MOD(HDMI_WP_PWR_CTRL, val, 3, 2); + + /* wait till PHY_PWR_STATUS is set */ + if (hdmi_wait_for_bit_change(HDMI_WP_PWR_CTRL, 1, 0, val) != val) { + DSSERR("Failed to set PHY_PWR_STATUS\n"); + return -ETIMEDOUT; + } + + return 0; +} + +static int hdmi_pll_reset(void) +{ + /* SYSRESET controlled by power FSM */ + REG_FLD_MOD(PLLCTRL_PLL_CONTROL, 0x0, 3, 3); + + /* READ 0x0 reset is in progress */ + if (hdmi_wait_for_bit_change(PLLCTRL_PLL_STATUS, 0, 0, 1) != 1) { + DSSERR("Failed to sysreset PLL\n"); + return -ETIMEDOUT; + } + + return 0; +} + +static int hdmi_phy_init(void) +{ + u16 r = 0; + + r = hdmi_set_phy_pwr(HDMI_PHYPWRCMD_LDOON); + if (r) + return r; + + r = hdmi_set_phy_pwr(HDMI_PHYPWRCMD_TXON); + if (r) + return r; + + /* + * Read address 0 in order to get the SCP reset done completed + * Dummy access performed to make sure reset is done + */ + hdmi_read_reg(HDMI_TXPHY_TX_CTRL); + + /* + * Write to phy address 0 to configure the clock + * use HFBITCLK write HDMI_TXPHY_TX_CONTROL_FREQOUT field + */ + REG_FLD_MOD(HDMI_TXPHY_TX_CTRL, 0x1, 31, 30); + + /* Write to phy address 1 to start HDMI line (TXVALID and TMDSCLKEN) */ + hdmi_write_reg(HDMI_TXPHY_DIGITAL_CTRL, 0xF0000000); + + /* Setup max LDO voltage */ + REG_FLD_MOD(HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0); + + /* Write to phy address 3 to change the polarity control */ + REG_FLD_MOD(HDMI_TXPHY_PAD_CFG_CTRL, 0x1, 27, 27); + + return 0; +} + +static int hdmi_wait_softreset(void) +{ + /* reset W1 */ + REG_FLD_MOD(HDMI_WP_SYSCONFIG, 0x1, 0, 0); + + /* wait till SOFTRESET == 0 */ + if (hdmi_wait_for_bit_change(HDMI_WP_SYSCONFIG, 0, 0, 0) != 0) { + DSSERR("sysconfig reset failed\n"); + return -ETIMEDOUT; + } + + return 0; +} + +static int hdmi_pll_program(struct hdmi_pll_info *fmt) +{ + u16 r = 0; + enum hdmi_clk_refsel refsel; + + /* wait for wrapper reset */ + r = hdmi_wait_softreset(); + if (r) + return r; + + r = hdmi_set_pll_pwr(HDMI_PLLPWRCMD_ALLOFF); + if (r) + return r; + + r = hdmi_set_pll_pwr(HDMI_PLLPWRCMD_BOTHON_ALLCLKS); + if (r) + return r; + + r = hdmi_pll_reset(); + if (r) + return r; + + refsel = HDMI_REFSEL_SYSCLK; + + r = hdmi_pll_init(refsel, fmt->dcofreq, fmt, fmt->regsd); + if (r) + return r; + + return 0; +} + +static void hdmi_phy_off(void) +{ + hdmi_set_phy_pwr(HDMI_PHYPWRCMD_OFF); +} + +static int hdmi_core_ddc_edid(u8 *pedid, int ext) +{ + u32 i, j; + char checksum = 0; + u32 offset = 0; + + /* Turn on CLK for DDC */ + REG_FLD_MOD(HDMI_CORE_AV_DPD, 0x7, 2, 0); + + /* + * SW HACK : Without the Delay DDC(i2c bus) reads 0 values / + * right shifted values( The behavior is not consistent and seen only + * with some TV's) + */ + usleep_range(800, 1000); + + if (!ext) { + /* Clk SCL Devices */ + REG_FLD_MOD(HDMI_CORE_DDC_CMD, 0xA, 3, 0); + + /* HDMI_CORE_DDC_STATUS_IN_PROG */ + if (hdmi_wait_for_bit_change(HDMI_CORE_DDC_STATUS, + 4, 4, 0) != 0) { + DSSERR("Failed to program DDC\n"); + return -ETIMEDOUT; + } + + /* Clear FIFO */ + REG_FLD_MOD(HDMI_CORE_DDC_CMD, 0x9, 3, 0); + + /* HDMI_CORE_DDC_STATUS_IN_PROG */ + if (hdmi_wait_for_bit_change(HDMI_CORE_DDC_STATUS, + 4, 4, 0) != 0) { + DSSERR("Failed to program DDC\n"); + return -ETIMEDOUT; + } + + } else { + if (ext % 2 != 0) + offset = 0x80; + } + + /* Load Segment Address Register */ + REG_FLD_MOD(HDMI_CORE_DDC_SEGM, ext/2, 7, 0); + + /* Load Slave Address Register */ + REG_FLD_MOD(HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1); + + /* Load Offset Address Register */ + REG_FLD_MOD(HDMI_CORE_DDC_OFFSET, offset, 7, 0); + + /* Load Byte Count */ + REG_FLD_MOD(HDMI_CORE_DDC_COUNT1, 0x80, 7, 0); + REG_FLD_MOD(HDMI_CORE_DDC_COUNT2, 0x0, 1, 0); + + /* Set DDC_CMD */ + if (ext) + REG_FLD_MOD(HDMI_CORE_DDC_CMD, 0x4, 3, 0); + else + REG_FLD_MOD(HDMI_CORE_DDC_CMD, 0x2, 3, 0); + + /* HDMI_CORE_DDC_STATUS_BUS_LOW */ + if (REG_GET(HDMI_CORE_DDC_STATUS, 6, 6) == 1) { + DSSWARN("I2C Bus Low?\n"); + return -EIO; + } + /* HDMI_CORE_DDC_STATUS_NO_ACK */ + if (REG_GET(HDMI_CORE_DDC_STATUS, 5, 5) == 1) { + DSSWARN("I2C No Ack\n"); + return -EIO; + } + + i = ext * 128; + j = 0; + while (((REG_GET(HDMI_CORE_DDC_STATUS, 4, 4) == 1) || + (REG_GET(HDMI_CORE_DDC_STATUS, 2, 2) == 0)) && + j < 128) { + + if (REG_GET(HDMI_CORE_DDC_STATUS, 2, 2) == 0) { + /* FIFO not empty */ + pedid[i++] = REG_GET(HDMI_CORE_DDC_DATA, 7, 0); + j++; + } + } + + for (j = 0; j < 128; j++) + checksum += pedid[j]; + + if (checksum != 0) { + DSSERR("E-EDID checksum failed!!\n"); + return -EIO; + } + + return 0; +} + +static int read_edid(u8 *pedid, u16 max_length) +{ + int r = 0, n = 0, i = 0; + int max_ext_blocks = (max_length / 128) - 1; + + r = hdmi_core_ddc_edid(pedid, 0); + if (r) { + return r; + } else { + n = pedid[0x7e]; + + /* + * README: need to comply with max_length set by the caller. + * Better implementation should be to allocate necessary + * memory to store EDID according to nb_block field found + * in first block + */ + if (n > max_ext_blocks) + n = max_ext_blocks; + + for (i = 1; i <= n; i++) { + r = hdmi_core_ddc_edid(pedid, i); + if (r) + return r; + } + } + return 0; +} + +static int get_timings_index(void) +{ + int code; + + if (hdmi.mode == 0) + code = code_vesa[hdmi.code]; + else + code = code_cea[hdmi.code]; + + if (code == -1) { + /* HDMI code 4 corresponds to 640 * 480 VGA */ + hdmi.code = 4; + /* DVI mode 1 corresponds to HDMI 0 to DVI */ + hdmi.mode = HDMI_DVI; + + code = code_vesa[hdmi.code]; + } + return code; +} + +static struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing) +{ + int i = 0, code = -1, temp_vsync = 0, temp_hsync = 0; + int timing_vsync = 0, timing_hsync = 0; + struct omap_video_timings temp; + struct hdmi_cm cm = {-1}; + DSSDBG("hdmi_get_code\n"); + + for (i = 0; i < OMAP_HDMI_TIMINGS_NB; i++) { + temp = cea_vesa_timings[i].timings; + if ((temp.pixel_clock == timing->pixel_clock) && + (temp.x_res == timing->x_res) && + (temp.y_res == timing->y_res)) { + + temp_hsync = temp.hfp + temp.hsw + temp.hbp; + timing_hsync = timing->hfp + timing->hsw + timing->hbp; + temp_vsync = temp.vfp + temp.vsw + temp.vbp; + timing_vsync = timing->vfp + timing->vsw + timing->vbp; + + DSSDBG("temp_hsync = %d , temp_vsync = %d" + "timing_hsync = %d, timing_vsync = %d\n", + temp_hsync, temp_hsync, + timing_hsync, timing_vsync); + + if ((temp_hsync == timing_hsync) && + (temp_vsync == timing_vsync)) { + code = i; + cm.code = code_index[i]; + if (code < 14) + cm.mode = HDMI_HDMI; + else + cm.mode = HDMI_DVI; + DSSDBG("Hdmi_code = %d mode = %d\n", + cm.code, cm.mode); + break; + } + } + } + + return cm; +} + +static void get_horz_vert_timing_info(int current_descriptor_addrs, u8 *edid , + struct omap_video_timings *timings) +{ + /* X and Y resolution */ + timings->x_res = (((edid[current_descriptor_addrs + 4] & 0xF0) << 4) | + edid[current_descriptor_addrs + 2]); + timings->y_res = (((edid[current_descriptor_addrs + 7] & 0xF0) << 4) | + edid[current_descriptor_addrs + 5]); + + timings->pixel_clock = ((edid[current_descriptor_addrs + 1] << 8) | + edid[current_descriptor_addrs]); + + timings->pixel_clock = 10 * timings->pixel_clock; + + /* HORIZONTAL FRONT PORCH */ + timings->hfp = edid[current_descriptor_addrs + 8] | + ((edid[current_descriptor_addrs + 11] & 0xc0) << 2); + /* HORIZONTAL SYNC WIDTH */ + timings->hsw = edid[current_descriptor_addrs + 9] | + ((edid[current_descriptor_addrs + 11] & 0x30) << 4); + /* HORIZONTAL BACK PORCH */ + timings->hbp = (((edid[current_descriptor_addrs + 4] & 0x0F) << 8) | + edid[current_descriptor_addrs + 3]) - + (timings->hfp + timings->hsw); + /* VERTICAL FRONT PORCH */ + timings->vfp = ((edid[current_descriptor_addrs + 10] & 0xF0) >> 4) | + ((edid[current_descriptor_addrs + 11] & 0x0f) << 2); + /* VERTICAL SYNC WIDTH */ + timings->vsw = (edid[current_descriptor_addrs + 10] & 0x0F) | + ((edid[current_descriptor_addrs + 11] & 0x03) << 4); + /* VERTICAL BACK PORCH */ + timings->vbp = (((edid[current_descriptor_addrs + 7] & 0x0F) << 8) | + edid[current_descriptor_addrs + 6]) - + (timings->vfp + timings->vsw); + +} + +/* Description : This function gets the resolution information from EDID */ +static void get_edid_timing_data(u8 *edid) +{ + u8 count; + u16 current_descriptor_addrs; + struct hdmi_cm cm; + struct omap_video_timings edid_timings; + + /* seach block 0, there are 4 DTDs arranged in priority order */ + for (count = 0; count < EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR; count++) { + current_descriptor_addrs = + EDID_DESCRIPTOR_BLOCK0_ADDRESS + + count * EDID_TIMING_DESCRIPTOR_SIZE; + get_horz_vert_timing_info(current_descriptor_addrs, + edid, &edid_timings); + cm = hdmi_get_code(&edid_timings); + DSSDBG("Block0[%d] value matches code = %d , mode = %d\n", + count, cm.code, cm.mode); + if (cm.code == -1) { + continue; + } else { + hdmi.code = cm.code; + hdmi.mode = cm.mode; + DSSDBG("code = %d , mode = %d\n", + hdmi.code, hdmi.mode); + return; + } + } + if (edid[0x7e] != 0x00) { + for (count = 0; count < EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR; + count++) { + current_descriptor_addrs = + EDID_DESCRIPTOR_BLOCK1_ADDRESS + + count * EDID_TIMING_DESCRIPTOR_SIZE; + get_horz_vert_timing_info(current_descriptor_addrs, + edid, &edid_timings); + cm = hdmi_get_code(&edid_timings); + DSSDBG("Block1[%d] value matches code = %d, mode = %d", + count, cm.code, cm.mode); + if (cm.code == -1) { + continue; + } else { + hdmi.code = cm.code; + hdmi.mode = cm.mode; + DSSDBG("code = %d , mode = %d\n", + hdmi.code, hdmi.mode); + return; + } + } + } + + DSSINFO("no valid timing found , falling back to VGA\n"); + hdmi.code = 4; /* setting default value of 640 480 VGA */ + hdmi.mode = HDMI_DVI; +} + +static void hdmi_read_edid(struct omap_video_timings *dp) +{ + int ret = 0, code; + + memset(hdmi.edid, 0, HDMI_EDID_MAX_LENGTH); + + if (!hdmi.edid_set) + ret = read_edid(hdmi.edid, HDMI_EDID_MAX_LENGTH); + + if (!ret) { + if (!memcmp(hdmi.edid, edid_header, sizeof(edid_header))) { + /* search for timings of default resolution */ + get_edid_timing_data(hdmi.edid); + hdmi.edid_set = true; + } + } else { + DSSWARN("failed to read E-EDID\n"); + } + + if (!hdmi.edid_set) { + DSSINFO("fallback to VGA\n"); + hdmi.code = 4; /* setting default value of 640 480 VGA */ + hdmi.mode = HDMI_DVI; + } + + code = get_timings_index(); + + *dp = cea_vesa_timings[code].timings; +} + +static void hdmi_core_init(struct hdmi_core_video_config *video_cfg, + struct hdmi_core_infoframe_avi *avi_cfg, + struct hdmi_core_packet_enable_repeat *repeat_cfg) +{ + DSSDBG("Enter hdmi_core_init\n"); + + /* video core */ + video_cfg->ip_bus_width = HDMI_INPUT_8BIT; + video_cfg->op_dither_truc = HDMI_OUTPUTTRUNCATION_8BIT; + video_cfg->deep_color_pkt = HDMI_DEEPCOLORPACKECTDISABLE; + video_cfg->pkt_mode = HDMI_PACKETMODERESERVEDVALUE; + video_cfg->hdmi_dvi = HDMI_DVI; + video_cfg->tclk_sel_clkmult = HDMI_FPLL10IDCK; + + /* info frame */ + avi_cfg->db1_format = 0; + avi_cfg->db1_active_info = 0; + avi_cfg->db1_bar_info_dv = 0; + avi_cfg->db1_scan_info = 0; + avi_cfg->db2_colorimetry = 0; + avi_cfg->db2_aspect_ratio = 0; + avi_cfg->db2_active_fmt_ar = 0; + avi_cfg->db3_itc = 0; + avi_cfg->db3_ec = 0; + avi_cfg->db3_q_range = 0; + avi_cfg->db3_nup_scaling = 0; + avi_cfg->db4_videocode = 0; + avi_cfg->db5_pixel_repeat = 0; + avi_cfg->db6_7_line_eoftop = 0 ; + avi_cfg->db8_9_line_sofbottom = 0; + avi_cfg->db10_11_pixel_eofleft = 0; + avi_cfg->db12_13_pixel_sofright = 0; + + /* packet enable and repeat */ + repeat_cfg->audio_pkt = 0; + repeat_cfg->audio_pkt_repeat = 0; + repeat_cfg->avi_infoframe = 0; + repeat_cfg->avi_infoframe_repeat = 0; + repeat_cfg->gen_cntrl_pkt = 0; + repeat_cfg->gen_cntrl_pkt_repeat = 0; + repeat_cfg->generic_pkt = 0; + repeat_cfg->generic_pkt_repeat = 0; +} + +static void hdmi_core_powerdown_disable(void) +{ + DSSDBG("Enter hdmi_core_powerdown_disable\n"); + REG_FLD_MOD(HDMI_CORE_CTRL1, 0x0, 0, 0); +} + +static void hdmi_core_swreset_release(void) +{ + DSSDBG("Enter hdmi_core_swreset_release\n"); + REG_FLD_MOD(HDMI_CORE_SYS_SRST, 0x0, 0, 0); +} + +static void hdmi_core_swreset_assert(void) +{ + DSSDBG("Enter hdmi_core_swreset_assert\n"); + REG_FLD_MOD(HDMI_CORE_SYS_SRST, 0x1, 0, 0); +} + +/* DSS_HDMI_CORE_VIDEO_CONFIG */ +static void hdmi_core_video_config(struct hdmi_core_video_config *cfg) +{ + u32 r = 0; + + /* sys_ctrl1 default configuration not tunable */ + r = hdmi_read_reg(HDMI_CORE_CTRL1); + r = FLD_MOD(r, HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC, 5, 5); + r = FLD_MOD(r, HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC, 4, 4); + r = FLD_MOD(r, HDMI_CORE_CTRL1_BSEL_24BITBUS, 2, 2); + r = FLD_MOD(r, HDMI_CORE_CTRL1_EDGE_RISINGEDGE, 1, 1); + hdmi_write_reg(HDMI_CORE_CTRL1, r); + + REG_FLD_MOD(HDMI_CORE_SYS_VID_ACEN, cfg->ip_bus_width, 7, 6); + + /* Vid_Mode */ + r = hdmi_read_reg(HDMI_CORE_SYS_VID_MODE); + + /* dither truncation configuration */ + if (cfg->op_dither_truc > HDMI_OUTPUTTRUNCATION_12BIT) { + r = FLD_MOD(r, cfg->op_dither_truc - 3, 7, 6); + r = FLD_MOD(r, 1, 5, 5); + } else { + r = FLD_MOD(r, cfg->op_dither_truc, 7, 6); + r = FLD_MOD(r, 0, 5, 5); + } + hdmi_write_reg(HDMI_CORE_SYS_VID_MODE, r); + + /* HDMI_Ctrl */ + r = hdmi_read_reg(HDMI_CORE_AV_HDMI_CTRL); + r = FLD_MOD(r, cfg->deep_color_pkt, 6, 6); + r = FLD_MOD(r, cfg->pkt_mode, 5, 3); + r = FLD_MOD(r, cfg->hdmi_dvi, 0, 0); + hdmi_write_reg(HDMI_CORE_AV_HDMI_CTRL, r); + + /* TMDS_CTRL */ + REG_FLD_MOD(HDMI_CORE_SYS_TMDS_CTRL, + cfg->tclk_sel_clkmult, 6, 5); +} + +static void hdmi_core_aux_infoframe_avi_config( + struct hdmi_core_infoframe_avi info_avi) +{ + u32 val; + char sum = 0, checksum = 0; + + sum += 0x82 + 0x002 + 0x00D; + hdmi_write_reg(HDMI_CORE_AV_AVI_TYPE, 0x082); + hdmi_write_reg(HDMI_CORE_AV_AVI_VERS, 0x002); + hdmi_write_reg(HDMI_CORE_AV_AVI_LEN, 0x00D); + + val = (info_avi.db1_format << 5) | + (info_avi.db1_active_info << 4) | + (info_avi.db1_bar_info_dv << 2) | + (info_avi.db1_scan_info); + hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(0), val); + sum += val; + + val = (info_avi.db2_colorimetry << 6) | + (info_avi.db2_aspect_ratio << 4) | + (info_avi.db2_active_fmt_ar); + hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(1), val); + sum += val; + + val = (info_avi.db3_itc << 7) | + (info_avi.db3_ec << 4) | + (info_avi.db3_q_range << 2) | + (info_avi.db3_nup_scaling); + hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(2), val); + sum += val; + + hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(3), info_avi.db4_videocode); + sum += info_avi.db4_videocode; + + val = info_avi.db5_pixel_repeat; + hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(4), val); + sum += val; + + val = info_avi.db6_7_line_eoftop & 0x00FF; + hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(5), val); + sum += val; + + val = ((info_avi.db6_7_line_eoftop >> 8) & 0x00FF); + hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(6), val); + sum += val; + + val = info_avi.db8_9_line_sofbottom & 0x00FF; + hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(7), val); + sum += val; + + val = ((info_avi.db8_9_line_sofbottom >> 8) & 0x00FF); + hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(8), val); + sum += val; + + val = info_avi.db10_11_pixel_eofleft & 0x00FF; + hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(9), val); + sum += val; + + val = ((info_avi.db10_11_pixel_eofleft >> 8) & 0x00FF); + hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(10), val); + sum += val; + + val = info_avi.db12_13_pixel_sofright & 0x00FF; + hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(11), val); + sum += val; + + val = ((info_avi.db12_13_pixel_sofright >> 8) & 0x00FF); + hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(12), val); + sum += val; + + checksum = 0x100 - sum; + hdmi_write_reg(HDMI_CORE_AV_AVI_CHSUM, checksum); +} + +static void hdmi_core_av_packet_config( + struct hdmi_core_packet_enable_repeat repeat_cfg) +{ + /* enable/repeat the infoframe */ + hdmi_write_reg(HDMI_CORE_AV_PB_CTRL1, + (repeat_cfg.audio_pkt << 5) | + (repeat_cfg.audio_pkt_repeat << 4) | + (repeat_cfg.avi_infoframe << 1) | + (repeat_cfg.avi_infoframe_repeat)); + + /* enable/repeat the packet */ + hdmi_write_reg(HDMI_CORE_AV_PB_CTRL2, + (repeat_cfg.gen_cntrl_pkt << 3) | + (repeat_cfg.gen_cntrl_pkt_repeat << 2) | + (repeat_cfg.generic_pkt << 1) | + (repeat_cfg.generic_pkt_repeat)); +} + +static void hdmi_wp_init(struct omap_video_timings *timings, + struct hdmi_video_format *video_fmt, + struct hdmi_video_interface *video_int) +{ + DSSDBG("Enter hdmi_wp_init\n"); + + timings->hbp = 0; + timings->hfp = 0; + timings->hsw = 0; + timings->vbp = 0; + timings->vfp = 0; + timings->vsw = 0; + + video_fmt->packing_mode = HDMI_PACK_10b_RGB_YUV444; + video_fmt->y_res = 0; + video_fmt->x_res = 0; + + video_int->vsp = 0; + video_int->hsp = 0; + + video_int->interlacing = 0; + video_int->tm = 0; /* HDMI_TIMING_SLAVE */ + +} + +static void hdmi_wp_video_start(bool start) +{ + REG_FLD_MOD(HDMI_WP_VIDEO_CFG, start, 31, 31); +} + +static void hdmi_wp_video_init_format(struct hdmi_video_format *video_fmt, + struct omap_video_timings *timings, struct hdmi_config *param) +{ + DSSDBG("Enter hdmi_wp_video_init_format\n"); + + video_fmt->y_res = param->timings.timings.y_res; + video_fmt->x_res = param->timings.timings.x_res; + + timings->hbp = param->timings.timings.hbp; + timings->hfp = param->timings.timings.hfp; + timings->hsw = param->timings.timings.hsw; + timings->vbp = param->timings.timings.vbp; + timings->vfp = param->timings.timings.vfp; + timings->vsw = param->timings.timings.vsw; +} + +static void hdmi_wp_video_config_format( + struct hdmi_video_format *video_fmt) +{ + u32 l = 0; + + REG_FLD_MOD(HDMI_WP_VIDEO_CFG, video_fmt->packing_mode, 10, 8); + + l |= FLD_VAL(video_fmt->y_res, 31, 16); + l |= FLD_VAL(video_fmt->x_res, 15, 0); + hdmi_write_reg(HDMI_WP_VIDEO_SIZE, l); +} + +static void hdmi_wp_video_config_interface( + struct hdmi_video_interface *video_int) +{ + u32 r; + DSSDBG("Enter hdmi_wp_video_config_interface\n"); + + r = hdmi_read_reg(HDMI_WP_VIDEO_CFG); + r = FLD_MOD(r, video_int->vsp, 7, 7); + r = FLD_MOD(r, video_int->hsp, 6, 6); + r = FLD_MOD(r, video_int->interlacing, 3, 3); + r = FLD_MOD(r, video_int->tm, 1, 0); + hdmi_write_reg(HDMI_WP_VIDEO_CFG, r); +} + +static void hdmi_wp_video_config_timing( + struct omap_video_timings *timings) +{ + u32 timing_h = 0; + u32 timing_v = 0; + + DSSDBG("Enter hdmi_wp_video_config_timing\n"); + + timing_h |= FLD_VAL(timings->hbp, 31, 20); + timing_h |= FLD_VAL(timings->hfp, 19, 8); + timing_h |= FLD_VAL(timings->hsw, 7, 0); + hdmi_write_reg(HDMI_WP_VIDEO_TIMING_H, timing_h); + + timing_v |= FLD_VAL(timings->vbp, 31, 20); + timing_v |= FLD_VAL(timings->vfp, 19, 8); + timing_v |= FLD_VAL(timings->vsw, 7, 0); + hdmi_write_reg(HDMI_WP_VIDEO_TIMING_V, timing_v); +} + +static void hdmi_basic_configure(struct hdmi_config *cfg) +{ + /* HDMI */ + struct omap_video_timings video_timing; + struct hdmi_video_format video_format; + struct hdmi_video_interface video_interface; + /* HDMI core */ + struct hdmi_core_infoframe_avi avi_cfg; + struct hdmi_core_video_config v_core_cfg; + struct hdmi_core_packet_enable_repeat repeat_cfg; + + hdmi_wp_init(&video_timing, &video_format, + &video_interface); + + hdmi_core_init(&v_core_cfg, + &avi_cfg, + &repeat_cfg); + + hdmi_wp_video_init_format(&video_format, + &video_timing, cfg); + + hdmi_wp_video_config_timing(&video_timing); + + /* video config */ + video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422; + + hdmi_wp_video_config_format(&video_format); + + video_interface.vsp = cfg->timings.vsync_pol; + video_interface.hsp = cfg->timings.hsync_pol; + video_interface.interlacing = cfg->interlace; + video_interface.tm = 1 ; /* HDMI_TIMING_MASTER_24BIT */ + + hdmi_wp_video_config_interface(&video_interface); + + /* + * configure core video part + * set software reset in the core + */ + hdmi_core_swreset_assert(); + + /* power down off */ + hdmi_core_powerdown_disable(); + + v_core_cfg.pkt_mode = HDMI_PACKETMODE24BITPERPIXEL; + v_core_cfg.hdmi_dvi = cfg->cm.mode; + + hdmi_core_video_config(&v_core_cfg); + + /* release software reset in the core */ + hdmi_core_swreset_release(); + + /* + * configure packet + * info frame video see doc CEA861-D page 65 + */ + avi_cfg.db1_format = HDMI_INFOFRAME_AVI_DB1Y_RGB; + avi_cfg.db1_active_info = + HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF; + avi_cfg.db1_bar_info_dv = HDMI_INFOFRAME_AVI_DB1B_NO; + avi_cfg.db1_scan_info = HDMI_INFOFRAME_AVI_DB1S_0; + avi_cfg.db2_colorimetry = HDMI_INFOFRAME_AVI_DB2C_NO; + avi_cfg.db2_aspect_ratio = HDMI_INFOFRAME_AVI_DB2M_NO; + avi_cfg.db2_active_fmt_ar = HDMI_INFOFRAME_AVI_DB2R_SAME; + avi_cfg.db3_itc = HDMI_INFOFRAME_AVI_DB3ITC_NO; + avi_cfg.db3_ec = HDMI_INFOFRAME_AVI_DB3EC_XVYUV601; + avi_cfg.db3_q_range = HDMI_INFOFRAME_AVI_DB3Q_DEFAULT; + avi_cfg.db3_nup_scaling = HDMI_INFOFRAME_AVI_DB3SC_NO; + avi_cfg.db4_videocode = cfg->cm.code; + avi_cfg.db5_pixel_repeat = HDMI_INFOFRAME_AVI_DB5PR_NO; + avi_cfg.db6_7_line_eoftop = 0; + avi_cfg.db8_9_line_sofbottom = 0; + avi_cfg.db10_11_pixel_eofleft = 0; + avi_cfg.db12_13_pixel_sofright = 0; + + hdmi_core_aux_infoframe_avi_config(avi_cfg); + + /* enable/repeat the infoframe */ + repeat_cfg.avi_infoframe = HDMI_PACKETENABLE; + repeat_cfg.avi_infoframe_repeat = HDMI_PACKETREPEATON; + /* wakeup */ + repeat_cfg.audio_pkt = HDMI_PACKETENABLE; + repeat_cfg.audio_pkt_repeat = HDMI_PACKETREPEATON; + hdmi_core_av_packet_config(repeat_cfg); +} + +static void update_hdmi_timings(struct hdmi_config *cfg, + struct omap_video_timings *timings, int code) +{ + cfg->timings.timings.x_res = timings->x_res; + cfg->timings.timings.y_res = timings->y_res; + cfg->timings.timings.hbp = timings->hbp; + cfg->timings.timings.hfp = timings->hfp; + cfg->timings.timings.hsw = timings->hsw; + cfg->timings.timings.vbp = timings->vbp; + cfg->timings.timings.vfp = timings->vfp; + cfg->timings.timings.vsw = timings->vsw; + cfg->timings.timings.pixel_clock = timings->pixel_clock; + cfg->timings.vsync_pol = cea_vesa_timings[code].vsync_pol; + cfg->timings.hsync_pol = cea_vesa_timings[code].hsync_pol; +} + +static void hdmi_compute_pll(unsigned long clkin, int phy, + int n, struct hdmi_pll_info *pi) +{ + unsigned long refclk; + u32 mf; + + /* + * Input clock is predivided by N + 1 + * out put of which is reference clk + */ + refclk = clkin / (n + 1); + pi->regn = n; + + /* + * multiplier is pixel_clk/ref_clk + * Multiplying by 100 to avoid fractional part removal + */ + pi->regm = (phy * 100/(refclk))/100; + pi->regm2 = 1; + + /* + * fractional multiplier is remainder of the difference between + * multiplier and actual phy(required pixel clock thus should be + * multiplied by 2^18(262144) divided by the reference clock + */ + mf = (phy - pi->regm * refclk) * 262144; + pi->regmf = mf/(refclk); + + /* + * Dcofreq should be set to 1 if required pixel clock + * is greater than 1000MHz + */ + pi->dcofreq = phy > 1000 * 100; + pi->regsd = ((pi->regm * clkin / 10) / ((n + 1) * 250) + 5) / 10; + + DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf); + DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd); +} + +static void hdmi_enable_clocks(int enable) +{ + if (enable) + dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK | + DSS_CLK_SYSCK | DSS_CLK_VIDFCK); + else + dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK | + DSS_CLK_SYSCK | DSS_CLK_VIDFCK); +} + +static int hdmi_power_on(struct omap_dss_device *dssdev) +{ + int r, code = 0; + struct hdmi_pll_info pll_data; + struct omap_video_timings *p; + int clkin, n, phy; + + hdmi_enable_clocks(1); + + dispc_enable_channel(OMAP_DSS_CHANNEL_DIGIT, 0); + + p = &dssdev->panel.timings; + + DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", + dssdev->panel.timings.x_res, + dssdev->panel.timings.y_res); + + if (!hdmi.custom_set) { + DSSDBG("Read EDID as no EDID is not set on poweron\n"); + hdmi_read_edid(p); + } + code = get_timings_index(); + dssdev->panel.timings = cea_vesa_timings[code].timings; + update_hdmi_timings(&hdmi.cfg, p, code); + + clkin = 3840; /* 38.4 MHz */ + n = 15; /* this is a constant for our math */ + phy = p->pixel_clock; + + hdmi_compute_pll(clkin, phy, n, &pll_data); + + hdmi_wp_video_start(0); + + /* config the PLL and PHY first */ + r = hdmi_pll_program(&pll_data); + if (r) { + DSSDBG("Failed to lock PLL\n"); + goto err; + } + + r = hdmi_phy_init(); + if (r) { + DSSDBG("Failed to start PHY\n"); + goto err; + } + + hdmi.cfg.cm.mode = hdmi.mode; + hdmi.cfg.cm.code = hdmi.code; + hdmi_basic_configure(&hdmi.cfg); + + /* Make selection of HDMI in DSS */ + dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK); + + /* Select the dispc clock source as PRCM clock, to ensure that it is not + * DSI PLL source as the clock selected by DSI PLL might not be + * sufficient for the resolution selected / that can be changed + * dynamically by user. This can be moved to single location , say + * Boardfile. + */ + dss_select_dispc_clk_source(DSS_CLK_SRC_FCK); + + /* bypass TV gamma table */ + dispc_enable_gamma_table(0); + + /* tv size */ + dispc_set_digit_size(dssdev->panel.timings.x_res, + dssdev->panel.timings.y_res); + + dispc_enable_channel(OMAP_DSS_CHANNEL_DIGIT, 1); + + hdmi_wp_video_start(1); + + return 0; +err: + hdmi_enable_clocks(0); + return -EIO; +} + +static void hdmi_power_off(struct omap_dss_device *dssdev) +{ + dispc_enable_channel(OMAP_DSS_CHANNEL_DIGIT, 0); + + hdmi_wp_video_start(0); + hdmi_phy_off(); + hdmi_set_pll_pwr(HDMI_PLLPWRCMD_ALLOFF); + hdmi_enable_clocks(0); + + hdmi.edid_set = 0; +} + +int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev, + struct omap_video_timings *timings) +{ + struct hdmi_cm cm; + + cm = hdmi_get_code(timings); + if (cm.code == -1) { + DSSERR("Invalid timing entered\n"); + return -EINVAL; + } + + return 0; + +} + +void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev) +{ + struct hdmi_cm cm; + + hdmi.custom_set = 1; + cm = hdmi_get_code(&dssdev->panel.timings); + hdmi.code = cm.code; + hdmi.mode = cm.mode; + omapdss_hdmi_display_enable(dssdev); + hdmi.custom_set = 0; +} + +int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev) +{ + int r = 0; + + DSSDBG("ENTER hdmi_display_enable\n"); + + mutex_lock(&hdmi.lock); + + r = omap_dss_start_device(dssdev); + if (r) { + DSSERR("failed to start device\n"); + goto err0; + } + + if (dssdev->platform_enable) { + r = dssdev->platform_enable(dssdev); + if (r) { + DSSERR("failed to enable GPIO's\n"); + goto err1; + } + } + + r = hdmi_power_on(dssdev); + if (r) { + DSSERR("failed to power on device\n"); + goto err2; + } + + mutex_unlock(&hdmi.lock); + return 0; + +err2: + if (dssdev->platform_disable) + dssdev->platform_disable(dssdev); +err1: + omap_dss_stop_device(dssdev); +err0: + mutex_unlock(&hdmi.lock); + return r; +} + +void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev) +{ + DSSDBG("Enter hdmi_display_disable\n"); + + mutex_lock(&hdmi.lock); + + hdmi_power_off(dssdev); + + if (dssdev->platform_disable) + dssdev->platform_disable(dssdev); + + omap_dss_stop_device(dssdev); + + mutex_unlock(&hdmi.lock); +} + +/* HDMI HW IP initialisation */ +static int omapdss_hdmihw_probe(struct platform_device *pdev) +{ + struct resource *hdmi_mem; + + hdmi.pdata = pdev->dev.platform_data; + hdmi.pdev = pdev; + + mutex_init(&hdmi.lock); + + hdmi_mem = platform_get_resource(hdmi.pdev, IORESOURCE_MEM, 0); + if (!hdmi_mem) { + DSSERR("can't get IORESOURCE_MEM HDMI\n"); + return -EINVAL; + } + + /* Base address taken from platform */ + hdmi.base_wp = ioremap(hdmi_mem->start, resource_size(hdmi_mem)); + if (!hdmi.base_wp) { + DSSERR("can't ioremap WP\n"); + return -ENOMEM; + } + + hdmi_panel_init(); + + return 0; +} + +static int omapdss_hdmihw_remove(struct platform_device *pdev) +{ + hdmi_panel_exit(); + + iounmap(hdmi.base_wp); + + return 0; +} + +static struct platform_driver omapdss_hdmihw_driver = { + .probe = omapdss_hdmihw_probe, + .remove = omapdss_hdmihw_remove, + .driver = { + .name = "omapdss_hdmi", + .owner = THIS_MODULE, + }, +}; + +int hdmi_init_platform_driver(void) +{ + return platform_driver_register(&omapdss_hdmihw_driver); +} + +void hdmi_uninit_platform_driver(void) +{ + return platform_driver_unregister(&omapdss_hdmihw_driver); +} From 70be83235ea2815f6c2a5fd45753de406be6c6aa Mon Sep 17 00:00:00 2001 From: Mythri P K Date: Thu, 10 Mar 2011 15:48:48 +0530 Subject: [PATCH 075/140] OMAP4: DSS2: HDMI: HDMI panel driver addition in the DSS The panel driver(hdmi_omap4_panel.c) in omap2/dss acts as a controller to manage the enable and disable requests and synchronize audio and video. Signed-off-by: Mythri P K Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dss.h | 2 + drivers/video/omap2/dss/hdmi_omap4_panel.c | 222 +++++++++++++++++++++ 2 files changed, 224 insertions(+) create mode 100644 drivers/video/omap2/dss/hdmi_omap4_panel.c diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h index 91ed3fa8e60d..c2f582bb19c0 100644 --- a/drivers/video/omap2/dss/dss.h +++ b/drivers/video/omap2/dss/dss.h @@ -477,6 +477,8 @@ void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev); void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev); int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev, struct omap_video_timings *timings); +int hdmi_panel_init(void); +void hdmi_panel_exit(void); /* RFBI */ #ifdef CONFIG_OMAP2_DSS_RFBI diff --git a/drivers/video/omap2/dss/hdmi_omap4_panel.c b/drivers/video/omap2/dss/hdmi_omap4_panel.c new file mode 100644 index 000000000000..ffb5de94131f --- /dev/null +++ b/drivers/video/omap2/dss/hdmi_omap4_panel.c @@ -0,0 +1,222 @@ +/* + * hdmi_omap4_panel.c + * + * HDMI library support functions for TI OMAP4 processors. + * + * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/ + * Authors: Mythri P k + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include + +#include "dss.h" + +static struct { + struct mutex hdmi_lock; +} hdmi; + + +static int hdmi_panel_probe(struct omap_dss_device *dssdev) +{ + DSSDBG("ENTER hdmi_panel_probe\n"); + + dssdev->panel.config = OMAP_DSS_LCD_TFT | + OMAP_DSS_LCD_IVS | OMAP_DSS_LCD_IHS; + + /* + * Initialize the timings to 640 * 480 + * This is only for framebuffer update not for TV timing setting + * Setting TV timing will be done only on enable + */ + dssdev->panel.timings.x_res = 640; + dssdev->panel.timings.y_res = 480; + + DSSDBG("hdmi_panel_probe x_res= %d y_res = %d\n", + dssdev->panel.timings.x_res, + dssdev->panel.timings.y_res); + return 0; +} + +static void hdmi_panel_remove(struct omap_dss_device *dssdev) +{ + +} + +static int hdmi_panel_enable(struct omap_dss_device *dssdev) +{ + int r = 0; + DSSDBG("ENTER hdmi_panel_enable\n"); + + mutex_lock(&hdmi.hdmi_lock); + + if (dssdev->state != OMAP_DSS_DISPLAY_DISABLED) { + r = -EINVAL; + goto err; + } + + r = omapdss_hdmi_display_enable(dssdev); + if (r) { + DSSERR("failed to power on\n"); + goto err; + } + + dssdev->state = OMAP_DSS_DISPLAY_ACTIVE; + +err: + mutex_unlock(&hdmi.hdmi_lock); + + return r; +} + +static void hdmi_panel_disable(struct omap_dss_device *dssdev) +{ + mutex_lock(&hdmi.hdmi_lock); + + if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) + omapdss_hdmi_display_disable(dssdev); + + dssdev->state = OMAP_DSS_DISPLAY_DISABLED; + + mutex_unlock(&hdmi.hdmi_lock); +} + +static int hdmi_panel_suspend(struct omap_dss_device *dssdev) +{ + int r = 0; + + mutex_lock(&hdmi.hdmi_lock); + + if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE) { + r = -EINVAL; + goto err; + } + + dssdev->state = OMAP_DSS_DISPLAY_SUSPENDED; + + omapdss_hdmi_display_disable(dssdev); + +err: + mutex_unlock(&hdmi.hdmi_lock); + + return r; +} + +static int hdmi_panel_resume(struct omap_dss_device *dssdev) +{ + int r = 0; + + mutex_lock(&hdmi.hdmi_lock); + + if (dssdev->state != OMAP_DSS_DISPLAY_SUSPENDED) { + r = -EINVAL; + goto err; + } + + r = omapdss_hdmi_display_enable(dssdev); + if (r) { + DSSERR("failed to power on\n"); + goto err; + } + + dssdev->state = OMAP_DSS_DISPLAY_ACTIVE; + +err: + mutex_unlock(&hdmi.hdmi_lock); + + return r; +} + +static void hdmi_get_timings(struct omap_dss_device *dssdev, + struct omap_video_timings *timings) +{ + mutex_lock(&hdmi.hdmi_lock); + + *timings = dssdev->panel.timings; + + mutex_unlock(&hdmi.hdmi_lock); +} + +static void hdmi_set_timings(struct omap_dss_device *dssdev, + struct omap_video_timings *timings) +{ + DSSDBG("hdmi_set_timings\n"); + + mutex_lock(&hdmi.hdmi_lock); + + dssdev->panel.timings = *timings; + + if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) { + /* turn the hdmi off and on to get new timings to use */ + omapdss_hdmi_display_disable(dssdev); + omapdss_hdmi_display_set_timing(dssdev); + } + + mutex_unlock(&hdmi.hdmi_lock); +} + +static int hdmi_check_timings(struct omap_dss_device *dssdev, + struct omap_video_timings *timings) +{ + int r = 0; + + DSSDBG("hdmi_check_timings\n"); + + mutex_lock(&hdmi.hdmi_lock); + + r = omapdss_hdmi_display_check_timing(dssdev, timings); + if (r) { + DSSERR("Timing cannot be applied\n"); + goto err; + } +err: + mutex_unlock(&hdmi.hdmi_lock); + return r; +} + +static struct omap_dss_driver hdmi_driver = { + .probe = hdmi_panel_probe, + .remove = hdmi_panel_remove, + .enable = hdmi_panel_enable, + .disable = hdmi_panel_disable, + .suspend = hdmi_panel_suspend, + .resume = hdmi_panel_resume, + .get_timings = hdmi_get_timings, + .set_timings = hdmi_set_timings, + .check_timings = hdmi_check_timings, + .driver = { + .name = "hdmi_panel", + .owner = THIS_MODULE, + }, +}; + +int hdmi_panel_init(void) +{ + mutex_init(&hdmi.hdmi_lock); + + omap_dss_register_driver(&hdmi_driver); + + return 0; +} + +void hdmi_panel_exit(void) +{ + omap_dss_unregister_driver(&hdmi_driver); + +} From 642e21bff200610b1d4c0e706d0a6b16ae4e25db Mon Sep 17 00:00:00 2001 From: Mythri P K Date: Thu, 10 Mar 2011 15:12:48 +0530 Subject: [PATCH 076/140] OMAP4: DSS2: HDMI: Add makefile and kconfig changes to enable HDMI in OMAP4 Adding kconfig and makefile changes to add support for HDMI in OMAP4. Signed-off-by: Mythri P K Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/Kconfig | 8 ++++++++ drivers/video/omap2/dss/Makefile | 2 ++ 2 files changed, 10 insertions(+) diff --git a/drivers/video/omap2/dss/Kconfig b/drivers/video/omap2/dss/Kconfig index db01473c3307..bfc5da0e9700 100644 --- a/drivers/video/omap2/dss/Kconfig +++ b/drivers/video/omap2/dss/Kconfig @@ -60,6 +60,14 @@ config OMAP2_DSS_VENC help OMAP Video Encoder support for S-Video and composite TV-out. +config OMAP4_DSS_HDMI + bool "HDMI support" + depends on ARCH_OMAP4 + default y + help + HDMI Interface. This adds the High Definition Multimedia Interface. + See http://www.hdmi.org/ for HDMI specification. + config OMAP2_DSS_SDI bool "SDI support" depends on ARCH_OMAP3 diff --git a/drivers/video/omap2/dss/Makefile b/drivers/video/omap2/dss/Makefile index 7db17b5e570c..10d9d3bb3e24 100644 --- a/drivers/video/omap2/dss/Makefile +++ b/drivers/video/omap2/dss/Makefile @@ -5,3 +5,5 @@ omapdss-$(CONFIG_OMAP2_DSS_RFBI) += rfbi.o omapdss-$(CONFIG_OMAP2_DSS_VENC) += venc.o omapdss-$(CONFIG_OMAP2_DSS_SDI) += sdi.o omapdss-$(CONFIG_OMAP2_DSS_DSI) += dsi.o +omapdss-$(CONFIG_OMAP4_DSS_HDMI) += hdmi.o \ + hdmi_omap4_panel.o From adbc2feee11aef2b3b0f4eff427d2ea5c211e798 Mon Sep 17 00:00:00 2001 From: Mythri P K Date: Wed, 9 Mar 2011 15:40:02 +0530 Subject: [PATCH 077/140] OMAP4: DSS: HDMI: Call to HDMI module init to register driver. calling the platform registration of HDMI driver from core during initialization. Signed-off-by: Mythri P K Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/core.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/video/omap2/dss/core.c b/drivers/video/omap2/dss/core.c index c2f930bf2844..1aa2ed1e786e 100644 --- a/drivers/video/omap2/dss/core.c +++ b/drivers/video/omap2/dss/core.c @@ -209,6 +209,12 @@ static int omap_dss_probe(struct platform_device *pdev) goto err_dsi; } + r = hdmi_init_platform_driver(); + if (r) { + DSSERR("Failed to initialize hdmi\n"); + goto err_hdmi; + } + r = dss_initialize_debugfs(); if (r) goto err_debugfs; @@ -238,6 +244,8 @@ static int omap_dss_probe(struct platform_device *pdev) err_register: dss_uninitialize_debugfs(); err_debugfs: + hdmi_uninit_platform_driver(); +err_hdmi: dsi_uninit_platform_driver(); err_dsi: venc_uninit_platform_driver(); @@ -263,6 +271,7 @@ static int omap_dss_remove(struct platform_device *pdev) dispc_uninit_platform_driver(); rfbi_uninit_platform_driver(); dsi_uninit_platform_driver(); + hdmi_uninit_platform_driver(); dss_uninit_platform_driver(); dss_uninit_overlays(pdev); From 0425b48b3f24b0b2b1f9b4f24fd491b70a8f911c Mon Sep 17 00:00:00 2001 From: Mythri P K Date: Tue, 8 Mar 2011 18:50:09 +0530 Subject: [PATCH 078/140] OMAP4: HDMI: Add HDMI structure in the board file for OMAP4 SDP Adding board file structure for display which adds the display structure with HDMI as the default driver when the display init is called. HDMI GPIO configurations are also done in this file. Signed-off-by: Mythri P K Signed-off-by: Tomi Valkeinen --- arch/arm/mach-omap2/board-4430sdp.c | 75 +++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index 85805d432e38..f5fcc5f2258d 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -36,6 +36,7 @@ #include #include #include +#include #include "mux.h" #include "hsmmc.h" @@ -47,6 +48,8 @@ #define ETH_KS8851_QUART 138 #define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO 184 #define OMAP4_SFH7741_ENABLE_GPIO 188 +#define HDMI_GPIO_HPD 60 /* Hot plug pin for HDMI */ +#define HDMI_GPIO_LS_OE 41 /* Level shifter for HDMI */ static const int sdp4430_keymap[] = { KEY(0, 0, KEY_E), @@ -620,6 +623,76 @@ static void __init omap_sfh7741prox_init(void) } } +static void sdp4430_hdmi_mux_init(void) +{ + /* PAD0_HDMI_HPD_PAD1_HDMI_CEC */ + omap_mux_init_signal("hdmi_hpd", + OMAP_PIN_INPUT_PULLUP); + omap_mux_init_signal("hdmi_cec", + OMAP_PIN_INPUT_PULLUP); + /* PAD0_HDMI_DDC_SCL_PAD1_HDMI_DDC_SDA */ + omap_mux_init_signal("hdmi_ddc_scl", + OMAP_PIN_INPUT_PULLUP); + omap_mux_init_signal("hdmi_ddc_sda", + OMAP_PIN_INPUT_PULLUP); +} + +static int sdp4430_panel_enable_hdmi(struct omap_dss_device *dssdev) +{ + int status; + + status = gpio_request_one(HDMI_GPIO_HPD, GPIOF_OUT_INIT_HIGH, + "hdmi_gpio_hpd"); + if (status) { + pr_err("Cannot request GPIO %d\n", HDMI_GPIO_HPD); + return status; + } + status = gpio_request_one(HDMI_GPIO_LS_OE, GPIOF_OUT_INIT_HIGH, + "hdmi_gpio_ls_oe"); + if (status) { + pr_err("Cannot request GPIO %d\n", HDMI_GPIO_LS_OE); + goto error1; + } + + return 0; + +error1: + gpio_free(HDMI_GPIO_HPD); + + return status; +} + +static void sdp4430_panel_disable_hdmi(struct omap_dss_device *dssdev) +{ + gpio_free(HDMI_GPIO_LS_OE); + gpio_free(HDMI_GPIO_HPD); +} + +static struct omap_dss_device sdp4430_hdmi_device = { + .name = "hdmi", + .driver_name = "hdmi_panel", + .type = OMAP_DISPLAY_TYPE_HDMI, + .platform_enable = sdp4430_panel_enable_hdmi, + .platform_disable = sdp4430_panel_disable_hdmi, + .channel = OMAP_DSS_CHANNEL_DIGIT, +}; + +static struct omap_dss_device *sdp4430_dss_devices[] = { + &sdp4430_hdmi_device, +}; + +static struct omap_dss_board_info sdp4430_dss_data = { + .num_devices = ARRAY_SIZE(sdp4430_dss_devices), + .devices = sdp4430_dss_devices, + .default_device = &sdp4430_hdmi_device, +}; + +void omap_4430sdp_display_init(void) +{ + sdp4430_hdmi_mux_init(); + omap_display_init(&sdp4430_dss_data); +} + #ifdef CONFIG_OMAP_MUX static struct omap_board_mux board_mux[] __initdata = { OMAP4_MUX(USBB2_ULPITLL_CLK, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), @@ -661,6 +734,8 @@ static void __init omap_4430sdp_init(void) status = omap4_keyboard_init(&sdp4430_keypad_data); if (status) pr_err("Keypad initialization failed: %d\n", status); + + omap_4430sdp_display_init(); } static void __init omap_4430sdp_map_io(void) From 17c84ef1e1265fad787d4082bd40a63eb6f3eeb1 Mon Sep 17 00:00:00 2001 From: "K, Mythri P" Date: Mon, 14 Mar 2011 23:57:42 -0500 Subject: [PATCH 079/140] OMAP4: HDMI: Add HDMI structure in the board file for OMAP4 PANDA Adding board file structure for display which adds the display structure with HDMI as the default driver when the display init is called. HDMI GPIO configurations are also done in this file. Signed-off-by: Mythri P K Signed-off-by: Tomi Valkeinen --- arch/arm/mach-omap2/board-omap4panda.c | 74 ++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c index a94ce07be72f..795ffc461522 100644 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ b/arch/arm/mach-omap2/board-omap4panda.c @@ -34,6 +34,7 @@ #include #include #include +#include #include #include @@ -49,6 +50,8 @@ #define GPIO_HUB_NRESET 62 #define GPIO_WIFI_PMENA 43 #define GPIO_WIFI_IRQ 53 +#define HDMI_GPIO_HPD 60 /* Hot plug pin for HDMI */ +#define HDMI_GPIO_LS_OE 41 /* Level shifter for HDMI */ /* wl127x BT, FM, GPS connectivity chip */ static int wl1271_gpios[] = {46, -1, -1}; @@ -467,6 +470,76 @@ static struct omap_board_mux board_mux[] __initdata = { #define board_mux NULL #endif +static void omap4_panda_hdmi_mux_init(void) +{ + /* PAD0_HDMI_HPD_PAD1_HDMI_CEC */ + omap_mux_init_signal("hdmi_hpd", + OMAP_PIN_INPUT_PULLUP); + omap_mux_init_signal("hdmi_cec", + OMAP_PIN_INPUT_PULLUP); + /* PAD0_HDMI_DDC_SCL_PAD1_HDMI_DDC_SDA */ + omap_mux_init_signal("hdmi_ddc_scl", + OMAP_PIN_INPUT_PULLUP); + omap_mux_init_signal("hdmi_ddc_sda", + OMAP_PIN_INPUT_PULLUP); +} + +static int omap4_panda_panel_enable_hdmi(struct omap_dss_device *dssdev) +{ + int status; + + status = gpio_request_one(HDMI_GPIO_HPD, GPIOF_OUT_INIT_HIGH, + "hdmi_gpio_hpd"); + if (status) { + pr_err("Cannot request GPIO %d\n", HDMI_GPIO_HPD); + return status; + } + status = gpio_request_one(HDMI_GPIO_LS_OE, GPIOF_OUT_INIT_HIGH, + "hdmi_gpio_ls_oe"); + if (status) { + pr_err("Cannot request GPIO %d\n", HDMI_GPIO_LS_OE); + goto error1; + } + + return 0; + +error1: + gpio_free(HDMI_GPIO_HPD); + + return status; +} + +static void omap4_panda_panel_disable_hdmi(struct omap_dss_device *dssdev) +{ + gpio_free(HDMI_GPIO_LS_OE); + gpio_free(HDMI_GPIO_HPD); +} + +static struct omap_dss_device omap4_panda_hdmi_device = { + .name = "hdmi", + .driver_name = "hdmi_panel", + .type = OMAP_DISPLAY_TYPE_HDMI, + .platform_enable = omap4_panda_panel_enable_hdmi, + .platform_disable = omap4_panda_panel_disable_hdmi, + .channel = OMAP_DSS_CHANNEL_DIGIT, +}; + +static struct omap_dss_device *omap4_panda_dss_devices[] = { + &omap4_panda_hdmi_device, +}; + +static struct omap_dss_board_info omap4_panda_dss_data = { + .num_devices = ARRAY_SIZE(omap4_panda_dss_devices), + .devices = omap4_panda_dss_devices, + .default_device = &omap4_panda_hdmi_device, +}; + +void omap4_panda_display_init(void) +{ + omap4_panda_hdmi_mux_init(); + omap_display_init(&omap4_panda_dss_data); +} + static void __init omap4_panda_init(void) { int package = OMAP_PACKAGE_CBS; @@ -485,6 +558,7 @@ static void __init omap4_panda_init(void) omap4_twl6030_hsmmc_init(mmc); omap4_ehci_init(); usb_musb_init(&musb_board_data); + omap4_panda_display_init(); } static void __init omap4_panda_map_io(void) From 0acf659f1469725fb6e39d53af970f36c5f69a41 Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Mon, 14 Mar 2011 07:28:57 -0500 Subject: [PATCH 080/140] OMAP: DSS2: Clean up for dpll4_m4_ck handling OMAP2 does not have dpll4_m4_ck source clock for dss functional clock, but later OMAPs do. Currently we check for cpu type in multiple places to find out if dpll4_m4_ck is available. This patch cleans up dss.c by using the fact that dss.dpll4_m4_ck pointer is NULL on OMAP2. This allows us to remove many of the cpu checks. Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dss.c | 93 ++++++++++++++++++++++------------- 1 file changed, 59 insertions(+), 34 deletions(-) diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c index f1628bd850d1..9d2390299df7 100644 --- a/drivers/video/omap2/dss/dss.c +++ b/drivers/video/omap2/dss/dss.c @@ -239,30 +239,40 @@ void dss_dump_clocks(struct seq_file *s) { unsigned long dpll4_ck_rate; unsigned long dpll4_m4_ck_rate; + const char *fclk_name, *fclk_real_name; + unsigned long fclk_rate; dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); - dpll4_ck_rate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); - dpll4_m4_ck_rate = clk_get_rate(dss.dpll4_m4_ck); - seq_printf(s, "- DSS -\n"); - seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate); + fclk_name = dss_get_generic_clk_source_name(DSS_CLK_SRC_FCK); + fclk_real_name = dss_feat_get_clk_source_name(DSS_CLK_SRC_FCK); + fclk_rate = dss_clk_get_rate(DSS_CLK_FCK); - if (cpu_is_omap3630()) - seq_printf(s, "%s (%s) = %lu / %lu = %lu\n", - dss_get_generic_clk_source_name(DSS_CLK_SRC_FCK), - dss_feat_get_clk_source_name(DSS_CLK_SRC_FCK), - dpll4_ck_rate, - dpll4_ck_rate / dpll4_m4_ck_rate, - dss_clk_get_rate(DSS_CLK_FCK)); - else - seq_printf(s, "%s (%s) = %lu / %lu * 2 = %lu\n", - dss_get_generic_clk_source_name(DSS_CLK_SRC_FCK), - dss_feat_get_clk_source_name(DSS_CLK_SRC_FCK), - dpll4_ck_rate, - dpll4_ck_rate / dpll4_m4_ck_rate, - dss_clk_get_rate(DSS_CLK_FCK)); + if (dss.dpll4_m4_ck) { + dpll4_ck_rate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); + dpll4_m4_ck_rate = clk_get_rate(dss.dpll4_m4_ck); + + seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate); + + if (cpu_is_omap3630()) + seq_printf(s, "%s (%s) = %lu / %lu = %lu\n", + fclk_name, fclk_real_name, + dpll4_ck_rate, + dpll4_ck_rate / dpll4_m4_ck_rate, + fclk_rate); + else + seq_printf(s, "%s (%s) = %lu / %lu * 2 = %lu\n", + fclk_name, fclk_real_name, + dpll4_ck_rate, + dpll4_ck_rate / dpll4_m4_ck_rate, + fclk_rate); + } else { + seq_printf(s, "%s (%s) = %lu\n", + fclk_name, fclk_real_name, + fclk_rate); + } dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); } @@ -382,31 +392,40 @@ enum dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel) /* calculate clock rates using dividers in cinfo */ int dss_calc_clock_rates(struct dss_clock_info *cinfo) { - unsigned long prate; + if (dss.dpll4_m4_ck) { + unsigned long prate; - if (cinfo->fck_div > (cpu_is_omap3630() ? 32 : 16) || - cinfo->fck_div == 0) - return -EINVAL; + if (cinfo->fck_div > (cpu_is_omap3630() ? 32 : 16) || + cinfo->fck_div == 0) + return -EINVAL; - prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); + prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); - cinfo->fck = prate / cinfo->fck_div; + cinfo->fck = prate / cinfo->fck_div; + } else { + if (cinfo->fck_div != 0) + return -EINVAL; + cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK); + } return 0; } int dss_set_clock_div(struct dss_clock_info *cinfo) { - unsigned long prate; - int r; + if (dss.dpll4_m4_ck) { + unsigned long prate; + int r; - if (cpu_is_omap34xx()) { prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); DSSDBG("dpll4_m4 = %ld\n", prate); r = clk_set_rate(dss.dpll4_m4_ck, prate / cinfo->fck_div); if (r) return r; + } else { + if (cinfo->fck_div != 0) + return -EINVAL; } DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div); @@ -418,9 +437,11 @@ int dss_get_clock_div(struct dss_clock_info *cinfo) { cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK); - if (cpu_is_omap34xx()) { + if (dss.dpll4_m4_ck) { unsigned long prate; + prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); + if (cpu_is_omap3630()) cinfo->fck_div = prate / (cinfo->fck); else @@ -434,7 +455,7 @@ int dss_get_clock_div(struct dss_clock_info *cinfo) unsigned long dss_get_dpll4_rate(void) { - if (cpu_is_omap34xx()) + if (dss.dpll4_m4_ck) return clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); else return 0; @@ -615,6 +636,7 @@ static int dss_init(void) int r; u32 rev; struct resource *dss_mem; + struct clk *dpll4_m4_ck; dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0); if (!dss_mem) { @@ -655,16 +677,19 @@ static int dss_init(void) REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */ REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */ #endif - if (cpu_is_omap34xx()) { - dss.dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck"); - if (IS_ERR(dss.dpll4_m4_ck)) { + dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck"); + if (IS_ERR(dpll4_m4_ck)) { DSSERR("Failed to get dpll4_m4_ck\n"); - r = PTR_ERR(dss.dpll4_m4_ck); + r = PTR_ERR(dpll4_m4_ck); goto fail1; } + } else { /* omap24xx */ + dpll4_m4_ck = NULL; } + dss.dpll4_m4_ck = dpll4_m4_ck; + dss.dsi_clk_source = DSS_CLK_SRC_FCK; dss.dispc_clk_source = DSS_CLK_SRC_FCK; dss.lcd_clk_source[0] = DSS_CLK_SRC_FCK; @@ -686,7 +711,7 @@ fail0: static void dss_exit(void) { - if (cpu_is_omap34xx()) + if (dss.dpll4_m4_ck) clk_put(dss.dpll4_m4_ck); iounmap(dss.base); From 2de110868f455b74e91111801ce63a3c9d06f091 Mon Sep 17 00:00:00 2001 From: "Murthy, Raghuveer" Date: Mon, 14 Mar 2011 07:28:58 -0500 Subject: [PATCH 081/140] OMAP: DSS2: Implement OMAP4 DSS fclk support Add dss.dpll4_m4_ck (DSS FCLK) initialization for OMAP4. This is used to compute the pixel clock for DPI interface and also to reconfigure the DSS FCLK to the desired rate, corresponding to the rate computed for pixel clock. Adding these cpu_is_44xx() checks are meant to be temporary, until a cleaner implementation to manage these checks are added. Currently this is needed to get DVI display running on OMAP4 PandaBoard Signed-off-by: Raghuveer Murthy [tomi.valkeinen@ti.com: minor changes due to conflicts] Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dss.c | 34 ++++++++++++++++++++++------------ 1 file changed, 22 insertions(+), 12 deletions(-) diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c index 9d2390299df7..3f1fee63c678 100644 --- a/drivers/video/omap2/dss/dss.c +++ b/drivers/video/omap2/dss/dss.c @@ -256,7 +256,7 @@ void dss_dump_clocks(struct seq_file *s) seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate); - if (cpu_is_omap3630()) + if (cpu_is_omap3630() || cpu_is_omap44xx()) seq_printf(s, "%s (%s) = %lu / %lu = %lu\n", fclk_name, fclk_real_name, dpll4_ck_rate, @@ -394,9 +394,12 @@ int dss_calc_clock_rates(struct dss_clock_info *cinfo) { if (dss.dpll4_m4_ck) { unsigned long prate; + u16 fck_div_max = 16; - if (cinfo->fck_div > (cpu_is_omap3630() ? 32 : 16) || - cinfo->fck_div == 0) + if (cpu_is_omap3630() || cpu_is_omap44xx()) + fck_div_max = 32; + + if (cinfo->fck_div > fck_div_max || cinfo->fck_div == 0) return -EINVAL; prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); @@ -442,7 +445,7 @@ int dss_get_clock_div(struct dss_clock_info *cinfo) prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); - if (cpu_is_omap3630()) + if (cpu_is_omap3630() || cpu_is_omap44xx()) cinfo->fck_div = prate / (cinfo->fck); else cinfo->fck_div = prate / (cinfo->fck / 2); @@ -471,7 +474,7 @@ int dss_calc_clock_div(bool is_tft, unsigned long req_pck, unsigned long fck, max_dss_fck; - u16 fck_div; + u16 fck_div, fck_div_max = 16; int match = 0; int min_fck_per_pck; @@ -504,7 +507,7 @@ retry: memset(&best_dss, 0, sizeof(best_dss)); memset(&best_dispc, 0, sizeof(best_dispc)); - if (cpu_is_omap24xx()) { + if (dss.dpll4_m4_ck == NULL) { struct dispc_clock_info cur_dispc; /* XXX can we change the clock on omap2? */ fck = dss_clk_get_rate(DSS_CLK_FCK); @@ -519,12 +522,14 @@ retry: best_dispc = cur_dispc; goto found; - } else if (cpu_is_omap34xx()) { - for (fck_div = (cpu_is_omap3630() ? 32 : 16); - fck_div > 0; --fck_div) { + } else { + if (cpu_is_omap3630() || cpu_is_omap44xx()) + fck_div_max = 32; + + for (fck_div = fck_div_max; fck_div > 0; --fck_div) { struct dispc_clock_info cur_dispc; - if (cpu_is_omap3630()) + if (fck_div_max == 32) fck = prate / fck_div; else fck = prate / fck_div * 2; @@ -552,8 +557,6 @@ retry: goto found; } } - } else { - BUG(); } found: @@ -684,6 +687,13 @@ static int dss_init(void) r = PTR_ERR(dpll4_m4_ck); goto fail1; } + } else if (cpu_is_omap44xx()) { + dpll4_m4_ck = clk_get(NULL, "dpll_per_m5x2_ck"); + if (IS_ERR(dpll4_m4_ck)) { + DSSERR("Failed to get dpll4_m4_ck\n"); + r = PTR_ERR(dpll4_m4_ck); + goto fail1; + } } else { /* omap24xx */ dpll4_m4_ck = NULL; } From b295d6e593e02168fdafc5db11464b6d51cf239d Mon Sep 17 00:00:00 2001 From: "Murthy, Raghuveer" Date: Mon, 14 Mar 2011 07:52:25 -0500 Subject: [PATCH 082/140] OMAP4: PandaBoard: Adding DVI support Adding DVI support to OMAP4 PandaBoard. PandaBoard uses TFP410 DVI Framer chip http://focus.ti.com/lit/ds/symlink/tfp410.pdf The TFP410 gets its power enable and display data over GPIO lines muxed in from OMAP4430. PandaBoard supports other LCD displays through expansion connectors, following board rework. This will disable the DVI interface. However, the existing mux settings remain the same PandaBoard additionally supports display over HDMI interface. It is mutually exclusive to display over DVI. Hence the mux settings need to be configured seperately, as and when HDMI is enabled Also, I2C3 bus used for reading EDID data from DVI Monitors is registered here. Since the design is similar to BeagleBoard, the code for the same is taken from the kernel.org commit e3333f48dd5cb21 (omap: Adding beagle i2c eeprom driver to read EDID) Reviewed-by: Manjunath G Kondaiah Reviewed-by: Anand Gadiyar Reviewed-by: Nishanth Menon Reviewed-by: Sumit Semwal Signed-off-by: Raghuveer Murthy [tomi.valkeinen@ti.com: fixed conflicts with HDMI] Signed-off-by: Tomi Valkeinen --- arch/arm/mach-omap2/board-omap4panda.c | 131 ++++++++++++++++++++++++- 1 file changed, 129 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c index 795ffc461522..e2b912f376cc 100644 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ b/arch/arm/mach-omap2/board-omap4panda.c @@ -40,6 +40,7 @@ #include #include #include +#include #include "timer-gp.h" #include "hsmmc.h" @@ -435,6 +436,17 @@ static struct i2c_board_info __initdata omap4_panda_i2c_boardinfo[] = { .platform_data = &omap4_panda_twldata, }, }; + +/* + * Display monitor features are burnt in their EEPROM as EDID data. The EEPROM + * is connected as I2C slave device, and can be accessed at address 0x50 + */ +static struct i2c_board_info __initdata panda_i2c_eeprom[] = { + { + I2C_BOARD_INFO("eeprom", 0x50), + }, +}; + static int __init omap4_panda_i2c_init(void) { /* @@ -444,7 +456,12 @@ static int __init omap4_panda_i2c_init(void) omap_register_i2c_bus(1, 400, omap4_panda_i2c_boardinfo, ARRAY_SIZE(omap4_panda_i2c_boardinfo)); omap_register_i2c_bus(2, 400, NULL, 0); - omap_register_i2c_bus(3, 400, NULL, 0); + /* + * Bus 3 is attached to the DVI port where devices like the pico DLP + * projector don't work reliably with 400kHz + */ + omap_register_i2c_bus(3, 100, panda_i2c_eeprom, + ARRAY_SIZE(panda_i2c_eeprom)); omap_register_i2c_bus(4, 400, NULL, 0); return 0; } @@ -464,12 +481,115 @@ static struct omap_board_mux board_mux[] __initdata = { OMAP4_MUX(SDMMC5_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), OMAP4_MUX(SDMMC5_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), OMAP4_MUX(SDMMC5_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), + /* gpio 0 - TFP410 PD */ + OMAP4_MUX(KPD_COL1, OMAP_PIN_OUTPUT | OMAP_MUX_MODE3), + /* dispc2_data23 */ + OMAP4_MUX(USBB2_ULPITLL_STP, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_data22 */ + OMAP4_MUX(USBB2_ULPITLL_DIR, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_data21 */ + OMAP4_MUX(USBB2_ULPITLL_NXT, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_data20 */ + OMAP4_MUX(USBB2_ULPITLL_DAT0, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_data19 */ + OMAP4_MUX(USBB2_ULPITLL_DAT1, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_data18 */ + OMAP4_MUX(USBB2_ULPITLL_DAT2, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_data15 */ + OMAP4_MUX(USBB2_ULPITLL_DAT3, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_data14 */ + OMAP4_MUX(USBB2_ULPITLL_DAT4, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_data13 */ + OMAP4_MUX(USBB2_ULPITLL_DAT5, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_data12 */ + OMAP4_MUX(USBB2_ULPITLL_DAT6, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_data11 */ + OMAP4_MUX(USBB2_ULPITLL_DAT7, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_data10 */ + OMAP4_MUX(DPM_EMU3, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_data9 */ + OMAP4_MUX(DPM_EMU4, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_data16 */ + OMAP4_MUX(DPM_EMU5, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_data17 */ + OMAP4_MUX(DPM_EMU6, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_hsync */ + OMAP4_MUX(DPM_EMU7, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_pclk */ + OMAP4_MUX(DPM_EMU8, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_vsync */ + OMAP4_MUX(DPM_EMU9, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_de */ + OMAP4_MUX(DPM_EMU10, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_data8 */ + OMAP4_MUX(DPM_EMU11, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_data7 */ + OMAP4_MUX(DPM_EMU12, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_data6 */ + OMAP4_MUX(DPM_EMU13, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_data5 */ + OMAP4_MUX(DPM_EMU14, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_data4 */ + OMAP4_MUX(DPM_EMU15, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_data3 */ + OMAP4_MUX(DPM_EMU16, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_data2 */ + OMAP4_MUX(DPM_EMU17, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_data1 */ + OMAP4_MUX(DPM_EMU18, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), + /* dispc2_data0 */ + OMAP4_MUX(DPM_EMU19, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), { .reg_offset = OMAP_MUX_TERMINATOR }, }; #else #define board_mux NULL #endif +/* Display DVI */ +#define PANDA_DVI_TFP410_POWER_DOWN_GPIO 0 + +static int omap4_panda_enable_dvi(struct omap_dss_device *dssdev) +{ + gpio_set_value(dssdev->reset_gpio, 1); + return 0; +} + +static void omap4_panda_disable_dvi(struct omap_dss_device *dssdev) +{ + gpio_set_value(dssdev->reset_gpio, 0); +} + +/* Using generic display panel */ +static struct panel_generic_dpi_data omap4_dvi_panel = { + .name = "generic", + .platform_enable = omap4_panda_enable_dvi, + .platform_disable = omap4_panda_disable_dvi, +}; + +struct omap_dss_device omap4_panda_dvi_device = { + .type = OMAP_DISPLAY_TYPE_DPI, + .name = "dvi", + .driver_name = "generic_dpi_panel", + .data = &omap4_dvi_panel, + .phy.dpi.data_lines = 24, + .reset_gpio = PANDA_DVI_TFP410_POWER_DOWN_GPIO, + .channel = OMAP_DSS_CHANNEL_LCD2, +}; + +int __init omap4_panda_dvi_init(void) +{ + int r; + + /* Requesting TFP410 DVI GPIO and disabling it, at bootup */ + r = gpio_request_one(omap4_panda_dvi_device.reset_gpio, + GPIOF_OUT_INIT_LOW, "DVI PD"); + if (r) + pr_err("Failed to get DVI powerdown GPIO\n"); + + return r; +} + + static void omap4_panda_hdmi_mux_init(void) { /* PAD0_HDMI_HPD_PAD1_HDMI_CEC */ @@ -525,17 +645,24 @@ static struct omap_dss_device omap4_panda_hdmi_device = { }; static struct omap_dss_device *omap4_panda_dss_devices[] = { + &omap4_panda_dvi_device, &omap4_panda_hdmi_device, }; static struct omap_dss_board_info omap4_panda_dss_data = { .num_devices = ARRAY_SIZE(omap4_panda_dss_devices), .devices = omap4_panda_dss_devices, - .default_device = &omap4_panda_hdmi_device, + .default_device = &omap4_panda_dvi_device, }; void omap4_panda_display_init(void) { + int r; + + r = omap4_panda_dvi_init(); + if (r) + pr_err("error initializing panda DVI\n"); + omap4_panda_hdmi_mux_init(); omap_display_init(&omap4_panda_dss_data); } From 4fdf30c44bb2e97a9f8f2b57764c5acd89267d4c Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Tue, 22 Mar 2011 14:31:35 +0900 Subject: [PATCH 083/140] mailmap: Update for OMAP DSS developers. TI folks seem to have a rather schizophrenic relationship with author naming conventions, stub in mailmap entries to match with the sign-off convention. Signed-off-by: Paul Mundt --- .mailmap | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/.mailmap b/.mailmap index 1eba28acab64..5a6dd592eedc 100644 --- a/.mailmap +++ b/.mailmap @@ -20,6 +20,7 @@ Andreas Herrmann Andrew Morton Andrew Vasquez Andy Adamson +Archit Taneja Arnaud Patard Arnd Bergmann Axel Dyks @@ -70,6 +71,7 @@ Leonid I Ananiev Linas Vepstas Mark Brown Matthieu CASTET +Mayuresh Janorkar Michael Buesch Michael Buesch Michel Dänzer @@ -78,6 +80,7 @@ Morten Welinder Morten Welinder Morten Welinder Morten Welinder +Mythri P K Nguyen Anh Quynh Paolo 'Blaisorblade' Giarrusso Patrick Mochel @@ -98,6 +101,7 @@ S.Çağlar Onur Simon Kelley Stéphane Witzmann Stephen Hemminger +Sumit Semwal Tejun Heo Thomas Graf Tony Luck From 9913319fc0b47f3f740633165dee4807d94d0096 Mon Sep 17 00:00:00 2001 From: "Kirill A. Shutemov" Date: Tue, 15 Mar 2011 22:53:18 +0000 Subject: [PATCH 084/140] omap: use list_move() instead of list_del()/list_add() combination Signed-off-by: Kirill A. Shutemov Acked-by: Tomi Valkeinen Signed-off-by: Paul Mundt --- drivers/video/omap/blizzard.c | 3 +-- drivers/video/omap/hwa742.c | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/video/omap/blizzard.c b/drivers/video/omap/blizzard.c index 87785c215a52..c0504a8a5079 100644 --- a/drivers/video/omap/blizzard.c +++ b/drivers/video/omap/blizzard.c @@ -397,8 +397,7 @@ static inline void free_req(struct blizzard_request *req) spin_lock_irqsave(&blizzard.req_lock, flags); - list_del(&req->entry); - list_add(&req->entry, &blizzard.free_req_list); + list_move(&req->entry, &blizzard.free_req_list); if (!(req->flags & REQ_FROM_IRQ_POOL)) up(&blizzard.req_sema); diff --git a/drivers/video/omap/hwa742.c b/drivers/video/omap/hwa742.c index 0016f77cd13f..084aa0ac562b 100644 --- a/drivers/video/omap/hwa742.c +++ b/drivers/video/omap/hwa742.c @@ -269,8 +269,7 @@ static inline void free_req(struct hwa742_request *req) spin_lock_irqsave(&hwa742.req_lock, flags); - list_del(&req->entry); - list_add(&req->entry, &hwa742.free_req_list); + list_move(&req->entry, &hwa742.free_req_list); if (!(req->flags & REQ_FROM_IRQ_POOL)) up(&hwa742.req_sema); From 1721af4d8581587409d66d4fe0be6bc455611e5b Mon Sep 17 00:00:00 2001 From: "Kirill A. Shutemov" Date: Tue, 15 Mar 2011 22:53:19 +0000 Subject: [PATCH 085/140] vmlfb: use list_move() instead of list_del()/list_add() combination Signed-off-by: Kirill A. Shutemov Signed-off-by: Paul Mundt --- drivers/video/vermilion/vermilion.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/video/vermilion/vermilion.c b/drivers/video/vermilion/vermilion.c index 931a567f9aff..970e43d13f52 100644 --- a/drivers/video/vermilion/vermilion.c +++ b/drivers/video/vermilion/vermilion.c @@ -891,8 +891,7 @@ static int vmlfb_set_par(struct fb_info *info) int ret; mutex_lock(&vml_mutex); - list_del(&vinfo->head); - list_add(&vinfo->head, (subsys) ? &global_has_mode : &global_no_mode); + list_move(&vinfo->head, (subsys) ? &global_has_mode : &global_no_mode); ret = vmlfb_set_par_locked(vinfo); mutex_unlock(&vml_mutex); From 83ea0f164c35fb847afd9309be9ba40431fc501d Mon Sep 17 00:00:00 2001 From: Aaro Koskinen Date: Sun, 13 Feb 2011 22:11:23 +0000 Subject: [PATCH 086/140] sisfb: POST should fail if R/W test fails Currently there is no indication if R/W test fails during POST. This can happen e.g. when user plugs in a card with unsupported type of memory. Since the driver will be unusable, it's better to fail the whole POST if the memory cannot be configured properly. Signed-off-by: Aaro Koskinen Cc: Thomas Winischhofer Signed-off-by: Paul Mundt --- drivers/video/sis/sis_main.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/drivers/video/sis/sis_main.c b/drivers/video/sis/sis_main.c index 2fb8c5a660fb..2c5de66dacf8 100644 --- a/drivers/video/sis/sis_main.c +++ b/drivers/video/sis/sis_main.c @@ -4627,11 +4627,11 @@ sisfb_post_xgi_rwtest(struct sis_video_info *ivideo, int starta, return 1; } -static void __devinit +static int __devinit sisfb_post_xgi_ramsize(struct sis_video_info *ivideo) { unsigned int buswidth, ranksize, channelab, mapsize; - int i, j, k, l; + int i, j, k, l, status; u8 reg, sr14; static const u8 dramsr13[12 * 5] = { 0x02, 0x0e, 0x0b, 0x80, 0x5d, @@ -4673,7 +4673,7 @@ sisfb_post_xgi_ramsize(struct sis_video_info *ivideo) SiS_SetReg(SISSR, 0x13, 0x35); SiS_SetReg(SISSR, 0x14, 0x41); /* TODO */ - return; + return -ENOMEM; } /* Non-interleaving */ @@ -4835,6 +4835,7 @@ bail_out: j = (ivideo->chip == XGI_20) ? 5 : 9; k = (ivideo->chip == XGI_20) ? 12 : 4; + status = -EIO; for(i = 0; i < k; i++) { @@ -4868,11 +4869,15 @@ bail_out: SiS_SetRegANDOR(SISSR, 0x14, 0x0f, (reg & 0xf0)); sisfb_post_xgi_delay(ivideo, 1); - if(sisfb_post_xgi_rwtest(ivideo, j, ((reg >> 4) + channelab - 2 + 20), mapsize)) + if (sisfb_post_xgi_rwtest(ivideo, j, ((reg >> 4) + channelab - 2 + 20), mapsize)) { + status = 0; break; + } } iounmap(ivideo->video_vbase); + + return status; } static void __devinit @@ -5648,6 +5653,7 @@ sisfb_post_xgi(struct pci_dev *pdev) SiS_SetReg(SISSR, 0x14, bios[regb + 0xe0 + 8]); } else { + int err; /* Set default mode, don't clear screen */ ivideo->SiS_Pr.SiS_UseOEM = false; @@ -5661,10 +5667,16 @@ sisfb_post_xgi(struct pci_dev *pdev) /* Disable read-cache */ SiS_SetRegAND(SISSR, 0x21, 0xdf); - sisfb_post_xgi_ramsize(ivideo); + err = sisfb_post_xgi_ramsize(ivideo); /* Enable read-cache */ SiS_SetRegOR(SISSR, 0x21, 0x20); + if (err) { + dev_err(&pdev->dev, + "%s: RAM size detection failed: %d\n", + __func__, err); + return 0; + } } #if 0 From 74de5f4e52bf6e2ee1fe559d53c5dbf0d9d6e4cd Mon Sep 17 00:00:00 2001 From: Aaro Koskinen Date: Sun, 13 Feb 2011 22:11:24 +0000 Subject: [PATCH 087/140] sisfb: move XGI POST RAM type detection into a subroutine Move XGI POST RAM type detection into a separate subroutine to make further code changes easier. No changes in functionality Signed-off-by: Aaro Koskinen Cc: Thomas Winischhofer Signed-off-by: Paul Mundt --- drivers/video/sis/sis_main.c | 57 ++++++++++++++++++++++-------------- 1 file changed, 35 insertions(+), 22 deletions(-) diff --git a/drivers/video/sis/sis_main.c b/drivers/video/sis/sis_main.c index 2c5de66dacf8..364559b12fc5 100644 --- a/drivers/video/sis/sis_main.c +++ b/drivers/video/sis/sis_main.c @@ -4936,6 +4936,40 @@ sisfb_post_xgi_setclocks(struct sis_video_info *ivideo, u8 regb) sisfb_post_xgi_delay(ivideo, 0x43); } +static u8 __devinit +sisfb_post_xgi_ramtype(struct sis_video_info *ivideo) +{ + unsigned char *bios = ivideo->bios_abase; + u8 ramtype; + u8 reg; + u8 v1; + + ramtype = 0x00; v1 = 0x10; + if (ivideo->haveXGIROM) { + ramtype = bios[0x62]; + v1 = bios[0x1d2]; + } + if (!(ramtype & 0x80)) { + if (ivideo->chip == XGI_20) { + SiS_SetReg(SISCR, 0x97, v1); + reg = SiS_GetReg(SISCR, 0x97); + if (reg & 0x10) { + ramtype = (reg & 0x01) << 1; + } + } else { + reg = SiS_GetReg(SISSR, 0x39); + ramtype = reg & 0x02; + if (!(ramtype)) { + reg = SiS_GetReg(SISSR, 0x3a); + ramtype = (reg >> 1) & 0x01; + } + } + } + ramtype &= 0x07; + + return ramtype; +} + static int __devinit sisfb_post_xgi(struct pci_dev *pdev) { @@ -5380,28 +5414,7 @@ sisfb_post_xgi(struct pci_dev *pdev) SiS_SetReg(SISSR, 0x1c, 0x00); } - ramtype = 0x00; v1 = 0x10; - if(ivideo->haveXGIROM) { - ramtype = bios[0x62]; - v1 = bios[0x1d2]; - } - if(!(ramtype & 0x80)) { - if(ivideo->chip == XGI_20) { - SiS_SetReg(SISCR, 0x97, v1); - reg = SiS_GetReg(SISCR, 0x97); - if(reg & 0x10) { - ramtype = (reg & 0x01) << 1; - } - } else { - reg = SiS_GetReg(SISSR, 0x39); - ramtype = reg & 0x02; - if(!(ramtype)) { - reg = SiS_GetReg(SISSR, 0x3a); - ramtype = (reg >> 1) & 0x01; - } - } - } - ramtype &= 0x07; + ramtype = sisfb_post_xgi_ramtype(ivideo); regb = 0; /* ! */ From 929c972e9589644805577317a38f1cd6b3ce5fc2 Mon Sep 17 00:00:00 2001 From: Aaro Koskinen Date: Sun, 13 Feb 2011 22:11:25 +0000 Subject: [PATCH 088/140] sisfb: add subroutine for detecting XGI Z9 Z7 and Z9 have the same PCI ID, so additional checking is needed to detect Z9. The method was "documented" in XGI's xgifb driver. Signed-off-by: Aaro Koskinen Cc: Thomas Winischhofer Signed-off-by: Paul Mundt --- drivers/video/sis/sis.h | 1 + drivers/video/sis/sis_main.c | 18 ++++++++++++++++++ drivers/video/sis/vgatypes.h | 1 + 3 files changed, 20 insertions(+) diff --git a/drivers/video/sis/sis.h b/drivers/video/sis/sis.h index eac7a01925f3..1987f1b7212f 100644 --- a/drivers/video/sis/sis.h +++ b/drivers/video/sis/sis.h @@ -495,6 +495,7 @@ struct sis_video_info { unsigned int refresh_rate; unsigned int chip; + unsigned int chip_real_id; u8 revision_id; int sisvga_enabled; /* PCI device was enabled */ diff --git a/drivers/video/sis/sis_main.c b/drivers/video/sis/sis_main.c index 364559b12fc5..f0c48e84bcdb 100644 --- a/drivers/video/sis/sis_main.c +++ b/drivers/video/sis/sis_main.c @@ -4563,6 +4563,11 @@ sisfb_post_sis315330(struct pci_dev *pdev) } #endif +static inline int sisfb_xgi_is21(struct sis_video_info *ivideo) +{ + return ivideo->chip_real_id == XGI_21; +} + static void __devinit sisfb_post_xgi_delay(struct sis_video_info *ivideo, int delay) { @@ -5802,6 +5807,7 @@ sisfb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) #endif ivideo->chip = chipinfo->chip; + ivideo->chip_real_id = chipinfo->chip; ivideo->sisvga_engine = chipinfo->vgaengine; ivideo->hwcursor_size = chipinfo->hwcursor_size; ivideo->CRT2_write_enable = chipinfo->CRT2_write_enable; @@ -6035,6 +6041,18 @@ sisfb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) sisfb_detect_custom_timing(ivideo); } +#ifdef CONFIG_FB_SIS_315 + if (ivideo->chip == XGI_20) { + /* Check if our Z7 chip is actually Z9 */ + SiS_SetRegOR(SISCR, 0x4a, 0x40); /* GPIOG EN */ + reg = SiS_GetReg(SISCR, 0x48); + if (reg & 0x02) { /* GPIOG */ + ivideo->chip_real_id = XGI_21; + dev_info(&pdev->dev, "Z9 detected\n"); + } + } +#endif + /* POST card in case this has not been done by the BIOS */ if( (!ivideo->sisvga_enabled) #if !defined(__i386__) && !defined(__x86_64__) diff --git a/drivers/video/sis/vgatypes.h b/drivers/video/sis/vgatypes.h index 12c0dfaf2518..e3f9976cfef0 100644 --- a/drivers/video/sis/vgatypes.h +++ b/drivers/video/sis/vgatypes.h @@ -87,6 +87,7 @@ typedef enum _SIS_CHIP_TYPE { SIS_341, SIS_342, XGI_20 = 75, + XGI_21, XGI_40, MAX_SIS_CHIP } SIS_CHIP_TYPE; From 5e8700bf6db24ccf6814c765519d8986f1c16357 Mon Sep 17 00:00:00 2001 From: Aaro Koskinen Date: Sun, 13 Feb 2011 22:11:26 +0000 Subject: [PATCH 089/140] sisfb: add RAM type detection for XGI Z9 Detect the XGI Z9 RAM type as "documented" by the XGI's xgifb driver. Signed-off-by: Aaro Koskinen Cc: Thomas Winischhofer Signed-off-by: Paul Mundt --- drivers/video/sis/sis_main.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/video/sis/sis_main.c b/drivers/video/sis/sis_main.c index f0c48e84bcdb..de0356788375 100644 --- a/drivers/video/sis/sis_main.c +++ b/drivers/video/sis/sis_main.c @@ -4955,7 +4955,13 @@ sisfb_post_xgi_ramtype(struct sis_video_info *ivideo) v1 = bios[0x1d2]; } if (!(ramtype & 0x80)) { - if (ivideo->chip == XGI_20) { + if (sisfb_xgi_is21(ivideo)) { + SiS_SetRegAND(SISCR, 0xb4, 0xfd); /* GPIO control */ + SiS_SetRegOR(SISCR, 0x4a, 0x80); /* GPIOH EN */ + reg = SiS_GetReg(SISCR, 0x48); + SiS_SetRegOR(SISCR, 0xb4, 0x02); + ramtype = reg & 0x01; /* GPIOH */ + } else if (ivideo->chip == XGI_20) { SiS_SetReg(SISCR, 0x97, v1); reg = SiS_GetReg(SISCR, 0x97); if (reg & 0x10) { From c9982d59c5c877a65fbdef3c875e82eaa95c2505 Mon Sep 17 00:00:00 2001 From: Aaro Koskinen Date: Sun, 13 Feb 2011 22:11:27 +0000 Subject: [PATCH 090/140] sisfb: move XGI POST DDR2 bootup code into subroutines Move DDR2 register setting code into separate subroutines. No changes in functionality. Signed-off-by: Aaro Koskinen Cc: Thomas Winischhofer Signed-off-by: Paul Mundt --- drivers/video/sis/sis_main.c | 139 +++++++++++++++++++++-------------- 1 file changed, 84 insertions(+), 55 deletions(-) diff --git a/drivers/video/sis/sis_main.c b/drivers/video/sis/sis_main.c index de0356788375..9c52d7bbef70 100644 --- a/drivers/video/sis/sis_main.c +++ b/drivers/video/sis/sis_main.c @@ -4941,6 +4941,89 @@ sisfb_post_xgi_setclocks(struct sis_video_info *ivideo, u8 regb) sisfb_post_xgi_delay(ivideo, 0x43); } +static void __devinit +sisfb_post_xgi_ddr2_mrs_default(struct sis_video_info *ivideo, u8 regb) +{ + unsigned char *bios = ivideo->bios_abase; + u8 v1; + + SiS_SetReg(SISSR, 0x28, 0x64); + SiS_SetReg(SISSR, 0x29, 0x63); + sisfb_post_xgi_delay(ivideo, 15); + SiS_SetReg(SISSR, 0x18, 0x00); + SiS_SetReg(SISSR, 0x19, 0x20); + SiS_SetReg(SISSR, 0x16, 0x00); + SiS_SetReg(SISSR, 0x16, 0x80); + SiS_SetReg(SISSR, 0x18, 0xc5); + SiS_SetReg(SISSR, 0x19, 0x23); + SiS_SetReg(SISSR, 0x16, 0x00); + SiS_SetReg(SISSR, 0x16, 0x80); + sisfb_post_xgi_delay(ivideo, 1); + SiS_SetReg(SISCR, 0x97, 0x11); + sisfb_post_xgi_setclocks(ivideo, regb); + sisfb_post_xgi_delay(ivideo, 0x46); + SiS_SetReg(SISSR, 0x18, 0xc5); + SiS_SetReg(SISSR, 0x19, 0x23); + SiS_SetReg(SISSR, 0x16, 0x00); + SiS_SetReg(SISSR, 0x16, 0x80); + sisfb_post_xgi_delay(ivideo, 1); + SiS_SetReg(SISSR, 0x1b, 0x04); + sisfb_post_xgi_delay(ivideo, 1); + SiS_SetReg(SISSR, 0x1b, 0x00); + sisfb_post_xgi_delay(ivideo, 1); + v1 = 0x31; + if (ivideo->haveXGIROM) { + v1 = bios[0xf0]; + } + SiS_SetReg(SISSR, 0x18, v1); + SiS_SetReg(SISSR, 0x19, 0x06); + SiS_SetReg(SISSR, 0x16, 0x04); + SiS_SetReg(SISSR, 0x16, 0x84); + sisfb_post_xgi_delay(ivideo, 1); +} + +static void __devinit +sisfb_post_xgi_ddr2(struct sis_video_info *ivideo, u8 regb) +{ + unsigned char *bios = ivideo->bios_abase; + static const u8 cs158[8] = { + 0x88, 0xaa, 0x48, 0x00, 0x00, 0x00, 0x00, 0x00 + }; + static const u8 cs160[8] = { + 0x44, 0x77, 0x77, 0x00, 0x00, 0x00, 0x00, 0x00 + }; + static const u8 cs168[8] = { + 0x48, 0x78, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00 + }; + u8 reg; + u8 v1; + u8 v2; + u8 v3; + + SiS_SetReg(SISCR, 0x82, 0x77); + SiS_SetReg(SISCR, 0x86, 0x00); + reg = SiS_GetReg(SISCR, 0x86); + SiS_SetReg(SISCR, 0x86, 0x88); + reg = SiS_GetReg(SISCR, 0x86); + v1 = cs168[regb]; v2 = cs160[regb]; v3 = cs158[regb]; + if (ivideo->haveXGIROM) { + v1 = bios[regb + 0x168]; + v2 = bios[regb + 0x160]; + v3 = bios[regb + 0x158]; + } + SiS_SetReg(SISCR, 0x86, v1); + SiS_SetReg(SISCR, 0x82, 0x77); + SiS_SetReg(SISCR, 0x85, 0x00); + reg = SiS_GetReg(SISCR, 0x85); + SiS_SetReg(SISCR, 0x85, 0x88); + reg = SiS_GetReg(SISCR, 0x85); + SiS_SetReg(SISCR, 0x85, v2); + SiS_SetReg(SISCR, 0x82, v3); + SiS_SetReg(SISCR, 0x98, 0x01); + SiS_SetReg(SISCR, 0x9a, 0x02); + sisfb_post_xgi_ddr2_default(ivideo, regb); +} + static u8 __devinit sisfb_post_xgi_ramtype(struct sis_video_info *ivideo) { @@ -5514,61 +5597,7 @@ sisfb_post_xgi(struct pci_dev *pdev) SiS_SetReg(SISSR, 0x1b, 0x00); break; case 1: - SiS_SetReg(SISCR, 0x82, 0x77); - SiS_SetReg(SISCR, 0x86, 0x00); - reg = SiS_GetReg(SISCR, 0x86); - SiS_SetReg(SISCR, 0x86, 0x88); - reg = SiS_GetReg(SISCR, 0x86); - v1 = cs168[regb]; v2 = cs160[regb]; v3 = cs158[regb]; - if(ivideo->haveXGIROM) { - v1 = bios[regb + 0x168]; - v2 = bios[regb + 0x160]; - v3 = bios[regb + 0x158]; - } - SiS_SetReg(SISCR, 0x86, v1); - SiS_SetReg(SISCR, 0x82, 0x77); - SiS_SetReg(SISCR, 0x85, 0x00); - reg = SiS_GetReg(SISCR, 0x85); - SiS_SetReg(SISCR, 0x85, 0x88); - reg = SiS_GetReg(SISCR, 0x85); - SiS_SetReg(SISCR, 0x85, v2); - SiS_SetReg(SISCR, 0x82, v3); - SiS_SetReg(SISCR, 0x98, 0x01); - SiS_SetReg(SISCR, 0x9a, 0x02); - - SiS_SetReg(SISSR, 0x28, 0x64); - SiS_SetReg(SISSR, 0x29, 0x63); - sisfb_post_xgi_delay(ivideo, 15); - SiS_SetReg(SISSR, 0x18, 0x00); - SiS_SetReg(SISSR, 0x19, 0x20); - SiS_SetReg(SISSR, 0x16, 0x00); - SiS_SetReg(SISSR, 0x16, 0x80); - SiS_SetReg(SISSR, 0x18, 0xc5); - SiS_SetReg(SISSR, 0x19, 0x23); - SiS_SetReg(SISSR, 0x16, 0x00); - SiS_SetReg(SISSR, 0x16, 0x80); - sisfb_post_xgi_delay(ivideo, 1); - SiS_SetReg(SISCR, 0x97, 0x11); - sisfb_post_xgi_setclocks(ivideo, regb); - sisfb_post_xgi_delay(ivideo, 0x46); - SiS_SetReg(SISSR, 0x18, 0xc5); - SiS_SetReg(SISSR, 0x19, 0x23); - SiS_SetReg(SISSR, 0x16, 0x00); - SiS_SetReg(SISSR, 0x16, 0x80); - sisfb_post_xgi_delay(ivideo, 1); - SiS_SetReg(SISSR, 0x1b, 0x04); - sisfb_post_xgi_delay(ivideo, 1); - SiS_SetReg(SISSR, 0x1b, 0x00); - sisfb_post_xgi_delay(ivideo, 1); - v1 = 0x31; - if(ivideo->haveXGIROM) { - v1 = bios[0xf0]; - } - SiS_SetReg(SISSR, 0x18, v1); - SiS_SetReg(SISSR, 0x19, 0x06); - SiS_SetReg(SISSR, 0x16, 0x04); - SiS_SetReg(SISSR, 0x16, 0x84); - sisfb_post_xgi_delay(ivideo, 1); + sisfb_post_xgi_ddr2(ivideo, regb); break; default: sisfb_post_xgi_setclocks(ivideo, regb); From 42dea903bf56414aa1eb299412a744b0fd269931 Mon Sep 17 00:00:00 2001 From: Aaro Koskinen Date: Sun, 13 Feb 2011 22:11:28 +0000 Subject: [PATCH 091/140] sisfb: add support for XGI Z9 DDR2 POST Add support for ZGI Z9 DDR2 POST. The init sequence is from XGI's xgifb driver. Tested with ARM board using a PCI card with XGI Z9s and 32 MB DDR2 memory. After a cold reset the POST succeeds. Signed-off-by: Aaro Koskinen Cc: Thomas Winischhofer Signed-off-by: Paul Mundt --- drivers/video/sis/sis_main.c | 77 +++++++++++++++++++++++++++++++----- 1 file changed, 68 insertions(+), 9 deletions(-) diff --git a/drivers/video/sis/sis_main.c b/drivers/video/sis/sis_main.c index 9c52d7bbef70..75259845933d 100644 --- a/drivers/video/sis/sis_main.c +++ b/drivers/video/sis/sis_main.c @@ -4982,6 +4982,48 @@ sisfb_post_xgi_ddr2_mrs_default(struct sis_video_info *ivideo, u8 regb) sisfb_post_xgi_delay(ivideo, 1); } +static void __devinit +sisfb_post_xgi_ddr2_mrs_xg21(struct sis_video_info *ivideo) +{ + sisfb_post_xgi_setclocks(ivideo, 1); + + SiS_SetReg(SISCR, 0x97, 0x11); + sisfb_post_xgi_delay(ivideo, 0x46); + + SiS_SetReg(SISSR, 0x18, 0x00); /* EMRS2 */ + SiS_SetReg(SISSR, 0x19, 0x80); + SiS_SetReg(SISSR, 0x16, 0x05); + SiS_SetReg(SISSR, 0x16, 0x85); + + SiS_SetReg(SISSR, 0x18, 0x00); /* EMRS3 */ + SiS_SetReg(SISSR, 0x19, 0xc0); + SiS_SetReg(SISSR, 0x16, 0x05); + SiS_SetReg(SISSR, 0x16, 0x85); + + SiS_SetReg(SISSR, 0x18, 0x00); /* EMRS1 */ + SiS_SetReg(SISSR, 0x19, 0x40); + SiS_SetReg(SISSR, 0x16, 0x05); + SiS_SetReg(SISSR, 0x16, 0x85); + + SiS_SetReg(SISSR, 0x18, 0x42); /* MRS1 */ + SiS_SetReg(SISSR, 0x19, 0x02); + SiS_SetReg(SISSR, 0x16, 0x05); + SiS_SetReg(SISSR, 0x16, 0x85); + sisfb_post_xgi_delay(ivideo, 1); + + SiS_SetReg(SISSR, 0x1b, 0x04); + sisfb_post_xgi_delay(ivideo, 1); + + SiS_SetReg(SISSR, 0x1b, 0x00); + sisfb_post_xgi_delay(ivideo, 1); + + SiS_SetReg(SISSR, 0x18, 0x42); /* MRS1 */ + SiS_SetReg(SISSR, 0x19, 0x00); + SiS_SetReg(SISSR, 0x16, 0x05); + SiS_SetReg(SISSR, 0x16, 0x85); + sisfb_post_xgi_delay(ivideo, 1); +} + static void __devinit sisfb_post_xgi_ddr2(struct sis_video_info *ivideo, u8 regb) { @@ -5000,6 +5042,7 @@ sisfb_post_xgi_ddr2(struct sis_video_info *ivideo, u8 regb) u8 v2; u8 v3; + SiS_SetReg(SISCR, 0xb0, 0x80); /* DDR2 dual frequency mode */ SiS_SetReg(SISCR, 0x82, 0x77); SiS_SetReg(SISCR, 0x86, 0x00); reg = SiS_GetReg(SISCR, 0x86); @@ -5021,7 +5064,10 @@ sisfb_post_xgi_ddr2(struct sis_video_info *ivideo, u8 regb) SiS_SetReg(SISCR, 0x82, v3); SiS_SetReg(SISCR, 0x98, 0x01); SiS_SetReg(SISCR, 0x9a, 0x02); - sisfb_post_xgi_ddr2_default(ivideo, regb); + if (sisfb_xgi_is21(ivideo)) + sisfb_post_xgi_ddr2_mrs_xg21(ivideo); + else + sisfb_post_xgi_ddr2_mrs_default(ivideo, regb); } static u8 __devinit @@ -5346,9 +5392,23 @@ sisfb_post_xgi(struct pci_dev *pdev) SiS_SetReg(SISCR, 0x77, v1); } - /* RAM type */ - - regb = 0; /* ! */ + /* RAM type: + * + * 0 == DDR1, 1 == DDR2, 2..7 == reserved? + * + * The code seems to written so that regb should equal ramtype, + * however, so far it has been hardcoded to 0. Enable other values only + * on XGI Z9, as it passes the POST, and add a warning for others. + */ + ramtype = sisfb_post_xgi_ramtype(ivideo); + if (!sisfb_xgi_is21(ivideo) && ramtype) { + dev_warn(&pdev->dev, + "RAM type something else than expected: %d\n", + ramtype); + regb = 0; + } else { + regb = ramtype; + } v1 = 0xff; if(ivideo->haveXGIROM) { @@ -5500,7 +5560,10 @@ sisfb_post_xgi(struct pci_dev *pdev) } } - SiS_SetReg(SISSR, 0x17, 0x00); + if (regb == 1) + SiS_SetReg(SISSR, 0x17, 0x80); /* DDR2 */ + else + SiS_SetReg(SISSR, 0x17, 0x00); /* DDR1 */ SiS_SetReg(SISSR, 0x1a, 0x87); if(ivideo->chip == XGI_20) { @@ -5508,10 +5571,6 @@ sisfb_post_xgi(struct pci_dev *pdev) SiS_SetReg(SISSR, 0x1c, 0x00); } - ramtype = sisfb_post_xgi_ramtype(ivideo); - - regb = 0; /* ! */ - switch(ramtype) { case 0: sisfb_post_xgi_setclocks(ivideo, regb); From 1284e49cf186eaa19056e85a76a443d4eca8995d Mon Sep 17 00:00:00 2001 From: David Miller Date: Tue, 11 Jan 2011 23:49:03 +0000 Subject: [PATCH 092/140] svga: Use proper VGA register name macros in svga_wattr. Instead of magic register location constants. Signed-off-by: David S. Miller Signed-off-by: Paul Mundt --- include/linux/svga.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/linux/svga.h b/include/linux/svga.h index c59a51a2b0e7..3fc52cb0bcb4 100644 --- a/include/linux/svga.h +++ b/include/linux/svga.h @@ -69,9 +69,9 @@ struct svga_pll { static inline void svga_wattr(u8 index, u8 data) { - inb(0x3DA); - outb(index, 0x3C0); - outb(data, 0x3C0); + inb(VGA_IS1_RC); + outb(index, VGA_ATT_IW); + outb(data, VGA_ATT_W); } /* Write a value to a sequence register with a mask */ From f6b0cc477de99fe715f1071b13ab822daed9a34f Mon Sep 17 00:00:00 2001 From: David Miller Date: Tue, 11 Jan 2011 23:49:18 +0000 Subject: [PATCH 093/140] svga: Make svga_wattr take an iomem regbase pointer. And use vga_{r,w}(). Signed-off-by: David S. Miller Signed-off-by: Paul Mundt --- drivers/video/s3fb.c | 2 +- drivers/video/svgalib.c | 18 +++++++++--------- include/linux/svga.h | 8 ++++---- 3 files changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/video/s3fb.c b/drivers/video/s3fb.c index 75738a928610..bcbf098a41c7 100644 --- a/drivers/video/s3fb.c +++ b/drivers/video/s3fb.c @@ -552,7 +552,7 @@ static int s3fb_set_par(struct fb_info *info) } vga_wcrt(NULL, 0x3A, 0x35); - svga_wattr(0x33, 0x00); + svga_wattr(par->state.vgabase, 0x33, 0x00); if (info->var.vmode & FB_VMODE_DOUBLE) svga_wcrt_mask(0x09, 0x80, 0x80); diff --git a/drivers/video/svgalib.c b/drivers/video/svgalib.c index fdb45674e2f6..59c99fd4901b 100644 --- a/drivers/video/svgalib.c +++ b/drivers/video/svgalib.c @@ -102,14 +102,14 @@ void svga_set_default_atc_regs(void) /* All standard ATC registers (AR00 - AR14) */ for (count = 0; count <= 0xF; count ++) - svga_wattr(count, count); + svga_wattr(NULL, count, count); - svga_wattr(VGA_ATC_MODE, 0x01); -/* svga_wattr(VGA_ATC_MODE, 0x41); */ - svga_wattr(VGA_ATC_OVERSCAN, 0x00); - svga_wattr(VGA_ATC_PLANE_ENABLE, 0x0F); - svga_wattr(VGA_ATC_PEL, 0x00); - svga_wattr(VGA_ATC_COLOR_PAGE, 0x00); + svga_wattr(NULL, VGA_ATC_MODE, 0x01); +/* svga_wattr(NULL, VGA_ATC_MODE, 0x41); */ + svga_wattr(NULL, VGA_ATC_OVERSCAN, 0x00); + svga_wattr(NULL, VGA_ATC_PLANE_ENABLE, 0x0F); + svga_wattr(NULL, VGA_ATC_PEL, 0x00); + svga_wattr(NULL, VGA_ATC_COLOR_PAGE, 0x00); vga_r(NULL, 0x3DA); vga_w(NULL, VGA_ATT_W, 0x20); @@ -159,8 +159,8 @@ void svga_set_textmode_vga_regs(void) vga_r(NULL, 0x3DA); vga_w(NULL, VGA_ATT_W, 0x00); - svga_wattr(0x10, 0x0C); /* Attribute Mode Control Register - text mode, blinking and line graphics */ - svga_wattr(0x13, 0x08); /* Horizontal Pixel Panning Register */ + svga_wattr(NULL, 0x10, 0x0C); /* Attribute Mode Control Register - text mode, blinking and line graphics */ + svga_wattr(NULL, 0x13, 0x08); /* Horizontal Pixel Panning Register */ vga_r(NULL, 0x3DA); vga_w(NULL, VGA_ATT_W, 0x20); diff --git a/include/linux/svga.h b/include/linux/svga.h index 3fc52cb0bcb4..95d39412a3c2 100644 --- a/include/linux/svga.h +++ b/include/linux/svga.h @@ -67,11 +67,11 @@ struct svga_pll { /* Write a value to the attribute register */ -static inline void svga_wattr(u8 index, u8 data) +static inline void svga_wattr(void __iomem *regbase, u8 index, u8 data) { - inb(VGA_IS1_RC); - outb(index, VGA_ATT_IW); - outb(data, VGA_ATT_W); + vga_r(regbase, VGA_IS1_RC); + vga_w(regbase, VGA_ATT_IW, index); + vga_w(regbase, VGA_ATT_W, data); } /* Write a value to a sequence register with a mask */ From 21da386d0e4c55f6f7482b4637532b942e22b70a Mon Sep 17 00:00:00 2001 From: David Miller Date: Tue, 11 Jan 2011 23:49:34 +0000 Subject: [PATCH 094/140] svga: Make svga_wcrt_multi take an iomem regbase pointer. Signed-off-by: David S. Miller Signed-off-by: Paul Mundt --- drivers/video/arkfb.c | 9 +++++---- drivers/video/s3fb.c | 13 +++++++------ drivers/video/svgalib.c | 32 ++++++++++++++++---------------- drivers/video/vt8623fb.c | 10 ++++++---- include/linux/svga.h | 2 +- 5 files changed, 35 insertions(+), 31 deletions(-) diff --git a/drivers/video/arkfb.c b/drivers/video/arkfb.c index 391ac939f011..a54dbf4c7836 100644 --- a/drivers/video/arkfb.c +++ b/drivers/video/arkfb.c @@ -657,8 +657,8 @@ static int arkfb_set_par(struct fb_info *info) svga_set_default_atc_regs(); svga_set_default_seq_regs(); svga_set_default_crt_regs(); - svga_wcrt_multi(ark_line_compare_regs, 0xFFFFFFFF); - svga_wcrt_multi(ark_start_address_regs, 0); + svga_wcrt_multi(par->state.vgabase, ark_line_compare_regs, 0xFFFFFFFF); + svga_wcrt_multi(par->state.vgabase, ark_start_address_regs, 0); /* ARK specific initialization */ svga_wseq_mask(0x10, 0x1F, 0x1F); /* enable linear framebuffer and full memory access */ @@ -676,7 +676,7 @@ static int arkfb_set_par(struct fb_info *info) /* Set the offset register */ pr_debug("fb%d: offset register : %d\n", info->node, offset_value); - svga_wcrt_multi(ark_offset_regs, offset_value); + svga_wcrt_multi(par->state.vgabase, ark_offset_regs, offset_value); /* fix for hi-res textmode */ svga_wcrt_mask(0x40, 0x08, 0x08); @@ -884,6 +884,7 @@ static int arkfb_blank(int blank_mode, struct fb_info *info) static int arkfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) { + struct arkfb_info *par = info->par; unsigned int offset; /* Calculate the offset */ @@ -897,7 +898,7 @@ static int arkfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info } /* Set the offset */ - svga_wcrt_multi(ark_start_address_regs, offset); + svga_wcrt_multi(par->state.vgabase, ark_start_address_regs, offset); return 0; } diff --git a/drivers/video/s3fb.c b/drivers/video/s3fb.c index bcbf098a41c7..3984dcf7ba67 100644 --- a/drivers/video/s3fb.c +++ b/drivers/video/s3fb.c @@ -518,8 +518,8 @@ static int s3fb_set_par(struct fb_info *info) svga_set_default_atc_regs(); svga_set_default_seq_regs(); svga_set_default_crt_regs(); - svga_wcrt_multi(s3_line_compare_regs, 0xFFFFFFFF); - svga_wcrt_multi(s3_start_address_regs, 0); + svga_wcrt_multi(par->state.vgabase, s3_line_compare_regs, 0xFFFFFFFF); + svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, 0); /* S3 specific initialization */ svga_wcrt_mask(0x58, 0x10, 0x10); /* enable linear framebuffer */ @@ -540,7 +540,7 @@ static int s3fb_set_par(struct fb_info *info) /* Set the offset register */ pr_debug("fb%d: offset register : %d\n", info->node, offset_value); - svga_wcrt_multi(s3_offset_regs, offset_value); + svga_wcrt_multi(par->state.vgabase, s3_offset_regs, offset_value); if (par->chip != CHIP_360_TRIO3D_1X && par->chip != CHIP_362_TRIO3D_2X && @@ -822,8 +822,9 @@ static int s3fb_blank(int blank_mode, struct fb_info *info) /* Pan the display */ -static int s3fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) { - +static int s3fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) +{ + struct s3fb_info *par = info->par; unsigned int offset; /* Calculate the offset */ @@ -837,7 +838,7 @@ static int s3fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) } /* Set the offset */ - svga_wcrt_multi(s3_start_address_regs, offset); + svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, offset); return 0; } diff --git a/drivers/video/svgalib.c b/drivers/video/svgalib.c index 59c99fd4901b..bf3c7a92eeab 100644 --- a/drivers/video/svgalib.c +++ b/drivers/video/svgalib.c @@ -20,12 +20,12 @@ /* Write a CRT register value spread across multiple registers */ -void svga_wcrt_multi(const struct vga_regset *regset, u32 value) { - +void svga_wcrt_multi(void __iomem *regbase, const struct vga_regset *regset, u32 value) +{ u8 regval, bitval, bitnum; while (regset->regnum != VGA_REGSET_END_VAL) { - regval = vga_rcrt(NULL, regset->regnum); + regval = vga_rcrt(regbase, regset->regnum); bitnum = regset->lowbit; while (bitnum <= regset->highbit) { bitval = 1 << bitnum; @@ -34,7 +34,7 @@ void svga_wcrt_multi(const struct vga_regset *regset, u32 value) { bitnum ++; value = value >> 1; } - vga_wcrt(NULL, regset->regnum, regval); + vga_wcrt(regbase, regset->regnum, regval); regset ++; } } @@ -516,62 +516,62 @@ void svga_set_timings(const struct svga_timing_regs *tm, struct fb_var_screeninf value = var->xres + var->left_margin + var->right_margin + var->hsync_len; value = (value * hmul) / hdiv; pr_debug("fb%d: horizontal total : %d\n", node, value); - svga_wcrt_multi(tm->h_total_regs, (value / 8) - 5); + svga_wcrt_multi(NULL, tm->h_total_regs, (value / 8) - 5); value = var->xres; value = (value * hmul) / hdiv; pr_debug("fb%d: horizontal display : %d\n", node, value); - svga_wcrt_multi(tm->h_display_regs, (value / 8) - 1); + svga_wcrt_multi(NULL, tm->h_display_regs, (value / 8) - 1); value = var->xres; value = (value * hmul) / hdiv; pr_debug("fb%d: horizontal blank start: %d\n", node, value); - svga_wcrt_multi(tm->h_blank_start_regs, (value / 8) - 1 + hborder); + svga_wcrt_multi(NULL, tm->h_blank_start_regs, (value / 8) - 1 + hborder); value = var->xres + var->left_margin + var->right_margin + var->hsync_len; value = (value * hmul) / hdiv; pr_debug("fb%d: horizontal blank end : %d\n", node, value); - svga_wcrt_multi(tm->h_blank_end_regs, (value / 8) - 1 - hborder); + svga_wcrt_multi(NULL, tm->h_blank_end_regs, (value / 8) - 1 - hborder); value = var->xres + var->right_margin; value = (value * hmul) / hdiv; pr_debug("fb%d: horizontal sync start : %d\n", node, value); - svga_wcrt_multi(tm->h_sync_start_regs, (value / 8)); + svga_wcrt_multi(NULL, tm->h_sync_start_regs, (value / 8)); value = var->xres + var->right_margin + var->hsync_len; value = (value * hmul) / hdiv; pr_debug("fb%d: horizontal sync end : %d\n", node, value); - svga_wcrt_multi(tm->h_sync_end_regs, (value / 8)); + svga_wcrt_multi(NULL, tm->h_sync_end_regs, (value / 8)); value = var->yres + var->upper_margin + var->lower_margin + var->vsync_len; value = (value * vmul) / vdiv; pr_debug("fb%d: vertical total : %d\n", node, value); - svga_wcrt_multi(tm->v_total_regs, value - 2); + svga_wcrt_multi(NULL, tm->v_total_regs, value - 2); value = var->yres; value = (value * vmul) / vdiv; pr_debug("fb%d: vertical display : %d\n", node, value); - svga_wcrt_multi(tm->v_display_regs, value - 1); + svga_wcrt_multi(NULL, tm->v_display_regs, value - 1); value = var->yres; value = (value * vmul) / vdiv; pr_debug("fb%d: vertical blank start : %d\n", node, value); - svga_wcrt_multi(tm->v_blank_start_regs, value); + svga_wcrt_multi(NULL, tm->v_blank_start_regs, value); value = var->yres + var->upper_margin + var->lower_margin + var->vsync_len; value = (value * vmul) / vdiv; pr_debug("fb%d: vertical blank end : %d\n", node, value); - svga_wcrt_multi(tm->v_blank_end_regs, value - 2); + svga_wcrt_multi(NULL, tm->v_blank_end_regs, value - 2); value = var->yres + var->lower_margin; value = (value * vmul) / vdiv; pr_debug("fb%d: vertical sync start : %d\n", node, value); - svga_wcrt_multi(tm->v_sync_start_regs, value); + svga_wcrt_multi(NULL, tm->v_sync_start_regs, value); value = var->yres + var->lower_margin + var->vsync_len; value = (value * vmul) / vdiv; pr_debug("fb%d: vertical sync end : %d\n", node, value); - svga_wcrt_multi(tm->v_sync_end_regs, value); + svga_wcrt_multi(NULL, tm->v_sync_end_regs, value); /* Set horizontal and vertical sync pulse polarity in misc register */ diff --git a/drivers/video/vt8623fb.c b/drivers/video/vt8623fb.c index a2965ab92cfb..46f8e06a55e8 100644 --- a/drivers/video/vt8623fb.c +++ b/drivers/video/vt8623fb.c @@ -373,6 +373,7 @@ static int vt8623fb_check_var(struct fb_var_screeninfo *var, struct fb_info *inf static int vt8623fb_set_par(struct fb_info *info) { u32 mode, offset_value, fetch_value, screen_size; + struct vt8623fb_info *par = info->par; u32 bpp = info->var.bits_per_pixel; if (bpp != 0) { @@ -428,10 +429,10 @@ static int vt8623fb_set_par(struct fb_info *info) svga_set_default_atc_regs(); svga_set_default_seq_regs(); svga_set_default_crt_regs(); - svga_wcrt_multi(vt8623_line_compare_regs, 0xFFFFFFFF); - svga_wcrt_multi(vt8623_start_address_regs, 0); + svga_wcrt_multi(par->state.vgabase, vt8623_line_compare_regs, 0xFFFFFFFF); + svga_wcrt_multi(par->state.vgabase, vt8623_start_address_regs, 0); - svga_wcrt_multi(vt8623_offset_regs, offset_value); + svga_wcrt_multi(par->state.vgabase, vt8623_offset_regs, offset_value); svga_wseq_multi(vt8623_fetch_count_regs, fetch_value); /* Clear H/V Skew */ @@ -603,6 +604,7 @@ static int vt8623fb_blank(int blank_mode, struct fb_info *info) static int vt8623fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) { + struct vt8623fb_info *par = info->par; unsigned int offset; /* Calculate the offset */ @@ -616,7 +618,7 @@ static int vt8623fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *i } /* Set the offset */ - svga_wcrt_multi(vt8623_start_address_regs, offset); + svga_wcrt_multi(par->state.vgabase, vt8623_start_address_regs, offset); return 0; } diff --git a/include/linux/svga.h b/include/linux/svga.h index 95d39412a3c2..8ca81e0b0a6c 100644 --- a/include/linux/svga.h +++ b/include/linux/svga.h @@ -96,7 +96,7 @@ static inline int svga_primary_device(struct pci_dev *dev) } -void svga_wcrt_multi(const struct vga_regset *regset, u32 value); +void svga_wcrt_multi(void __iomem *regbase, const struct vga_regset *regset, u32 value); void svga_wseq_multi(const struct vga_regset *regset, u32 value); void svga_set_default_gfx_regs(void); From dc6aff3a5d3e4f565cb07cd5f3b6983850971da7 Mon Sep 17 00:00:00 2001 From: David Miller Date: Tue, 11 Jan 2011 23:49:49 +0000 Subject: [PATCH 095/140] svga: Make svga_wseq_multi take an iomem regbase pointer. Signed-off-by: David S. Miller Signed-off-by: Paul Mundt --- drivers/video/svgalib.c | 8 ++++---- drivers/video/vt8623fb.c | 2 +- include/linux/svga.h | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/video/svgalib.c b/drivers/video/svgalib.c index bf3c7a92eeab..ed190aa09653 100644 --- a/drivers/video/svgalib.c +++ b/drivers/video/svgalib.c @@ -40,12 +40,12 @@ void svga_wcrt_multi(void __iomem *regbase, const struct vga_regset *regset, u32 } /* Write a sequencer register value spread across multiple registers */ -void svga_wseq_multi(const struct vga_regset *regset, u32 value) { - +void svga_wseq_multi(void __iomem *regbase, const struct vga_regset *regset, u32 value) +{ u8 regval, bitval, bitnum; while (regset->regnum != VGA_REGSET_END_VAL) { - regval = vga_rseq(NULL, regset->regnum); + regval = vga_rseq(regbase, regset->regnum); bitnum = regset->lowbit; while (bitnum <= regset->highbit) { bitval = 1 << bitnum; @@ -54,7 +54,7 @@ void svga_wseq_multi(const struct vga_regset *regset, u32 value) { bitnum ++; value = value >> 1; } - vga_wseq(NULL, regset->regnum, regval); + vga_wseq(regbase, regset->regnum, regval); regset ++; } } diff --git a/drivers/video/vt8623fb.c b/drivers/video/vt8623fb.c index 46f8e06a55e8..f303ea0341bc 100644 --- a/drivers/video/vt8623fb.c +++ b/drivers/video/vt8623fb.c @@ -433,7 +433,7 @@ static int vt8623fb_set_par(struct fb_info *info) svga_wcrt_multi(par->state.vgabase, vt8623_start_address_regs, 0); svga_wcrt_multi(par->state.vgabase, vt8623_offset_regs, offset_value); - svga_wseq_multi(vt8623_fetch_count_regs, fetch_value); + svga_wseq_multi(par->state.vgabase, vt8623_fetch_count_regs, fetch_value); /* Clear H/V Skew */ svga_wcrt_mask(0x03, 0x00, 0x60); diff --git a/include/linux/svga.h b/include/linux/svga.h index 8ca81e0b0a6c..357e2bdac9aa 100644 --- a/include/linux/svga.h +++ b/include/linux/svga.h @@ -97,7 +97,7 @@ static inline int svga_primary_device(struct pci_dev *dev) void svga_wcrt_multi(void __iomem *regbase, const struct vga_regset *regset, u32 value); -void svga_wseq_multi(const struct vga_regset *regset, u32 value); +void svga_wseq_multi(void __iomem *regbase, const struct vga_regset *regset, u32 value); void svga_set_default_gfx_regs(void); void svga_set_default_atc_regs(void); From e2fade2c146ec718796049104b45267ddbfdf7a1 Mon Sep 17 00:00:00 2001 From: David Miller Date: Tue, 11 Jan 2011 23:50:04 +0000 Subject: [PATCH 096/140] svga: Make svga_set_default_gfx_regs take an iomem regbase pointer. Signed-off-by: David S. Miller Signed-off-by: Paul Mundt --- drivers/video/arkfb.c | 2 +- drivers/video/s3fb.c | 2 +- drivers/video/svgalib.c | 26 +++++++++++++------------- drivers/video/vt8623fb.c | 2 +- include/linux/svga.h | 2 +- 5 files changed, 17 insertions(+), 17 deletions(-) diff --git a/drivers/video/arkfb.c b/drivers/video/arkfb.c index a54dbf4c7836..e09694f58c2c 100644 --- a/drivers/video/arkfb.c +++ b/drivers/video/arkfb.c @@ -653,7 +653,7 @@ static int arkfb_set_par(struct fb_info *info) svga_wcrt_mask(0x17, 0x00, 0x80); /* Set default values */ - svga_set_default_gfx_regs(); + svga_set_default_gfx_regs(par->state.vgabase); svga_set_default_atc_regs(); svga_set_default_seq_regs(); svga_set_default_crt_regs(); diff --git a/drivers/video/s3fb.c b/drivers/video/s3fb.c index 3984dcf7ba67..7e34e5a163c4 100644 --- a/drivers/video/s3fb.c +++ b/drivers/video/s3fb.c @@ -514,7 +514,7 @@ static int s3fb_set_par(struct fb_info *info) svga_wcrt_mask(0x17, 0x00, 0x80); /* Set default values */ - svga_set_default_gfx_regs(); + svga_set_default_gfx_regs(par->state.vgabase); svga_set_default_atc_regs(); svga_set_default_seq_regs(); svga_set_default_crt_regs(); diff --git a/drivers/video/svgalib.c b/drivers/video/svgalib.c index ed190aa09653..25f9f87f73dd 100644 --- a/drivers/video/svgalib.c +++ b/drivers/video/svgalib.c @@ -75,21 +75,21 @@ static unsigned int svga_regset_size(const struct vga_regset *regset) /* Set graphics controller registers to sane values */ -void svga_set_default_gfx_regs(void) +void svga_set_default_gfx_regs(void __iomem *regbase) { /* All standard GFX registers (GR00 - GR08) */ - vga_wgfx(NULL, VGA_GFX_SR_VALUE, 0x00); - vga_wgfx(NULL, VGA_GFX_SR_ENABLE, 0x00); - vga_wgfx(NULL, VGA_GFX_COMPARE_VALUE, 0x00); - vga_wgfx(NULL, VGA_GFX_DATA_ROTATE, 0x00); - vga_wgfx(NULL, VGA_GFX_PLANE_READ, 0x00); - vga_wgfx(NULL, VGA_GFX_MODE, 0x00); -/* vga_wgfx(NULL, VGA_GFX_MODE, 0x20); */ -/* vga_wgfx(NULL, VGA_GFX_MODE, 0x40); */ - vga_wgfx(NULL, VGA_GFX_MISC, 0x05); -/* vga_wgfx(NULL, VGA_GFX_MISC, 0x01); */ - vga_wgfx(NULL, VGA_GFX_COMPARE_MASK, 0x0F); - vga_wgfx(NULL, VGA_GFX_BIT_MASK, 0xFF); + vga_wgfx(regbase, VGA_GFX_SR_VALUE, 0x00); + vga_wgfx(regbase, VGA_GFX_SR_ENABLE, 0x00); + vga_wgfx(regbase, VGA_GFX_COMPARE_VALUE, 0x00); + vga_wgfx(regbase, VGA_GFX_DATA_ROTATE, 0x00); + vga_wgfx(regbase, VGA_GFX_PLANE_READ, 0x00); + vga_wgfx(regbase, VGA_GFX_MODE, 0x00); +/* vga_wgfx(regbase, VGA_GFX_MODE, 0x20); */ +/* vga_wgfx(regbase, VGA_GFX_MODE, 0x40); */ + vga_wgfx(regbase, VGA_GFX_MISC, 0x05); +/* vga_wgfx(regbase, VGA_GFX_MISC, 0x01); */ + vga_wgfx(regbase, VGA_GFX_COMPARE_MASK, 0x0F); + vga_wgfx(regbase, VGA_GFX_BIT_MASK, 0xFF); } /* Set attribute controller registers to sane values */ diff --git a/drivers/video/vt8623fb.c b/drivers/video/vt8623fb.c index f303ea0341bc..ccb4a3e78fda 100644 --- a/drivers/video/vt8623fb.c +++ b/drivers/video/vt8623fb.c @@ -425,7 +425,7 @@ static int vt8623fb_set_par(struct fb_info *info) svga_wcrt_mask(0x17, 0x00, 0x80); /* Set default values */ - svga_set_default_gfx_regs(); + svga_set_default_gfx_regs(par->state.vgabase); svga_set_default_atc_regs(); svga_set_default_seq_regs(); svga_set_default_crt_regs(); diff --git a/include/linux/svga.h b/include/linux/svga.h index 357e2bdac9aa..4591032247f2 100644 --- a/include/linux/svga.h +++ b/include/linux/svga.h @@ -99,7 +99,7 @@ static inline int svga_primary_device(struct pci_dev *dev) void svga_wcrt_multi(void __iomem *regbase, const struct vga_regset *regset, u32 value); void svga_wseq_multi(void __iomem *regbase, const struct vga_regset *regset, u32 value); -void svga_set_default_gfx_regs(void); +void svga_set_default_gfx_regs(void __iomem *regbase); void svga_set_default_atc_regs(void); void svga_set_default_seq_regs(void); void svga_set_default_crt_regs(void); From f51a14dded14457e45b1f026a6af5ca6a51e4502 Mon Sep 17 00:00:00 2001 From: David Miller Date: Tue, 11 Jan 2011 23:50:36 +0000 Subject: [PATCH 097/140] svga: Make svga_set_default_atc_regs take an iomem regbase pointer. Signed-off-by: David S. Miller Signed-off-by: Paul Mundt --- drivers/video/arkfb.c | 2 +- drivers/video/s3fb.c | 2 +- drivers/video/svgalib.c | 24 ++++++++++++------------ drivers/video/vt8623fb.c | 2 +- include/linux/svga.h | 2 +- 5 files changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/video/arkfb.c b/drivers/video/arkfb.c index e09694f58c2c..1028e329c46b 100644 --- a/drivers/video/arkfb.c +++ b/drivers/video/arkfb.c @@ -654,7 +654,7 @@ static int arkfb_set_par(struct fb_info *info) /* Set default values */ svga_set_default_gfx_regs(par->state.vgabase); - svga_set_default_atc_regs(); + svga_set_default_atc_regs(par->state.vgabase); svga_set_default_seq_regs(); svga_set_default_crt_regs(); svga_wcrt_multi(par->state.vgabase, ark_line_compare_regs, 0xFFFFFFFF); diff --git a/drivers/video/s3fb.c b/drivers/video/s3fb.c index 7e34e5a163c4..7073cf904ccd 100644 --- a/drivers/video/s3fb.c +++ b/drivers/video/s3fb.c @@ -515,7 +515,7 @@ static int s3fb_set_par(struct fb_info *info) /* Set default values */ svga_set_default_gfx_regs(par->state.vgabase); - svga_set_default_atc_regs(); + svga_set_default_atc_regs(par->state.vgabase); svga_set_default_seq_regs(); svga_set_default_crt_regs(); svga_wcrt_multi(par->state.vgabase, s3_line_compare_regs, 0xFFFFFFFF); diff --git a/drivers/video/svgalib.c b/drivers/video/svgalib.c index 25f9f87f73dd..8b97359db502 100644 --- a/drivers/video/svgalib.c +++ b/drivers/video/svgalib.c @@ -93,26 +93,26 @@ void svga_set_default_gfx_regs(void __iomem *regbase) } /* Set attribute controller registers to sane values */ -void svga_set_default_atc_regs(void) +void svga_set_default_atc_regs(void __iomem *regbase) { u8 count; - vga_r(NULL, 0x3DA); - vga_w(NULL, VGA_ATT_W, 0x00); + vga_r(regbase, 0x3DA); + vga_w(regbase, VGA_ATT_W, 0x00); /* All standard ATC registers (AR00 - AR14) */ for (count = 0; count <= 0xF; count ++) - svga_wattr(NULL, count, count); + svga_wattr(regbase, count, count); - svga_wattr(NULL, VGA_ATC_MODE, 0x01); -/* svga_wattr(NULL, VGA_ATC_MODE, 0x41); */ - svga_wattr(NULL, VGA_ATC_OVERSCAN, 0x00); - svga_wattr(NULL, VGA_ATC_PLANE_ENABLE, 0x0F); - svga_wattr(NULL, VGA_ATC_PEL, 0x00); - svga_wattr(NULL, VGA_ATC_COLOR_PAGE, 0x00); + svga_wattr(regbase, VGA_ATC_MODE, 0x01); +/* svga_wattr(regbase, VGA_ATC_MODE, 0x41); */ + svga_wattr(regbase, VGA_ATC_OVERSCAN, 0x00); + svga_wattr(regbase, VGA_ATC_PLANE_ENABLE, 0x0F); + svga_wattr(regbase, VGA_ATC_PEL, 0x00); + svga_wattr(regbase, VGA_ATC_COLOR_PAGE, 0x00); - vga_r(NULL, 0x3DA); - vga_w(NULL, VGA_ATT_W, 0x20); + vga_r(regbase, 0x3DA); + vga_w(regbase, VGA_ATT_W, 0x20); } /* Set sequencer registers to sane values */ diff --git a/drivers/video/vt8623fb.c b/drivers/video/vt8623fb.c index ccb4a3e78fda..310af2dc43cd 100644 --- a/drivers/video/vt8623fb.c +++ b/drivers/video/vt8623fb.c @@ -426,7 +426,7 @@ static int vt8623fb_set_par(struct fb_info *info) /* Set default values */ svga_set_default_gfx_regs(par->state.vgabase); - svga_set_default_atc_regs(); + svga_set_default_atc_regs(par->state.vgabase); svga_set_default_seq_regs(); svga_set_default_crt_regs(); svga_wcrt_multi(par->state.vgabase, vt8623_line_compare_regs, 0xFFFFFFFF); diff --git a/include/linux/svga.h b/include/linux/svga.h index 4591032247f2..87a41641caeb 100644 --- a/include/linux/svga.h +++ b/include/linux/svga.h @@ -100,7 +100,7 @@ void svga_wcrt_multi(void __iomem *regbase, const struct vga_regset *regset, u32 void svga_wseq_multi(void __iomem *regbase, const struct vga_regset *regset, u32 value); void svga_set_default_gfx_regs(void __iomem *regbase); -void svga_set_default_atc_regs(void); +void svga_set_default_atc_regs(void __iomem *regbase); void svga_set_default_seq_regs(void); void svga_set_default_crt_regs(void); void svga_set_textmode_vga_regs(void); From a4ade83948e0ffc317b8227d92107271a0acdda5 Mon Sep 17 00:00:00 2001 From: David Miller Date: Tue, 11 Jan 2011 23:50:54 +0000 Subject: [PATCH 098/140] svga: Make svga_set_default_seq_regs take an iomem regbase pointer. Signed-off-by: David S. Miller Signed-off-by: Paul Mundt --- drivers/video/arkfb.c | 2 +- drivers/video/s3fb.c | 2 +- drivers/video/svgalib.c | 12 ++++++------ drivers/video/vt8623fb.c | 2 +- include/linux/svga.h | 2 +- 5 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/video/arkfb.c b/drivers/video/arkfb.c index 1028e329c46b..4cc412126ad3 100644 --- a/drivers/video/arkfb.c +++ b/drivers/video/arkfb.c @@ -655,7 +655,7 @@ static int arkfb_set_par(struct fb_info *info) /* Set default values */ svga_set_default_gfx_regs(par->state.vgabase); svga_set_default_atc_regs(par->state.vgabase); - svga_set_default_seq_regs(); + svga_set_default_seq_regs(par->state.vgabase); svga_set_default_crt_regs(); svga_wcrt_multi(par->state.vgabase, ark_line_compare_regs, 0xFFFFFFFF); svga_wcrt_multi(par->state.vgabase, ark_start_address_regs, 0); diff --git a/drivers/video/s3fb.c b/drivers/video/s3fb.c index 7073cf904ccd..f37c38bbe879 100644 --- a/drivers/video/s3fb.c +++ b/drivers/video/s3fb.c @@ -516,7 +516,7 @@ static int s3fb_set_par(struct fb_info *info) /* Set default values */ svga_set_default_gfx_regs(par->state.vgabase); svga_set_default_atc_regs(par->state.vgabase); - svga_set_default_seq_regs(); + svga_set_default_seq_regs(par->state.vgabase); svga_set_default_crt_regs(); svga_wcrt_multi(par->state.vgabase, s3_line_compare_regs, 0xFFFFFFFF); svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, 0); diff --git a/drivers/video/svgalib.c b/drivers/video/svgalib.c index 8b97359db502..6d3d39feb891 100644 --- a/drivers/video/svgalib.c +++ b/drivers/video/svgalib.c @@ -116,14 +116,14 @@ void svga_set_default_atc_regs(void __iomem *regbase) } /* Set sequencer registers to sane values */ -void svga_set_default_seq_regs(void) +void svga_set_default_seq_regs(void __iomem *regbase) { /* Standard sequencer registers (SR01 - SR04), SR00 is not set */ - vga_wseq(NULL, VGA_SEQ_CLOCK_MODE, VGA_SR01_CHAR_CLK_8DOTS); - vga_wseq(NULL, VGA_SEQ_PLANE_WRITE, VGA_SR02_ALL_PLANES); - vga_wseq(NULL, VGA_SEQ_CHARACTER_MAP, 0x00); -/* vga_wseq(NULL, VGA_SEQ_MEMORY_MODE, VGA_SR04_EXT_MEM | VGA_SR04_SEQ_MODE | VGA_SR04_CHN_4M); */ - vga_wseq(NULL, VGA_SEQ_MEMORY_MODE, VGA_SR04_EXT_MEM | VGA_SR04_SEQ_MODE); + vga_wseq(regbase, VGA_SEQ_CLOCK_MODE, VGA_SR01_CHAR_CLK_8DOTS); + vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, VGA_SR02_ALL_PLANES); + vga_wseq(regbase, VGA_SEQ_CHARACTER_MAP, 0x00); +/* vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, VGA_SR04_EXT_MEM | VGA_SR04_SEQ_MODE | VGA_SR04_CHN_4M); */ + vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, VGA_SR04_EXT_MEM | VGA_SR04_SEQ_MODE); } /* Set CRTC registers to sane values */ diff --git a/drivers/video/vt8623fb.c b/drivers/video/vt8623fb.c index 310af2dc43cd..9de76811200e 100644 --- a/drivers/video/vt8623fb.c +++ b/drivers/video/vt8623fb.c @@ -427,7 +427,7 @@ static int vt8623fb_set_par(struct fb_info *info) /* Set default values */ svga_set_default_gfx_regs(par->state.vgabase); svga_set_default_atc_regs(par->state.vgabase); - svga_set_default_seq_regs(); + svga_set_default_seq_regs(par->state.vgabase); svga_set_default_crt_regs(); svga_wcrt_multi(par->state.vgabase, vt8623_line_compare_regs, 0xFFFFFFFF); svga_wcrt_multi(par->state.vgabase, vt8623_start_address_regs, 0); diff --git a/include/linux/svga.h b/include/linux/svga.h index 87a41641caeb..d31a39844019 100644 --- a/include/linux/svga.h +++ b/include/linux/svga.h @@ -101,7 +101,7 @@ void svga_wseq_multi(void __iomem *regbase, const struct vga_regset *regset, u32 void svga_set_default_gfx_regs(void __iomem *regbase); void svga_set_default_atc_regs(void __iomem *regbase); -void svga_set_default_seq_regs(void); +void svga_set_default_seq_regs(void __iomem *regbase); void svga_set_default_crt_regs(void); void svga_set_textmode_vga_regs(void); From d907ec04cc498e11e039e0fff8eb58cf01e885da Mon Sep 17 00:00:00 2001 From: David Miller Date: Tue, 11 Jan 2011 23:51:08 +0000 Subject: [PATCH 099/140] svga: Make svga_wseq_mask() take an iomem regbase pointer. Signed-off-by: David S. Miller Signed-off-by: Paul Mundt --- drivers/video/arkfb.c | 16 ++++++++------- drivers/video/s3fb.c | 20 ++++++++++--------- drivers/video/svgalib.c | 2 +- drivers/video/vt8623fb.c | 43 +++++++++++++++++++++------------------- include/linux/svga.h | 4 ++-- 5 files changed, 46 insertions(+), 39 deletions(-) diff --git a/drivers/video/arkfb.c b/drivers/video/arkfb.c index 4cc412126ad3..c351b184b1bd 100644 --- a/drivers/video/arkfb.c +++ b/drivers/video/arkfb.c @@ -649,7 +649,7 @@ static int arkfb_set_par(struct fb_info *info) svga_wcrt_mask(0x11, 0x00, 0x80); /* Blank screen and turn off sync */ - svga_wseq_mask(0x01, 0x20, 0x20); + svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); svga_wcrt_mask(0x17, 0x00, 0x80); /* Set default values */ @@ -661,8 +661,8 @@ static int arkfb_set_par(struct fb_info *info) svga_wcrt_multi(par->state.vgabase, ark_start_address_regs, 0); /* ARK specific initialization */ - svga_wseq_mask(0x10, 0x1F, 0x1F); /* enable linear framebuffer and full memory access */ - svga_wseq_mask(0x12, 0x03, 0x03); /* 4 MB linear framebuffer size */ + svga_wseq_mask(par->state.vgabase, 0x10, 0x1F, 0x1F); /* enable linear framebuffer and full memory access */ + svga_wseq_mask(par->state.vgabase, 0x12, 0x03, 0x03); /* 4 MB linear framebuffer size */ vga_wseq(NULL, 0x13, info->fix.smem_start >> 16); vga_wseq(NULL, 0x14, info->fix.smem_start >> 24); @@ -787,7 +787,7 @@ static int arkfb_set_par(struct fb_info *info) memset_io(info->screen_base, 0x00, screen_size); /* Device and screen back on */ svga_wcrt_mask(0x17, 0x80, 0x80); - svga_wseq_mask(0x01, 0x00, 0x20); + svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); return 0; } @@ -857,22 +857,24 @@ static int arkfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, static int arkfb_blank(int blank_mode, struct fb_info *info) { + struct arkfb_info *par = info->par; + switch (blank_mode) { case FB_BLANK_UNBLANK: pr_debug("fb%d: unblank\n", info->node); - svga_wseq_mask(0x01, 0x00, 0x20); + svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); svga_wcrt_mask(0x17, 0x80, 0x80); break; case FB_BLANK_NORMAL: pr_debug("fb%d: blank\n", info->node); - svga_wseq_mask(0x01, 0x20, 0x20); + svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); svga_wcrt_mask(0x17, 0x80, 0x80); break; case FB_BLANK_POWERDOWN: case FB_BLANK_HSYNC_SUSPEND: case FB_BLANK_VSYNC_SUSPEND: pr_debug("fb%d: sync down\n", info->node); - svga_wseq_mask(0x01, 0x20, 0x20); + svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); svga_wcrt_mask(0x17, 0x00, 0x80); break; } diff --git a/drivers/video/s3fb.c b/drivers/video/s3fb.c index f37c38bbe879..efe77b683bfa 100644 --- a/drivers/video/s3fb.c +++ b/drivers/video/s3fb.c @@ -510,7 +510,7 @@ static int s3fb_set_par(struct fb_info *info) svga_wcrt_mask(0x11, 0x00, 0x80); /* Blank screen and turn off sync */ - svga_wseq_mask(0x01, 0x20, 0x20); + svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); svga_wcrt_mask(0x17, 0x00, 0x80); /* Set default values */ @@ -700,8 +700,8 @@ static int s3fb_set_par(struct fb_info *info) } if (par->chip != CHIP_988_VIRGE_VX) { - svga_wseq_mask(0x15, multiplex ? 0x10 : 0x00, 0x10); - svga_wseq_mask(0x18, multiplex ? 0x80 : 0x00, 0x80); + svga_wseq_mask(par->state.vgabase, 0x15, multiplex ? 0x10 : 0x00, 0x10); + svga_wseq_mask(par->state.vgabase, 0x18, multiplex ? 0x80 : 0x00, 0x80); } s3_set_pixclock(info, info->var.pixclock); @@ -718,7 +718,7 @@ static int s3fb_set_par(struct fb_info *info) memset_io(info->screen_base, 0x00, screen_size); /* Device and screen back on */ svga_wcrt_mask(0x17, 0x80, 0x80); - svga_wseq_mask(0x01, 0x00, 0x20); + svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); return 0; } @@ -788,31 +788,33 @@ static int s3fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, static int s3fb_blank(int blank_mode, struct fb_info *info) { + struct s3fb_info *par = info->par; + switch (blank_mode) { case FB_BLANK_UNBLANK: pr_debug("fb%d: unblank\n", info->node); svga_wcrt_mask(0x56, 0x00, 0x06); - svga_wseq_mask(0x01, 0x00, 0x20); + svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); break; case FB_BLANK_NORMAL: pr_debug("fb%d: blank\n", info->node); svga_wcrt_mask(0x56, 0x00, 0x06); - svga_wseq_mask(0x01, 0x20, 0x20); + svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); break; case FB_BLANK_HSYNC_SUSPEND: pr_debug("fb%d: hsync\n", info->node); svga_wcrt_mask(0x56, 0x02, 0x06); - svga_wseq_mask(0x01, 0x20, 0x20); + svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); break; case FB_BLANK_VSYNC_SUSPEND: pr_debug("fb%d: vsync\n", info->node); svga_wcrt_mask(0x56, 0x04, 0x06); - svga_wseq_mask(0x01, 0x20, 0x20); + svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); break; case FB_BLANK_POWERDOWN: pr_debug("fb%d: sync down\n", info->node); svga_wcrt_mask(0x56, 0x06, 0x06); - svga_wseq_mask(0x01, 0x20, 0x20); + svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); break; } diff --git a/drivers/video/svgalib.c b/drivers/video/svgalib.c index 6d3d39feb891..ea7490490de6 100644 --- a/drivers/video/svgalib.c +++ b/drivers/video/svgalib.c @@ -139,7 +139,7 @@ void svga_set_default_crt_regs(void) void svga_set_textmode_vga_regs(void) { - /* svga_wseq_mask(0x1, 0x00, 0x01); */ /* Switch 8/9 pixel per char */ + /* svga_wseq_mask(NULL, 0x1, 0x00, 0x01); */ /* Switch 8/9 pixel per char */ vga_wseq(NULL, VGA_SEQ_MEMORY_MODE, VGA_SR04_EXT_MEM); vga_wseq(NULL, VGA_SEQ_PLANE_WRITE, 0x03); diff --git a/drivers/video/vt8623fb.c b/drivers/video/vt8623fb.c index 9de76811200e..edcfee8bc90b 100644 --- a/drivers/video/vt8623fb.c +++ b/drivers/video/vt8623fb.c @@ -253,6 +253,7 @@ static void vt8623fb_fillrect(struct fb_info *info, const struct fb_fillrect *re static void vt8623_set_pixclock(struct fb_info *info, u32 pixclock) { + struct vt8623fb_info *par = info->par; u16 m, n, r; u8 regval; int rv; @@ -274,8 +275,8 @@ static void vt8623_set_pixclock(struct fb_info *info, u32 pixclock) udelay(1000); /* PLL reset */ - svga_wseq_mask(0x40, 0x02, 0x02); - svga_wseq_mask(0x40, 0x00, 0x02); + svga_wseq_mask(par->state.vgabase, 0x40, 0x02, 0x02); + svga_wseq_mask(par->state.vgabase, 0x40, 0x00, 0x02); } @@ -415,12 +416,12 @@ static int vt8623fb_set_par(struct fb_info *info) info->var.activate = FB_ACTIVATE_NOW; /* Unlock registers */ - svga_wseq_mask(0x10, 0x01, 0x01); + svga_wseq_mask(par->state.vgabase, 0x10, 0x01, 0x01); svga_wcrt_mask(0x11, 0x00, 0x80); svga_wcrt_mask(0x47, 0x00, 0x01); /* Device, screen and sync off */ - svga_wseq_mask(0x01, 0x20, 0x20); + svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); svga_wcrt_mask(0x36, 0x30, 0x30); svga_wcrt_mask(0x17, 0x00, 0x80); @@ -444,12 +445,12 @@ static int vt8623fb_set_par(struct fb_info *info) else svga_wcrt_mask(0x09, 0x00, 0x80); - svga_wseq_mask(0x1E, 0xF0, 0xF0); // DI/DVP bus - svga_wseq_mask(0x2A, 0x0F, 0x0F); // DI/DVP bus - svga_wseq_mask(0x16, 0x08, 0xBF); // FIFO read threshold + svga_wseq_mask(par->state.vgabase, 0x1E, 0xF0, 0xF0); // DI/DVP bus + svga_wseq_mask(par->state.vgabase, 0x2A, 0x0F, 0x0F); // DI/DVP bus + svga_wseq_mask(par->state.vgabase, 0x16, 0x08, 0xBF); // FIFO read threshold vga_wseq(NULL, 0x17, 0x1F); // FIFO depth vga_wseq(NULL, 0x18, 0x4E); - svga_wseq_mask(0x1A, 0x08, 0x08); // enable MMIO ? + svga_wseq_mask(par->state.vgabase, 0x1A, 0x08, 0x08); // enable MMIO ? vga_wcrt(NULL, 0x32, 0x00); vga_wcrt(NULL, 0x34, 0x00); @@ -466,31 +467,31 @@ static int vt8623fb_set_par(struct fb_info *info) case 0: pr_debug("fb%d: text mode\n", info->node); svga_set_textmode_vga_regs(); - svga_wseq_mask(0x15, 0x00, 0xFE); + svga_wseq_mask(par->state.vgabase, 0x15, 0x00, 0xFE); svga_wcrt_mask(0x11, 0x60, 0x70); break; case 1: pr_debug("fb%d: 4 bit pseudocolor\n", info->node); vga_wgfx(NULL, VGA_GFX_MODE, 0x40); - svga_wseq_mask(0x15, 0x20, 0xFE); + svga_wseq_mask(par->state.vgabase, 0x15, 0x20, 0xFE); svga_wcrt_mask(0x11, 0x00, 0x70); break; case 2: pr_debug("fb%d: 4 bit pseudocolor, planar\n", info->node); - svga_wseq_mask(0x15, 0x00, 0xFE); + svga_wseq_mask(par->state.vgabase, 0x15, 0x00, 0xFE); svga_wcrt_mask(0x11, 0x00, 0x70); break; case 3: pr_debug("fb%d: 8 bit pseudocolor\n", info->node); - svga_wseq_mask(0x15, 0x22, 0xFE); + svga_wseq_mask(par->state.vgabase, 0x15, 0x22, 0xFE); break; case 4: pr_debug("fb%d: 5/6/5 truecolor\n", info->node); - svga_wseq_mask(0x15, 0xB6, 0xFE); + svga_wseq_mask(par->state.vgabase, 0x15, 0xB6, 0xFE); break; case 5: pr_debug("fb%d: 8/8/8 truecolor\n", info->node); - svga_wseq_mask(0x15, 0xAE, 0xFE); + svga_wseq_mask(par->state.vgabase, 0x15, 0xAE, 0xFE); break; default: printk(KERN_ERR "vt8623fb: unsupported mode - bug\n"); @@ -507,7 +508,7 @@ static int vt8623fb_set_par(struct fb_info *info) /* Device and screen back on */ svga_wcrt_mask(0x17, 0x80, 0x80); svga_wcrt_mask(0x36, 0x00, 0x30); - svga_wseq_mask(0x01, 0x00, 0x20); + svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); return 0; } @@ -570,31 +571,33 @@ static int vt8623fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, static int vt8623fb_blank(int blank_mode, struct fb_info *info) { + struct vt8623fb_info *par = info->par; + switch (blank_mode) { case FB_BLANK_UNBLANK: pr_debug("fb%d: unblank\n", info->node); svga_wcrt_mask(0x36, 0x00, 0x30); - svga_wseq_mask(0x01, 0x00, 0x20); + svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); break; case FB_BLANK_NORMAL: pr_debug("fb%d: blank\n", info->node); svga_wcrt_mask(0x36, 0x00, 0x30); - svga_wseq_mask(0x01, 0x20, 0x20); + svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); break; case FB_BLANK_HSYNC_SUSPEND: pr_debug("fb%d: DPMS standby (hsync off)\n", info->node); svga_wcrt_mask(0x36, 0x10, 0x30); - svga_wseq_mask(0x01, 0x20, 0x20); + svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); break; case FB_BLANK_VSYNC_SUSPEND: pr_debug("fb%d: DPMS suspend (vsync off)\n", info->node); svga_wcrt_mask(0x36, 0x20, 0x30); - svga_wseq_mask(0x01, 0x20, 0x20); + svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); break; case FB_BLANK_POWERDOWN: pr_debug("fb%d: DPMS off (no sync)\n", info->node); svga_wcrt_mask(0x36, 0x30, 0x30); - svga_wseq_mask(0x01, 0x20, 0x20); + svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); break; } diff --git a/include/linux/svga.h b/include/linux/svga.h index d31a39844019..93f7777b268a 100644 --- a/include/linux/svga.h +++ b/include/linux/svga.h @@ -76,9 +76,9 @@ static inline void svga_wattr(void __iomem *regbase, u8 index, u8 data) /* Write a value to a sequence register with a mask */ -static inline void svga_wseq_mask(u8 index, u8 data, u8 mask) +static inline void svga_wseq_mask(void __iomem *regbase, u8 index, u8 data, u8 mask) { - vga_wseq(NULL, index, (data & mask) | (vga_rseq(NULL, index) & ~mask)); + vga_wseq(regbase, index, (data & mask) | (vga_rseq(regbase, index) & ~mask)); } /* Write a value to a CRT register with a mask */ From ea770789dce2d27afab39c3891a475624acbd82f Mon Sep 17 00:00:00 2001 From: David Miller Date: Tue, 11 Jan 2011 23:51:26 +0000 Subject: [PATCH 100/140] svga: Make svga_wcrt_mask() take an iomem regbase pointer. Signed-off-by: David S. Miller Signed-off-by: Paul Mundt --- drivers/video/arkfb.c | 40 ++++++++-------- drivers/video/s3fb.c | 98 ++++++++++++++++++++-------------------- drivers/video/svgalib.c | 8 ++-- drivers/video/vt8623fb.c | 36 +++++++-------- include/linux/svga.h | 4 +- 5 files changed, 93 insertions(+), 93 deletions(-) diff --git a/drivers/video/arkfb.c b/drivers/video/arkfb.c index c351b184b1bd..f24151e01da3 100644 --- a/drivers/video/arkfb.c +++ b/drivers/video/arkfb.c @@ -646,11 +646,11 @@ static int arkfb_set_par(struct fb_info *info) info->var.activate = FB_ACTIVATE_NOW; /* Unlock registers */ - svga_wcrt_mask(0x11, 0x00, 0x80); + svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80); /* Blank screen and turn off sync */ svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); - svga_wcrt_mask(0x17, 0x00, 0x80); + svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80); /* Set default values */ svga_set_default_gfx_regs(par->state.vgabase); @@ -679,17 +679,17 @@ static int arkfb_set_par(struct fb_info *info) svga_wcrt_multi(par->state.vgabase, ark_offset_regs, offset_value); /* fix for hi-res textmode */ - svga_wcrt_mask(0x40, 0x08, 0x08); + svga_wcrt_mask(par->state.vgabase, 0x40, 0x08, 0x08); if (info->var.vmode & FB_VMODE_DOUBLE) - svga_wcrt_mask(0x09, 0x80, 0x80); + svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80); else - svga_wcrt_mask(0x09, 0x00, 0x80); + svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80); if (info->var.vmode & FB_VMODE_INTERLACED) - svga_wcrt_mask(0x44, 0x04, 0x04); + svga_wcrt_mask(par->state.vgabase, 0x44, 0x04, 0x04); else - svga_wcrt_mask(0x44, 0x00, 0x04); + svga_wcrt_mask(par->state.vgabase, 0x44, 0x00, 0x04); hmul = 1; hdiv = 1; @@ -702,7 +702,7 @@ static int arkfb_set_par(struct fb_info *info) svga_set_textmode_vga_regs(); vga_wseq(NULL, 0x11, 0x10); /* basic VGA mode */ - svga_wcrt_mask(0x46, 0x00, 0x04); /* 8bit pixel path */ + svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */ dac_set_mode(par->dac, DAC_PSEUDO8_8); break; @@ -711,14 +711,14 @@ static int arkfb_set_par(struct fb_info *info) vga_wgfx(NULL, VGA_GFX_MODE, 0x40); vga_wseq(NULL, 0x11, 0x10); /* basic VGA mode */ - svga_wcrt_mask(0x46, 0x00, 0x04); /* 8bit pixel path */ + svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */ dac_set_mode(par->dac, DAC_PSEUDO8_8); break; case 2: pr_debug("fb%d: 4 bit pseudocolor, planar\n", info->node); vga_wseq(NULL, 0x11, 0x10); /* basic VGA mode */ - svga_wcrt_mask(0x46, 0x00, 0x04); /* 8bit pixel path */ + svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */ dac_set_mode(par->dac, DAC_PSEUDO8_8); break; case 3: @@ -728,11 +728,11 @@ static int arkfb_set_par(struct fb_info *info) if (info->var.pixclock > 20000) { pr_debug("fb%d: not using multiplex\n", info->node); - svga_wcrt_mask(0x46, 0x00, 0x04); /* 8bit pixel path */ + svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */ dac_set_mode(par->dac, DAC_PSEUDO8_8); } else { pr_debug("fb%d: using multiplex\n", info->node); - svga_wcrt_mask(0x46, 0x04, 0x04); /* 16bit pixel path */ + svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */ dac_set_mode(par->dac, DAC_PSEUDO8_16); hdiv = 2; } @@ -741,21 +741,21 @@ static int arkfb_set_par(struct fb_info *info) pr_debug("fb%d: 5/5/5 truecolor\n", info->node); vga_wseq(NULL, 0x11, 0x1A); /* 16bpp accel mode */ - svga_wcrt_mask(0x46, 0x04, 0x04); /* 16bit pixel path */ + svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */ dac_set_mode(par->dac, DAC_RGB1555_16); break; case 5: pr_debug("fb%d: 5/6/5 truecolor\n", info->node); vga_wseq(NULL, 0x11, 0x1A); /* 16bpp accel mode */ - svga_wcrt_mask(0x46, 0x04, 0x04); /* 16bit pixel path */ + svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */ dac_set_mode(par->dac, DAC_RGB0565_16); break; case 6: pr_debug("fb%d: 8/8/8 truecolor\n", info->node); vga_wseq(NULL, 0x11, 0x16); /* 8bpp accel mode ??? */ - svga_wcrt_mask(0x46, 0x04, 0x04); /* 16bit pixel path */ + svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */ dac_set_mode(par->dac, DAC_RGB0888_16); hmul = 3; hdiv = 2; @@ -764,7 +764,7 @@ static int arkfb_set_par(struct fb_info *info) pr_debug("fb%d: 8/8/8/8 truecolor\n", info->node); vga_wseq(NULL, 0x11, 0x1E); /* 32bpp accel mode */ - svga_wcrt_mask(0x46, 0x04, 0x04); /* 16bit pixel path */ + svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */ dac_set_mode(par->dac, DAC_RGB8888_16); hmul = 2; break; @@ -786,7 +786,7 @@ static int arkfb_set_par(struct fb_info *info) memset_io(info->screen_base, 0x00, screen_size); /* Device and screen back on */ - svga_wcrt_mask(0x17, 0x80, 0x80); + svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80); svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); return 0; @@ -863,19 +863,19 @@ static int arkfb_blank(int blank_mode, struct fb_info *info) case FB_BLANK_UNBLANK: pr_debug("fb%d: unblank\n", info->node); svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); - svga_wcrt_mask(0x17, 0x80, 0x80); + svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80); break; case FB_BLANK_NORMAL: pr_debug("fb%d: blank\n", info->node); svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); - svga_wcrt_mask(0x17, 0x80, 0x80); + svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80); break; case FB_BLANK_POWERDOWN: case FB_BLANK_HSYNC_SUSPEND: case FB_BLANK_VSYNC_SUSPEND: pr_debug("fb%d: sync down\n", info->node); svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); - svga_wcrt_mask(0x17, 0x00, 0x80); + svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80); break; } return 0; diff --git a/drivers/video/s3fb.c b/drivers/video/s3fb.c index efe77b683bfa..ece99f2044f4 100644 --- a/drivers/video/s3fb.c +++ b/drivers/video/s3fb.c @@ -507,11 +507,11 @@ static int s3fb_set_par(struct fb_info *info) vga_wcrt(NULL, 0x38, 0x48); vga_wcrt(NULL, 0x39, 0xA5); vga_wseq(NULL, 0x08, 0x06); - svga_wcrt_mask(0x11, 0x00, 0x80); + svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80); /* Blank screen and turn off sync */ svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); - svga_wcrt_mask(0x17, 0x00, 0x80); + svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80); /* Set default values */ svga_set_default_gfx_regs(par->state.vgabase); @@ -522,20 +522,20 @@ static int s3fb_set_par(struct fb_info *info) svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, 0); /* S3 specific initialization */ - svga_wcrt_mask(0x58, 0x10, 0x10); /* enable linear framebuffer */ - svga_wcrt_mask(0x31, 0x08, 0x08); /* enable sequencer access to framebuffer above 256 kB */ + svga_wcrt_mask(par->state.vgabase, 0x58, 0x10, 0x10); /* enable linear framebuffer */ + svga_wcrt_mask(par->state.vgabase, 0x31, 0x08, 0x08); /* enable sequencer access to framebuffer above 256 kB */ -/* svga_wcrt_mask(0x33, 0x08, 0x08); */ /* DDR ? */ -/* svga_wcrt_mask(0x43, 0x01, 0x01); */ /* DDR ? */ - svga_wcrt_mask(0x33, 0x00, 0x08); /* no DDR ? */ - svga_wcrt_mask(0x43, 0x00, 0x01); /* no DDR ? */ +/* svga_wcrt_mask(par->state.vgabase, 0x33, 0x08, 0x08); */ /* DDR ? */ +/* svga_wcrt_mask(par->state.vgabase, 0x43, 0x01, 0x01); */ /* DDR ? */ + svga_wcrt_mask(par->state.vgabase, 0x33, 0x00, 0x08); /* no DDR ? */ + svga_wcrt_mask(par->state.vgabase, 0x43, 0x00, 0x01); /* no DDR ? */ - svga_wcrt_mask(0x5D, 0x00, 0x28); /* Clear strange HSlen bits */ + svga_wcrt_mask(par->state.vgabase, 0x5D, 0x00, 0x28); /* Clear strange HSlen bits */ -/* svga_wcrt_mask(0x58, 0x03, 0x03); */ +/* svga_wcrt_mask(par->state.vgabase, 0x58, 0x03, 0x03); */ -/* svga_wcrt_mask(0x53, 0x12, 0x13); */ /* enable MMIO */ -/* svga_wcrt_mask(0x40, 0x08, 0x08); */ /* enable write buffer */ +/* svga_wcrt_mask(par->state.vgabase, 0x53, 0x12, 0x13); */ /* enable MMIO */ +/* svga_wcrt_mask(par->state.vgabase, 0x40, 0x08, 0x08); */ /* enable write buffer */ /* Set the offset register */ @@ -555,19 +555,19 @@ static int s3fb_set_par(struct fb_info *info) svga_wattr(par->state.vgabase, 0x33, 0x00); if (info->var.vmode & FB_VMODE_DOUBLE) - svga_wcrt_mask(0x09, 0x80, 0x80); + svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80); else - svga_wcrt_mask(0x09, 0x00, 0x80); + svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80); if (info->var.vmode & FB_VMODE_INTERLACED) - svga_wcrt_mask(0x42, 0x20, 0x20); + svga_wcrt_mask(par->state.vgabase, 0x42, 0x20, 0x20); else - svga_wcrt_mask(0x42, 0x00, 0x20); + svga_wcrt_mask(par->state.vgabase, 0x42, 0x00, 0x20); /* Disable hardware graphics cursor */ - svga_wcrt_mask(0x45, 0x00, 0x01); + svga_wcrt_mask(par->state.vgabase, 0x45, 0x00, 0x01); /* Disable Streams engine */ - svga_wcrt_mask(0x67, 0x00, 0x0C); + svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0x0C); mode = svga_match_format(s3fb_formats, &(info->var), &(info->fix)); @@ -596,7 +596,7 @@ static int s3fb_set_par(struct fb_info *info) vga_wcrt(NULL, 0x66, 0x81); } - svga_wcrt_mask(0x31, 0x00, 0x40); + svga_wcrt_mask(par->state.vgabase, 0x31, 0x00, 0x40); multiplex = 0; hmul = 1; @@ -607,15 +607,15 @@ static int s3fb_set_par(struct fb_info *info) svga_set_textmode_vga_regs(); /* Set additional registers like in 8-bit mode */ - svga_wcrt_mask(0x50, 0x00, 0x30); - svga_wcrt_mask(0x67, 0x00, 0xF0); + svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); + svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); /* Disable enhanced mode */ - svga_wcrt_mask(0x3A, 0x00, 0x30); + svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); if (fasttext) { pr_debug("fb%d: high speed text mode set\n", info->node); - svga_wcrt_mask(0x31, 0x40, 0x40); + svga_wcrt_mask(par->state.vgabase, 0x31, 0x40, 0x40); } break; case 1: @@ -623,32 +623,32 @@ static int s3fb_set_par(struct fb_info *info) vga_wgfx(NULL, VGA_GFX_MODE, 0x40); /* Set additional registers like in 8-bit mode */ - svga_wcrt_mask(0x50, 0x00, 0x30); - svga_wcrt_mask(0x67, 0x00, 0xF0); + svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); + svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); /* disable enhanced mode */ - svga_wcrt_mask(0x3A, 0x00, 0x30); + svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); break; case 2: pr_debug("fb%d: 4 bit pseudocolor, planar\n", info->node); /* Set additional registers like in 8-bit mode */ - svga_wcrt_mask(0x50, 0x00, 0x30); - svga_wcrt_mask(0x67, 0x00, 0xF0); + svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); + svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); /* disable enhanced mode */ - svga_wcrt_mask(0x3A, 0x00, 0x30); + svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); break; case 3: pr_debug("fb%d: 8 bit pseudocolor\n", info->node); - svga_wcrt_mask(0x50, 0x00, 0x30); + svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); if (info->var.pixclock > 20000 || par->chip == CHIP_360_TRIO3D_1X || par->chip == CHIP_362_TRIO3D_2X || par->chip == CHIP_368_TRIO3D_2X) - svga_wcrt_mask(0x67, 0x00, 0xF0); + svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); else { - svga_wcrt_mask(0x67, 0x10, 0xF0); + svga_wcrt_mask(par->state.vgabase, 0x67, 0x10, 0xF0); multiplex = 1; } break; @@ -656,12 +656,12 @@ static int s3fb_set_par(struct fb_info *info) pr_debug("fb%d: 5/5/5 truecolor\n", info->node); if (par->chip == CHIP_988_VIRGE_VX) { if (info->var.pixclock > 20000) - svga_wcrt_mask(0x67, 0x20, 0xF0); + svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0); else - svga_wcrt_mask(0x67, 0x30, 0xF0); + svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); } else { - svga_wcrt_mask(0x50, 0x10, 0x30); - svga_wcrt_mask(0x67, 0x30, 0xF0); + svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); + svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); if (par->chip != CHIP_360_TRIO3D_1X && par->chip != CHIP_362_TRIO3D_2X && par->chip != CHIP_368_TRIO3D_2X) @@ -672,12 +672,12 @@ static int s3fb_set_par(struct fb_info *info) pr_debug("fb%d: 5/6/5 truecolor\n", info->node); if (par->chip == CHIP_988_VIRGE_VX) { if (info->var.pixclock > 20000) - svga_wcrt_mask(0x67, 0x40, 0xF0); + svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0); else - svga_wcrt_mask(0x67, 0x50, 0xF0); + svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); } else { - svga_wcrt_mask(0x50, 0x10, 0x30); - svga_wcrt_mask(0x67, 0x50, 0xF0); + svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); + svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); if (par->chip != CHIP_360_TRIO3D_1X && par->chip != CHIP_362_TRIO3D_2X && par->chip != CHIP_368_TRIO3D_2X) @@ -687,12 +687,12 @@ static int s3fb_set_par(struct fb_info *info) case 6: /* VIRGE VX case */ pr_debug("fb%d: 8/8/8 truecolor\n", info->node); - svga_wcrt_mask(0x67, 0xD0, 0xF0); + svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0); break; case 7: pr_debug("fb%d: 8/8/8/8 truecolor\n", info->node); - svga_wcrt_mask(0x50, 0x30, 0x30); - svga_wcrt_mask(0x67, 0xD0, 0xF0); + svga_wcrt_mask(par->state.vgabase, 0x50, 0x30, 0x30); + svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0); break; default: printk(KERN_ERR "fb%d: unsupported mode - bug\n", info->node); @@ -717,7 +717,7 @@ static int s3fb_set_par(struct fb_info *info) memset_io(info->screen_base, 0x00, screen_size); /* Device and screen back on */ - svga_wcrt_mask(0x17, 0x80, 0x80); + svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80); svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); return 0; @@ -793,27 +793,27 @@ static int s3fb_blank(int blank_mode, struct fb_info *info) switch (blank_mode) { case FB_BLANK_UNBLANK: pr_debug("fb%d: unblank\n", info->node); - svga_wcrt_mask(0x56, 0x00, 0x06); + svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06); svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); break; case FB_BLANK_NORMAL: pr_debug("fb%d: blank\n", info->node); - svga_wcrt_mask(0x56, 0x00, 0x06); + svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06); svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); break; case FB_BLANK_HSYNC_SUSPEND: pr_debug("fb%d: hsync\n", info->node); - svga_wcrt_mask(0x56, 0x02, 0x06); + svga_wcrt_mask(par->state.vgabase, 0x56, 0x02, 0x06); svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); break; case FB_BLANK_VSYNC_SUSPEND: pr_debug("fb%d: vsync\n", info->node); - svga_wcrt_mask(0x56, 0x04, 0x06); + svga_wcrt_mask(par->state.vgabase, 0x56, 0x04, 0x06); svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); break; case FB_BLANK_POWERDOWN: pr_debug("fb%d: sync down\n", info->node); - svga_wcrt_mask(0x56, 0x06, 0x06); + svga_wcrt_mask(par->state.vgabase, 0x56, 0x06, 0x06); svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); break; } diff --git a/drivers/video/svgalib.c b/drivers/video/svgalib.c index ea7490490de6..3d07287e9322 100644 --- a/drivers/video/svgalib.c +++ b/drivers/video/svgalib.c @@ -130,9 +130,9 @@ void svga_set_default_seq_regs(void __iomem *regbase) void svga_set_default_crt_regs(void) { /* Standard CRT registers CR03 CR08 CR09 CR14 CR17 */ - svga_wcrt_mask(0x03, 0x80, 0x80); /* Enable vertical retrace EVRA */ + svga_wcrt_mask(NULL, 0x03, 0x80, 0x80); /* Enable vertical retrace EVRA */ vga_wcrt(NULL, VGA_CRTC_PRESET_ROW, 0); - svga_wcrt_mask(VGA_CRTC_MAX_SCAN, 0, 0x1F); + svga_wcrt_mask(NULL, VGA_CRTC_MAX_SCAN, 0, 0x1F); vga_wcrt(NULL, VGA_CRTC_UNDERLINE, 0); vga_wcrt(NULL, VGA_CRTC_MODE, 0xE3); } @@ -145,7 +145,7 @@ void svga_set_textmode_vga_regs(void) vga_wcrt(NULL, VGA_CRTC_MAX_SCAN, 0x0f); /* 0x4f */ vga_wcrt(NULL, VGA_CRTC_UNDERLINE, 0x1f); - svga_wcrt_mask(VGA_CRTC_MODE, 0x23, 0x7f); + svga_wcrt_mask(NULL, VGA_CRTC_MODE, 0x23, 0x7f); vga_wcrt(NULL, VGA_CRTC_CURSOR_START, 0x0d); vga_wcrt(NULL, VGA_CRTC_CURSOR_END, 0x0e); @@ -310,7 +310,7 @@ void svga_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor) if (! cursor -> mode) return; - svga_wcrt_mask(0x0A, 0x20, 0x20); /* disable cursor */ + svga_wcrt_mask(NULL, 0x0A, 0x20, 0x20); /* disable cursor */ if (cursor -> shape == FB_TILE_CURSOR_NONE) return; diff --git a/drivers/video/vt8623fb.c b/drivers/video/vt8623fb.c index edcfee8bc90b..bc54b57db985 100644 --- a/drivers/video/vt8623fb.c +++ b/drivers/video/vt8623fb.c @@ -417,13 +417,13 @@ static int vt8623fb_set_par(struct fb_info *info) /* Unlock registers */ svga_wseq_mask(par->state.vgabase, 0x10, 0x01, 0x01); - svga_wcrt_mask(0x11, 0x00, 0x80); - svga_wcrt_mask(0x47, 0x00, 0x01); + svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80); + svga_wcrt_mask(par->state.vgabase, 0x47, 0x00, 0x01); /* Device, screen and sync off */ svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); - svga_wcrt_mask(0x36, 0x30, 0x30); - svga_wcrt_mask(0x17, 0x00, 0x80); + svga_wcrt_mask(par->state.vgabase, 0x36, 0x30, 0x30); + svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80); /* Set default values */ svga_set_default_gfx_regs(par->state.vgabase); @@ -437,13 +437,13 @@ static int vt8623fb_set_par(struct fb_info *info) svga_wseq_multi(par->state.vgabase, vt8623_fetch_count_regs, fetch_value); /* Clear H/V Skew */ - svga_wcrt_mask(0x03, 0x00, 0x60); - svga_wcrt_mask(0x05, 0x00, 0x60); + svga_wcrt_mask(par->state.vgabase, 0x03, 0x00, 0x60); + svga_wcrt_mask(par->state.vgabase, 0x05, 0x00, 0x60); if (info->var.vmode & FB_VMODE_DOUBLE) - svga_wcrt_mask(0x09, 0x80, 0x80); + svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80); else - svga_wcrt_mask(0x09, 0x00, 0x80); + svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80); svga_wseq_mask(par->state.vgabase, 0x1E, 0xF0, 0xF0); // DI/DVP bus svga_wseq_mask(par->state.vgabase, 0x2A, 0x0F, 0x0F); // DI/DVP bus @@ -468,18 +468,18 @@ static int vt8623fb_set_par(struct fb_info *info) pr_debug("fb%d: text mode\n", info->node); svga_set_textmode_vga_regs(); svga_wseq_mask(par->state.vgabase, 0x15, 0x00, 0xFE); - svga_wcrt_mask(0x11, 0x60, 0x70); + svga_wcrt_mask(par->state.vgabase, 0x11, 0x60, 0x70); break; case 1: pr_debug("fb%d: 4 bit pseudocolor\n", info->node); vga_wgfx(NULL, VGA_GFX_MODE, 0x40); svga_wseq_mask(par->state.vgabase, 0x15, 0x20, 0xFE); - svga_wcrt_mask(0x11, 0x00, 0x70); + svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x70); break; case 2: pr_debug("fb%d: 4 bit pseudocolor, planar\n", info->node); svga_wseq_mask(par->state.vgabase, 0x15, 0x00, 0xFE); - svga_wcrt_mask(0x11, 0x00, 0x70); + svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x70); break; case 3: pr_debug("fb%d: 8 bit pseudocolor\n", info->node); @@ -506,8 +506,8 @@ static int vt8623fb_set_par(struct fb_info *info) memset_io(info->screen_base, 0x00, screen_size); /* Device and screen back on */ - svga_wcrt_mask(0x17, 0x80, 0x80); - svga_wcrt_mask(0x36, 0x00, 0x30); + svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80); + svga_wcrt_mask(par->state.vgabase, 0x36, 0x00, 0x30); svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); return 0; @@ -576,27 +576,27 @@ static int vt8623fb_blank(int blank_mode, struct fb_info *info) switch (blank_mode) { case FB_BLANK_UNBLANK: pr_debug("fb%d: unblank\n", info->node); - svga_wcrt_mask(0x36, 0x00, 0x30); + svga_wcrt_mask(par->state.vgabase, 0x36, 0x00, 0x30); svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); break; case FB_BLANK_NORMAL: pr_debug("fb%d: blank\n", info->node); - svga_wcrt_mask(0x36, 0x00, 0x30); + svga_wcrt_mask(par->state.vgabase, 0x36, 0x00, 0x30); svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); break; case FB_BLANK_HSYNC_SUSPEND: pr_debug("fb%d: DPMS standby (hsync off)\n", info->node); - svga_wcrt_mask(0x36, 0x10, 0x30); + svga_wcrt_mask(par->state.vgabase, 0x36, 0x10, 0x30); svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); break; case FB_BLANK_VSYNC_SUSPEND: pr_debug("fb%d: DPMS suspend (vsync off)\n", info->node); - svga_wcrt_mask(0x36, 0x20, 0x30); + svga_wcrt_mask(par->state.vgabase, 0x36, 0x20, 0x30); svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); break; case FB_BLANK_POWERDOWN: pr_debug("fb%d: DPMS off (no sync)\n", info->node); - svga_wcrt_mask(0x36, 0x30, 0x30); + svga_wcrt_mask(par->state.vgabase, 0x36, 0x30, 0x30); svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); break; } diff --git a/include/linux/svga.h b/include/linux/svga.h index 93f7777b268a..5c5b41bddee4 100644 --- a/include/linux/svga.h +++ b/include/linux/svga.h @@ -83,9 +83,9 @@ static inline void svga_wseq_mask(void __iomem *regbase, u8 index, u8 data, u8 m /* Write a value to a CRT register with a mask */ -static inline void svga_wcrt_mask(u8 index, u8 data, u8 mask) +static inline void svga_wcrt_mask(void __iomem *regbase, u8 index, u8 data, u8 mask) { - vga_wcrt(NULL, index, (data & mask) | (vga_rcrt(NULL, index) & ~mask)); + vga_wcrt(regbase, index, (data & mask) | (vga_rcrt(regbase, index) & ~mask)); } static inline int svga_primary_device(struct pci_dev *dev) From 1d28fcadb0e277844ebffb528cdfd25d44591035 Mon Sep 17 00:00:00 2001 From: David Miller Date: Tue, 11 Jan 2011 23:51:41 +0000 Subject: [PATCH 101/140] svga: Make svga_set_default_crt_regs() take an iomem regbase pointer. Signed-off-by: David S. Miller Signed-off-by: Paul Mundt --- drivers/video/arkfb.c | 2 +- drivers/video/s3fb.c | 2 +- drivers/video/svgalib.c | 12 ++++++------ drivers/video/vt8623fb.c | 2 +- include/linux/svga.h | 2 +- 5 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/video/arkfb.c b/drivers/video/arkfb.c index f24151e01da3..51fd8affe0c7 100644 --- a/drivers/video/arkfb.c +++ b/drivers/video/arkfb.c @@ -656,7 +656,7 @@ static int arkfb_set_par(struct fb_info *info) svga_set_default_gfx_regs(par->state.vgabase); svga_set_default_atc_regs(par->state.vgabase); svga_set_default_seq_regs(par->state.vgabase); - svga_set_default_crt_regs(); + svga_set_default_crt_regs(par->state.vgabase); svga_wcrt_multi(par->state.vgabase, ark_line_compare_regs, 0xFFFFFFFF); svga_wcrt_multi(par->state.vgabase, ark_start_address_regs, 0); diff --git a/drivers/video/s3fb.c b/drivers/video/s3fb.c index ece99f2044f4..a7a2463663c4 100644 --- a/drivers/video/s3fb.c +++ b/drivers/video/s3fb.c @@ -517,7 +517,7 @@ static int s3fb_set_par(struct fb_info *info) svga_set_default_gfx_regs(par->state.vgabase); svga_set_default_atc_regs(par->state.vgabase); svga_set_default_seq_regs(par->state.vgabase); - svga_set_default_crt_regs(); + svga_set_default_crt_regs(par->state.vgabase); svga_wcrt_multi(par->state.vgabase, s3_line_compare_regs, 0xFFFFFFFF); svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, 0); diff --git a/drivers/video/svgalib.c b/drivers/video/svgalib.c index 3d07287e9322..b0464977ed9b 100644 --- a/drivers/video/svgalib.c +++ b/drivers/video/svgalib.c @@ -127,14 +127,14 @@ void svga_set_default_seq_regs(void __iomem *regbase) } /* Set CRTC registers to sane values */ -void svga_set_default_crt_regs(void) +void svga_set_default_crt_regs(void __iomem *regbase) { /* Standard CRT registers CR03 CR08 CR09 CR14 CR17 */ - svga_wcrt_mask(NULL, 0x03, 0x80, 0x80); /* Enable vertical retrace EVRA */ - vga_wcrt(NULL, VGA_CRTC_PRESET_ROW, 0); - svga_wcrt_mask(NULL, VGA_CRTC_MAX_SCAN, 0, 0x1F); - vga_wcrt(NULL, VGA_CRTC_UNDERLINE, 0); - vga_wcrt(NULL, VGA_CRTC_MODE, 0xE3); + svga_wcrt_mask(regbase, 0x03, 0x80, 0x80); /* Enable vertical retrace EVRA */ + vga_wcrt(regbase, VGA_CRTC_PRESET_ROW, 0); + svga_wcrt_mask(regbase, VGA_CRTC_MAX_SCAN, 0, 0x1F); + vga_wcrt(regbase, VGA_CRTC_UNDERLINE, 0); + vga_wcrt(regbase, VGA_CRTC_MODE, 0xE3); } void svga_set_textmode_vga_regs(void) diff --git a/drivers/video/vt8623fb.c b/drivers/video/vt8623fb.c index bc54b57db985..a2624a841ecc 100644 --- a/drivers/video/vt8623fb.c +++ b/drivers/video/vt8623fb.c @@ -429,7 +429,7 @@ static int vt8623fb_set_par(struct fb_info *info) svga_set_default_gfx_regs(par->state.vgabase); svga_set_default_atc_regs(par->state.vgabase); svga_set_default_seq_regs(par->state.vgabase); - svga_set_default_crt_regs(); + svga_set_default_crt_regs(par->state.vgabase); svga_wcrt_multi(par->state.vgabase, vt8623_line_compare_regs, 0xFFFFFFFF); svga_wcrt_multi(par->state.vgabase, vt8623_start_address_regs, 0); diff --git a/include/linux/svga.h b/include/linux/svga.h index 5c5b41bddee4..2a32dd55d1a0 100644 --- a/include/linux/svga.h +++ b/include/linux/svga.h @@ -102,7 +102,7 @@ void svga_wseq_multi(void __iomem *regbase, const struct vga_regset *regset, u32 void svga_set_default_gfx_regs(void __iomem *regbase); void svga_set_default_atc_regs(void __iomem *regbase); void svga_set_default_seq_regs(void __iomem *regbase); -void svga_set_default_crt_regs(void); +void svga_set_default_crt_regs(void __iomem *regbase); void svga_set_textmode_vga_regs(void); void svga_settile(struct fb_info *info, struct fb_tilemap *map); From 9c96394bb90f855d265116f37897294fa1bdb072 Mon Sep 17 00:00:00 2001 From: David Miller Date: Tue, 11 Jan 2011 23:51:56 +0000 Subject: [PATCH 102/140] svga: Make svga_set_textmode_vga_regs() take an iomem regbase pointer. Signed-off-by: David S. Miller Signed-off-by: Paul Mundt --- drivers/video/arkfb.c | 2 +- drivers/video/s3fb.c | 2 +- drivers/video/svgalib.c | 40 ++++++++++++++++++++-------------------- drivers/video/vt8623fb.c | 2 +- include/linux/svga.h | 2 +- 5 files changed, 24 insertions(+), 24 deletions(-) diff --git a/drivers/video/arkfb.c b/drivers/video/arkfb.c index 51fd8affe0c7..658fff45332c 100644 --- a/drivers/video/arkfb.c +++ b/drivers/video/arkfb.c @@ -699,7 +699,7 @@ static int arkfb_set_par(struct fb_info *info) switch (mode) { case 0: pr_debug("fb%d: text mode\n", info->node); - svga_set_textmode_vga_regs(); + svga_set_textmode_vga_regs(par->state.vgabase); vga_wseq(NULL, 0x11, 0x10); /* basic VGA mode */ svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */ diff --git a/drivers/video/s3fb.c b/drivers/video/s3fb.c index a7a2463663c4..017219565800 100644 --- a/drivers/video/s3fb.c +++ b/drivers/video/s3fb.c @@ -604,7 +604,7 @@ static int s3fb_set_par(struct fb_info *info) switch (mode) { case 0: pr_debug("fb%d: text mode\n", info->node); - svga_set_textmode_vga_regs(); + svga_set_textmode_vga_regs(par->state.vgabase); /* Set additional registers like in 8-bit mode */ svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); diff --git a/drivers/video/svgalib.c b/drivers/video/svgalib.c index b0464977ed9b..ecda90ec4056 100644 --- a/drivers/video/svgalib.c +++ b/drivers/video/svgalib.c @@ -137,33 +137,33 @@ void svga_set_default_crt_regs(void __iomem *regbase) vga_wcrt(regbase, VGA_CRTC_MODE, 0xE3); } -void svga_set_textmode_vga_regs(void) +void svga_set_textmode_vga_regs(void __iomem *regbase) { - /* svga_wseq_mask(NULL, 0x1, 0x00, 0x01); */ /* Switch 8/9 pixel per char */ - vga_wseq(NULL, VGA_SEQ_MEMORY_MODE, VGA_SR04_EXT_MEM); - vga_wseq(NULL, VGA_SEQ_PLANE_WRITE, 0x03); + /* svga_wseq_mask(regbase, 0x1, 0x00, 0x01); */ /* Switch 8/9 pixel per char */ + vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, VGA_SR04_EXT_MEM); + vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0x03); - vga_wcrt(NULL, VGA_CRTC_MAX_SCAN, 0x0f); /* 0x4f */ - vga_wcrt(NULL, VGA_CRTC_UNDERLINE, 0x1f); - svga_wcrt_mask(NULL, VGA_CRTC_MODE, 0x23, 0x7f); + vga_wcrt(regbase, VGA_CRTC_MAX_SCAN, 0x0f); /* 0x4f */ + vga_wcrt(regbase, VGA_CRTC_UNDERLINE, 0x1f); + svga_wcrt_mask(regbase, VGA_CRTC_MODE, 0x23, 0x7f); - vga_wcrt(NULL, VGA_CRTC_CURSOR_START, 0x0d); - vga_wcrt(NULL, VGA_CRTC_CURSOR_END, 0x0e); - vga_wcrt(NULL, VGA_CRTC_CURSOR_HI, 0x00); - vga_wcrt(NULL, VGA_CRTC_CURSOR_LO, 0x00); + vga_wcrt(regbase, VGA_CRTC_CURSOR_START, 0x0d); + vga_wcrt(regbase, VGA_CRTC_CURSOR_END, 0x0e); + vga_wcrt(regbase, VGA_CRTC_CURSOR_HI, 0x00); + vga_wcrt(regbase, VGA_CRTC_CURSOR_LO, 0x00); - vga_wgfx(NULL, VGA_GFX_MODE, 0x10); /* Odd/even memory mode */ - vga_wgfx(NULL, VGA_GFX_MISC, 0x0E); /* Misc graphics register - text mode enable */ - vga_wgfx(NULL, VGA_GFX_COMPARE_MASK, 0x00); + vga_wgfx(regbase, VGA_GFX_MODE, 0x10); /* Odd/even memory mode */ + vga_wgfx(regbase, VGA_GFX_MISC, 0x0E); /* Misc graphics register - text mode enable */ + vga_wgfx(regbase, VGA_GFX_COMPARE_MASK, 0x00); - vga_r(NULL, 0x3DA); - vga_w(NULL, VGA_ATT_W, 0x00); + vga_r(regbase, 0x3DA); + vga_w(regbase, VGA_ATT_W, 0x00); - svga_wattr(NULL, 0x10, 0x0C); /* Attribute Mode Control Register - text mode, blinking and line graphics */ - svga_wattr(NULL, 0x13, 0x08); /* Horizontal Pixel Panning Register */ + svga_wattr(regbase, 0x10, 0x0C); /* Attribute Mode Control Register - text mode, blinking and line graphics */ + svga_wattr(regbase, 0x13, 0x08); /* Horizontal Pixel Panning Register */ - vga_r(NULL, 0x3DA); - vga_w(NULL, VGA_ATT_W, 0x20); + vga_r(regbase, 0x3DA); + vga_w(regbase, VGA_ATT_W, 0x20); } #if 0 diff --git a/drivers/video/vt8623fb.c b/drivers/video/vt8623fb.c index a2624a841ecc..e3bb7c5b1bd5 100644 --- a/drivers/video/vt8623fb.c +++ b/drivers/video/vt8623fb.c @@ -466,7 +466,7 @@ static int vt8623fb_set_par(struct fb_info *info) switch (mode) { case 0: pr_debug("fb%d: text mode\n", info->node); - svga_set_textmode_vga_regs(); + svga_set_textmode_vga_regs(par->state.vgabase); svga_wseq_mask(par->state.vgabase, 0x15, 0x00, 0xFE); svga_wcrt_mask(par->state.vgabase, 0x11, 0x60, 0x70); break; diff --git a/include/linux/svga.h b/include/linux/svga.h index 2a32dd55d1a0..767937d362d1 100644 --- a/include/linux/svga.h +++ b/include/linux/svga.h @@ -103,7 +103,7 @@ void svga_set_default_gfx_regs(void __iomem *regbase); void svga_set_default_atc_regs(void __iomem *regbase); void svga_set_default_seq_regs(void __iomem *regbase); void svga_set_default_crt_regs(void __iomem *regbase); -void svga_set_textmode_vga_regs(void); +void svga_set_textmode_vga_regs(void __iomem *regbase); void svga_settile(struct fb_info *info, struct fb_tilemap *map); void svga_tilecopy(struct fb_info *info, struct fb_tilearea *area); From 55db092388455457791cf00216b6b3965a8071f8 Mon Sep 17 00:00:00 2001 From: David Miller Date: Tue, 11 Jan 2011 23:52:11 +0000 Subject: [PATCH 103/140] svga: Make svga_tilecursor() take an iomem regbase pointer. Signed-off-by: David S. Miller Signed-off-by: Paul Mundt --- drivers/video/arkfb.c | 9 ++++++++- drivers/video/s3fb.c | 11 +++++++++-- drivers/video/svgalib.c | 12 ++++++------ drivers/video/vt8623fb.c | 8 +++++++- include/linux/svga.h | 2 +- 5 files changed, 31 insertions(+), 11 deletions(-) diff --git a/drivers/video/arkfb.c b/drivers/video/arkfb.c index 658fff45332c..a4cfcf99ceb6 100644 --- a/drivers/video/arkfb.c +++ b/drivers/video/arkfb.c @@ -158,12 +158,19 @@ static void arkfb_settile(struct fb_info *info, struct fb_tilemap *map) } } +static void arkfb_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor) +{ + struct arkfb_info *par = info->par; + + svga_tilecursor(par->state.vgabase, info, cursor); +} + static struct fb_tile_ops arkfb_tile_ops = { .fb_settile = arkfb_settile, .fb_tilecopy = svga_tilecopy, .fb_tilefill = svga_tilefill, .fb_tileblit = svga_tileblit, - .fb_tilecursor = svga_tilecursor, + .fb_tilecursor = arkfb_tilecursor, .fb_get_tilemax = svga_get_tilemax, }; diff --git a/drivers/video/s3fb.c b/drivers/video/s3fb.c index 017219565800..be3802e8108a 100644 --- a/drivers/video/s3fb.c +++ b/drivers/video/s3fb.c @@ -188,12 +188,19 @@ static void s3fb_settile_fast(struct fb_info *info, struct fb_tilemap *map) } } +static void s3fb_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor) +{ + struct s3fb_info *par = info->par; + + svga_tilecursor(par->state.vgabase, info, cursor); +} + static struct fb_tile_ops s3fb_tile_ops = { .fb_settile = svga_settile, .fb_tilecopy = svga_tilecopy, .fb_tilefill = svga_tilefill, .fb_tileblit = svga_tileblit, - .fb_tilecursor = svga_tilecursor, + .fb_tilecursor = s3fb_tilecursor, .fb_get_tilemax = svga_get_tilemax, }; @@ -202,7 +209,7 @@ static struct fb_tile_ops s3fb_fast_tile_ops = { .fb_tilecopy = svga_tilecopy, .fb_tilefill = svga_tilefill, .fb_tileblit = svga_tileblit, - .fb_tilecursor = svga_tilecursor, + .fb_tilecursor = s3fb_tilecursor, .fb_get_tilemax = svga_get_tilemax, }; diff --git a/drivers/video/svgalib.c b/drivers/video/svgalib.c index ecda90ec4056..4876be85ecfd 100644 --- a/drivers/video/svgalib.c +++ b/drivers/video/svgalib.c @@ -299,7 +299,7 @@ void svga_tileblit(struct fb_info *info, struct fb_tileblit *blit) } /* Set cursor in text (tileblit) mode */ -void svga_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor) +void svga_tilecursor(void __iomem *regbase, struct fb_info *info, struct fb_tilecursor *cursor) { u8 cs = 0x0d; u8 ce = 0x0e; @@ -310,7 +310,7 @@ void svga_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor) if (! cursor -> mode) return; - svga_wcrt_mask(NULL, 0x0A, 0x20, 0x20); /* disable cursor */ + svga_wcrt_mask(regbase, 0x0A, 0x20, 0x20); /* disable cursor */ if (cursor -> shape == FB_TILE_CURSOR_NONE) return; @@ -334,11 +334,11 @@ void svga_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor) } /* set cursor position */ - vga_wcrt(NULL, 0x0E, pos >> 8); - vga_wcrt(NULL, 0x0F, pos & 0xFF); + vga_wcrt(regbase, 0x0E, pos >> 8); + vga_wcrt(regbase, 0x0F, pos & 0xFF); - vga_wcrt(NULL, 0x0B, ce); /* set cursor end */ - vga_wcrt(NULL, 0x0A, cs); /* set cursor start and enable it */ + vga_wcrt(regbase, 0x0B, ce); /* set cursor end */ + vga_wcrt(regbase, 0x0A, cs); /* set cursor start and enable it */ } int svga_get_tilemax(struct fb_info *info) diff --git a/drivers/video/vt8623fb.c b/drivers/video/vt8623fb.c index e3bb7c5b1bd5..cedac002fa4b 100644 --- a/drivers/video/vt8623fb.c +++ b/drivers/video/vt8623fb.c @@ -121,13 +121,19 @@ MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, d /* ------------------------------------------------------------------------- */ +static void vt8623fb_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor) +{ + struct vt8623fb_info *par = info->par; + + svga_tilecursor(par->state.vgabase, info, cursor); +} static struct fb_tile_ops vt8623fb_tile_ops = { .fb_settile = svga_settile, .fb_tilecopy = svga_tilecopy, .fb_tilefill = svga_tilefill, .fb_tileblit = svga_tileblit, - .fb_tilecursor = svga_tilecursor, + .fb_tilecursor = vt8623fb_tilecursor, .fb_get_tilemax = svga_get_tilemax, }; diff --git a/include/linux/svga.h b/include/linux/svga.h index 767937d362d1..87879500f75b 100644 --- a/include/linux/svga.h +++ b/include/linux/svga.h @@ -109,7 +109,7 @@ void svga_settile(struct fb_info *info, struct fb_tilemap *map); void svga_tilecopy(struct fb_info *info, struct fb_tilearea *area); void svga_tilefill(struct fb_info *info, struct fb_tilerect *rect); void svga_tileblit(struct fb_info *info, struct fb_tileblit *blit); -void svga_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor); +void svga_tilecursor(void __iomem *regbase, struct fb_info *info, struct fb_tilecursor *cursor); int svga_get_tilemax(struct fb_info *info); void svga_get_caps(struct fb_info *info, struct fb_blit_caps *caps, struct fb_var_screeninfo *var); From 38d2620ea40c2f9a5f17d6488bf004973570279c Mon Sep 17 00:00:00 2001 From: David Miller Date: Tue, 11 Jan 2011 23:52:25 +0000 Subject: [PATCH 104/140] svga: Make svga_set_timings() take an iomem regbase pointer. Signed-off-by: David S. Miller Signed-off-by: Paul Mundt --- drivers/video/arkfb.c | 2 +- drivers/video/s3fb.c | 2 +- drivers/video/svgalib.c | 33 +++++++++++++++++---------------- drivers/video/vt8623fb.c | 2 +- include/linux/svga.h | 2 +- 5 files changed, 21 insertions(+), 20 deletions(-) diff --git a/drivers/video/arkfb.c b/drivers/video/arkfb.c index a4cfcf99ceb6..aded91b42c76 100644 --- a/drivers/video/arkfb.c +++ b/drivers/video/arkfb.c @@ -781,7 +781,7 @@ static int arkfb_set_par(struct fb_info *info) } ark_set_pixclock(info, (hdiv * info->var.pixclock) / hmul); - svga_set_timings(&ark_timing_regs, &(info->var), hmul, hdiv, + svga_set_timings(par->state.vgabase, &ark_timing_regs, &(info->var), hmul, hdiv, (info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1, (info->var.vmode & FB_VMODE_INTERLACED) ? 2 : 1, hmul, info->node); diff --git a/drivers/video/s3fb.c b/drivers/video/s3fb.c index be3802e8108a..23e4724bd439 100644 --- a/drivers/video/s3fb.c +++ b/drivers/video/s3fb.c @@ -712,7 +712,7 @@ static int s3fb_set_par(struct fb_info *info) } s3_set_pixclock(info, info->var.pixclock); - svga_set_timings(&s3_timing_regs, &(info->var), hmul, 1, + svga_set_timings(par->state.vgabase, &s3_timing_regs, &(info->var), hmul, 1, (info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1, (info->var.vmode & FB_VMODE_INTERLACED) ? 2 : 1, hmul, info->node); diff --git a/drivers/video/svgalib.c b/drivers/video/svgalib.c index 4876be85ecfd..33df9ec91795 100644 --- a/drivers/video/svgalib.c +++ b/drivers/video/svgalib.c @@ -507,8 +507,9 @@ int svga_check_timings(const struct svga_timing_regs *tm, struct fb_var_screenin } /* Set CRT timing registers */ -void svga_set_timings(const struct svga_timing_regs *tm, struct fb_var_screeninfo *var, - u32 hmul, u32 hdiv, u32 vmul, u32 vdiv, u32 hborder, int node) +void svga_set_timings(void __iomem *regbase, const struct svga_timing_regs *tm, + struct fb_var_screeninfo *var, + u32 hmul, u32 hdiv, u32 vmul, u32 vdiv, u32 hborder, int node) { u8 regval; u32 value; @@ -516,66 +517,66 @@ void svga_set_timings(const struct svga_timing_regs *tm, struct fb_var_screeninf value = var->xres + var->left_margin + var->right_margin + var->hsync_len; value = (value * hmul) / hdiv; pr_debug("fb%d: horizontal total : %d\n", node, value); - svga_wcrt_multi(NULL, tm->h_total_regs, (value / 8) - 5); + svga_wcrt_multi(regbase, tm->h_total_regs, (value / 8) - 5); value = var->xres; value = (value * hmul) / hdiv; pr_debug("fb%d: horizontal display : %d\n", node, value); - svga_wcrt_multi(NULL, tm->h_display_regs, (value / 8) - 1); + svga_wcrt_multi(regbase, tm->h_display_regs, (value / 8) - 1); value = var->xres; value = (value * hmul) / hdiv; pr_debug("fb%d: horizontal blank start: %d\n", node, value); - svga_wcrt_multi(NULL, tm->h_blank_start_regs, (value / 8) - 1 + hborder); + svga_wcrt_multi(regbase, tm->h_blank_start_regs, (value / 8) - 1 + hborder); value = var->xres + var->left_margin + var->right_margin + var->hsync_len; value = (value * hmul) / hdiv; pr_debug("fb%d: horizontal blank end : %d\n", node, value); - svga_wcrt_multi(NULL, tm->h_blank_end_regs, (value / 8) - 1 - hborder); + svga_wcrt_multi(regbase, tm->h_blank_end_regs, (value / 8) - 1 - hborder); value = var->xres + var->right_margin; value = (value * hmul) / hdiv; pr_debug("fb%d: horizontal sync start : %d\n", node, value); - svga_wcrt_multi(NULL, tm->h_sync_start_regs, (value / 8)); + svga_wcrt_multi(regbase, tm->h_sync_start_regs, (value / 8)); value = var->xres + var->right_margin + var->hsync_len; value = (value * hmul) / hdiv; pr_debug("fb%d: horizontal sync end : %d\n", node, value); - svga_wcrt_multi(NULL, tm->h_sync_end_regs, (value / 8)); + svga_wcrt_multi(regbase, tm->h_sync_end_regs, (value / 8)); value = var->yres + var->upper_margin + var->lower_margin + var->vsync_len; value = (value * vmul) / vdiv; pr_debug("fb%d: vertical total : %d\n", node, value); - svga_wcrt_multi(NULL, tm->v_total_regs, value - 2); + svga_wcrt_multi(regbase, tm->v_total_regs, value - 2); value = var->yres; value = (value * vmul) / vdiv; pr_debug("fb%d: vertical display : %d\n", node, value); - svga_wcrt_multi(NULL, tm->v_display_regs, value - 1); + svga_wcrt_multi(regbase, tm->v_display_regs, value - 1); value = var->yres; value = (value * vmul) / vdiv; pr_debug("fb%d: vertical blank start : %d\n", node, value); - svga_wcrt_multi(NULL, tm->v_blank_start_regs, value); + svga_wcrt_multi(regbase, tm->v_blank_start_regs, value); value = var->yres + var->upper_margin + var->lower_margin + var->vsync_len; value = (value * vmul) / vdiv; pr_debug("fb%d: vertical blank end : %d\n", node, value); - svga_wcrt_multi(NULL, tm->v_blank_end_regs, value - 2); + svga_wcrt_multi(regbase, tm->v_blank_end_regs, value - 2); value = var->yres + var->lower_margin; value = (value * vmul) / vdiv; pr_debug("fb%d: vertical sync start : %d\n", node, value); - svga_wcrt_multi(NULL, tm->v_sync_start_regs, value); + svga_wcrt_multi(regbase, tm->v_sync_start_regs, value); value = var->yres + var->lower_margin + var->vsync_len; value = (value * vmul) / vdiv; pr_debug("fb%d: vertical sync end : %d\n", node, value); - svga_wcrt_multi(NULL, tm->v_sync_end_regs, value); + svga_wcrt_multi(regbase, tm->v_sync_end_regs, value); /* Set horizontal and vertical sync pulse polarity in misc register */ - regval = vga_r(NULL, VGA_MIS_R); + regval = vga_r(regbase, VGA_MIS_R); if (var->sync & FB_SYNC_HOR_HIGH_ACT) { pr_debug("fb%d: positive horizontal sync\n", node); regval = regval & ~0x80; @@ -590,7 +591,7 @@ void svga_set_timings(const struct svga_timing_regs *tm, struct fb_var_screeninf pr_debug("fb%d: negative vertical sync\n\n", node); regval = regval | 0x40; } - vga_w(NULL, VGA_MIS_W, regval); + vga_w(regbase, VGA_MIS_W, regval); } diff --git a/drivers/video/vt8623fb.c b/drivers/video/vt8623fb.c index cedac002fa4b..4764fb2fffc0 100644 --- a/drivers/video/vt8623fb.c +++ b/drivers/video/vt8623fb.c @@ -505,7 +505,7 @@ static int vt8623fb_set_par(struct fb_info *info) } vt8623_set_pixclock(info, info->var.pixclock); - svga_set_timings(&vt8623_timing_regs, &(info->var), 1, 1, + svga_set_timings(par->state.vgabase, &vt8623_timing_regs, &(info->var), 1, 1, (info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1, 1, 1, info->node); diff --git a/include/linux/svga.h b/include/linux/svga.h index 87879500f75b..bfa68e837d6a 100644 --- a/include/linux/svga.h +++ b/include/linux/svga.h @@ -116,7 +116,7 @@ void svga_get_caps(struct fb_info *info, struct fb_blit_caps *caps, int svga_compute_pll(const struct svga_pll *pll, u32 f_wanted, u16 *m, u16 *n, u16 *r, int node); int svga_check_timings(const struct svga_timing_regs *tm, struct fb_var_screeninfo *var, int node); -void svga_set_timings(const struct svga_timing_regs *tm, struct fb_var_screeninfo *var, u32 hmul, u32 hdiv, u32 vmul, u32 vdiv, u32 hborder, int node); +void svga_set_timings(void __iomem *regbase, const struct svga_timing_regs *tm, struct fb_var_screeninfo *var, u32 hmul, u32 hdiv, u32 vmul, u32 vdiv, u32 hborder, int node); int svga_match_format(const struct svga_fb_format *frm, struct fb_var_screeninfo *var, struct fb_fix_screeninfo *fix); From c5e04633b3b765a06986008e577930555e0f544b Mon Sep 17 00:00:00 2001 From: David Miller Date: Tue, 11 Jan 2011 23:52:40 +0000 Subject: [PATCH 105/140] arkfb: Pass par->state.vgabase to vga_*() calls. Instead of just plain NULL. Signed-off-by: David S. Miller Signed-off-by: Paul Mundt --- drivers/video/arkfb.c | 60 ++++++++++++++++++++++++------------------- 1 file changed, 34 insertions(+), 26 deletions(-) diff --git a/drivers/video/arkfb.c b/drivers/video/arkfb.c index aded91b42c76..53c66e8dcb0b 100644 --- a/drivers/video/arkfb.c +++ b/drivers/video/arkfb.c @@ -473,32 +473,40 @@ static unsigned short dac_regs[4] = {0x3c8, 0x3c9, 0x3c6, 0x3c7}; static void ark_dac_read_regs(void *data, u8 *code, int count) { - u8 regval = vga_rseq(NULL, 0x1C); + struct fb_info *info = data; + struct arkfb_info *par; + u8 regval; + par = info->par; + regval = vga_rseq(par->state.vgabase, 0x1C); while (count != 0) { - vga_wseq(NULL, 0x1C, regval | (code[0] & 4 ? 0x80 : 0)); - code[1] = vga_r(NULL, dac_regs[code[0] & 3]); + vga_wseq(par->state.vgabase, 0x1C, regval | (code[0] & 4 ? 0x80 : 0)); + code[1] = vga_r(par->state.vgabase, dac_regs[code[0] & 3]); count--; code += 2; } - vga_wseq(NULL, 0x1C, regval); + vga_wseq(par->state.vgabase, 0x1C, regval); } static void ark_dac_write_regs(void *data, u8 *code, int count) { - u8 regval = vga_rseq(NULL, 0x1C); + struct fb_info *info = data; + struct arkfb_info *par; + u8 regval; + par = info->par; + regval = vga_rseq(par->state.vgabase, 0x1C); while (count != 0) { - vga_wseq(NULL, 0x1C, regval | (code[0] & 4 ? 0x80 : 0)); - vga_w(NULL, dac_regs[code[0] & 3], code[1]); + vga_wseq(par->state.vgabase, 0x1C, regval | (code[0] & 4 ? 0x80 : 0)); + vga_w(par->state.vgabase, dac_regs[code[0] & 3], code[1]); count--; code += 2; } - vga_wseq(NULL, 0x1C, regval); + vga_wseq(par->state.vgabase, 0x1C, regval); } @@ -514,8 +522,8 @@ static void ark_set_pixclock(struct fb_info *info, u32 pixclock) } /* Set VGA misc register */ - regval = vga_r(NULL, VGA_MIS_R); - vga_w(NULL, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD); + regval = vga_r(par->state.vgabase, VGA_MIS_R); + vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD); } @@ -671,15 +679,15 @@ static int arkfb_set_par(struct fb_info *info) svga_wseq_mask(par->state.vgabase, 0x10, 0x1F, 0x1F); /* enable linear framebuffer and full memory access */ svga_wseq_mask(par->state.vgabase, 0x12, 0x03, 0x03); /* 4 MB linear framebuffer size */ - vga_wseq(NULL, 0x13, info->fix.smem_start >> 16); - vga_wseq(NULL, 0x14, info->fix.smem_start >> 24); - vga_wseq(NULL, 0x15, 0); - vga_wseq(NULL, 0x16, 0); + vga_wseq(par->state.vgabase, 0x13, info->fix.smem_start >> 16); + vga_wseq(par->state.vgabase, 0x14, info->fix.smem_start >> 24); + vga_wseq(par->state.vgabase, 0x15, 0); + vga_wseq(par->state.vgabase, 0x16, 0); /* Set the FIFO threshold register */ /* It is fascinating way to store 5-bit value in 8-bit register */ regval = 0x10 | ((threshold & 0x0E) >> 1) | (threshold & 0x01) << 7 | (threshold & 0x10) << 1; - vga_wseq(NULL, 0x18, regval); + vga_wseq(par->state.vgabase, 0x18, regval); /* Set the offset register */ pr_debug("fb%d: offset register : %d\n", info->node, offset_value); @@ -708,30 +716,30 @@ static int arkfb_set_par(struct fb_info *info) pr_debug("fb%d: text mode\n", info->node); svga_set_textmode_vga_regs(par->state.vgabase); - vga_wseq(NULL, 0x11, 0x10); /* basic VGA mode */ + vga_wseq(par->state.vgabase, 0x11, 0x10); /* basic VGA mode */ svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */ dac_set_mode(par->dac, DAC_PSEUDO8_8); break; case 1: pr_debug("fb%d: 4 bit pseudocolor\n", info->node); - vga_wgfx(NULL, VGA_GFX_MODE, 0x40); + vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40); - vga_wseq(NULL, 0x11, 0x10); /* basic VGA mode */ + vga_wseq(par->state.vgabase, 0x11, 0x10); /* basic VGA mode */ svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */ dac_set_mode(par->dac, DAC_PSEUDO8_8); break; case 2: pr_debug("fb%d: 4 bit pseudocolor, planar\n", info->node); - vga_wseq(NULL, 0x11, 0x10); /* basic VGA mode */ + vga_wseq(par->state.vgabase, 0x11, 0x10); /* basic VGA mode */ svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */ dac_set_mode(par->dac, DAC_PSEUDO8_8); break; case 3: pr_debug("fb%d: 8 bit pseudocolor\n", info->node); - vga_wseq(NULL, 0x11, 0x16); /* 8bpp accel mode */ + vga_wseq(par->state.vgabase, 0x11, 0x16); /* 8bpp accel mode */ if (info->var.pixclock > 20000) { pr_debug("fb%d: not using multiplex\n", info->node); @@ -747,21 +755,21 @@ static int arkfb_set_par(struct fb_info *info) case 4: pr_debug("fb%d: 5/5/5 truecolor\n", info->node); - vga_wseq(NULL, 0x11, 0x1A); /* 16bpp accel mode */ + vga_wseq(par->state.vgabase, 0x11, 0x1A); /* 16bpp accel mode */ svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */ dac_set_mode(par->dac, DAC_RGB1555_16); break; case 5: pr_debug("fb%d: 5/6/5 truecolor\n", info->node); - vga_wseq(NULL, 0x11, 0x1A); /* 16bpp accel mode */ + vga_wseq(par->state.vgabase, 0x11, 0x1A); /* 16bpp accel mode */ svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */ dac_set_mode(par->dac, DAC_RGB0565_16); break; case 6: pr_debug("fb%d: 8/8/8 truecolor\n", info->node); - vga_wseq(NULL, 0x11, 0x16); /* 8bpp accel mode ??? */ + vga_wseq(par->state.vgabase, 0x11, 0x16); /* 8bpp accel mode ??? */ svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */ dac_set_mode(par->dac, DAC_RGB0888_16); hmul = 3; @@ -770,7 +778,7 @@ static int arkfb_set_par(struct fb_info *info) case 7: pr_debug("fb%d: 8/8/8/8 truecolor\n", info->node); - vga_wseq(NULL, 0x11, 0x1E); /* 32bpp accel mode */ + vga_wseq(par->state.vgabase, 0x11, 0x1E); /* 32bpp accel mode */ svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */ dac_set_mode(par->dac, DAC_RGB8888_16); hmul = 2; @@ -789,7 +797,7 @@ static int arkfb_set_par(struct fb_info *info) /* Set interlaced mode start/end register */ value = info->var.xres + info->var.left_margin + info->var.right_margin + info->var.hsync_len; value = ((value * hmul / hdiv) / 8) - 5; - vga_wcrt(NULL, 0x42, (value + 1) / 2); + vga_wcrt(par->state.vgabase, 0x42, (value + 1) / 2); memset_io(info->screen_base, 0x00, screen_size); /* Device and screen back on */ @@ -996,7 +1004,7 @@ static int __devinit ark_pci_probe(struct pci_dev *dev, const struct pci_device_ } /* FIXME get memsize */ - regval = vga_rseq(NULL, 0x10); + regval = vga_rseq(par->state.vgabase, 0x10); info->screen_size = (1 << (regval >> 6)) << 20; info->fix.smem_len = info->screen_size; From f8645933513c65ac55f23c63b2649097289795c6 Mon Sep 17 00:00:00 2001 From: David Miller Date: Tue, 11 Jan 2011 23:52:57 +0000 Subject: [PATCH 106/140] s3fb: Pass par->state.vgabase to vga_*() calls. Instead of just plain NULL. Signed-off-by: David S. Miller Signed-off-by: Paul Mundt --- drivers/video/s3fb.c | 102 ++++++++++++++++++++++--------------------- 1 file changed, 52 insertions(+), 50 deletions(-) diff --git a/drivers/video/s3fb.c b/drivers/video/s3fb.c index 23e4724bd439..262490a74bb7 100644 --- a/drivers/video/s3fb.c +++ b/drivers/video/s3fb.c @@ -348,26 +348,26 @@ static void s3_set_pixclock(struct fb_info *info, u32 pixclock) } /* Set VGA misc register */ - regval = vga_r(NULL, VGA_MIS_R); - vga_w(NULL, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD); + regval = vga_r(par->state.vgabase, VGA_MIS_R); + vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD); /* Set S3 clock registers */ if (par->chip == CHIP_360_TRIO3D_1X || par->chip == CHIP_362_TRIO3D_2X || par->chip == CHIP_368_TRIO3D_2X) { - vga_wseq(NULL, 0x12, (n - 2) | ((r & 3) << 6)); /* n and two bits of r */ - vga_wseq(NULL, 0x29, r >> 2); /* remaining highest bit of r */ + vga_wseq(par->state.vgabase, 0x12, (n - 2) | ((r & 3) << 6)); /* n and two bits of r */ + vga_wseq(par->state.vgabase, 0x29, r >> 2); /* remaining highest bit of r */ } else - vga_wseq(NULL, 0x12, (n - 2) | (r << 5)); - vga_wseq(NULL, 0x13, m - 2); + vga_wseq(par->state.vgabase, 0x12, (n - 2) | (r << 5)); + vga_wseq(par->state.vgabase, 0x13, m - 2); udelay(1000); /* Activate clock - write 0, 1, 0 to seq/15 bit 5 */ - regval = vga_rseq (NULL, 0x15); /* | 0x80; */ - vga_wseq(NULL, 0x15, regval & ~(1<<5)); - vga_wseq(NULL, 0x15, regval | (1<<5)); - vga_wseq(NULL, 0x15, regval & ~(1<<5)); + regval = vga_rseq (par->state.vgabase, 0x15); /* | 0x80; */ + vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5)); + vga_wseq(par->state.vgabase, 0x15, regval | (1<<5)); + vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5)); } @@ -511,9 +511,9 @@ static int s3fb_set_par(struct fb_info *info) info->var.activate = FB_ACTIVATE_NOW; /* Unlock registers */ - vga_wcrt(NULL, 0x38, 0x48); - vga_wcrt(NULL, 0x39, 0xA5); - vga_wseq(NULL, 0x08, 0x06); + vga_wcrt(par->state.vgabase, 0x38, 0x48); + vga_wcrt(par->state.vgabase, 0x39, 0xA5); + vga_wseq(par->state.vgabase, 0x08, 0x06); svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80); /* Blank screen and turn off sync */ @@ -552,13 +552,13 @@ static int s3fb_set_par(struct fb_info *info) if (par->chip != CHIP_360_TRIO3D_1X && par->chip != CHIP_362_TRIO3D_2X && par->chip != CHIP_368_TRIO3D_2X) { - vga_wcrt(NULL, 0x54, 0x18); /* M parameter */ - vga_wcrt(NULL, 0x60, 0xff); /* N parameter */ - vga_wcrt(NULL, 0x61, 0xff); /* L parameter */ - vga_wcrt(NULL, 0x62, 0xff); /* L parameter */ + vga_wcrt(par->state.vgabase, 0x54, 0x18); /* M parameter */ + vga_wcrt(par->state.vgabase, 0x60, 0xff); /* N parameter */ + vga_wcrt(par->state.vgabase, 0x61, 0xff); /* L parameter */ + vga_wcrt(par->state.vgabase, 0x62, 0xff); /* L parameter */ } - vga_wcrt(NULL, 0x3A, 0x35); + vga_wcrt(par->state.vgabase, 0x3A, 0x35); svga_wattr(par->state.vgabase, 0x33, 0x00); if (info->var.vmode & FB_VMODE_DOUBLE) @@ -580,27 +580,27 @@ static int s3fb_set_par(struct fb_info *info) /* S3 virge DX hack */ if (par->chip == CHIP_375_VIRGE_DX) { - vga_wcrt(NULL, 0x86, 0x80); - vga_wcrt(NULL, 0x90, 0x00); + vga_wcrt(par->state.vgabase, 0x86, 0x80); + vga_wcrt(par->state.vgabase, 0x90, 0x00); } /* S3 virge VX hack */ if (par->chip == CHIP_988_VIRGE_VX) { - vga_wcrt(NULL, 0x50, 0x00); - vga_wcrt(NULL, 0x67, 0x50); + vga_wcrt(par->state.vgabase, 0x50, 0x00); + vga_wcrt(par->state.vgabase, 0x67, 0x50); - vga_wcrt(NULL, 0x63, (mode <= 2) ? 0x90 : 0x09); - vga_wcrt(NULL, 0x66, 0x90); + vga_wcrt(par->state.vgabase, 0x63, (mode <= 2) ? 0x90 : 0x09); + vga_wcrt(par->state.vgabase, 0x66, 0x90); } if (par->chip == CHIP_360_TRIO3D_1X || par->chip == CHIP_362_TRIO3D_2X || par->chip == CHIP_368_TRIO3D_2X) { dbytes = info->var.xres * ((bpp+7)/8); - vga_wcrt(NULL, 0x91, (dbytes + 7) / 8); - vga_wcrt(NULL, 0x90, (((dbytes + 7) / 8) >> 8) | 0x80); + vga_wcrt(par->state.vgabase, 0x91, (dbytes + 7) / 8); + vga_wcrt(par->state.vgabase, 0x90, (((dbytes + 7) / 8) >> 8) | 0x80); - vga_wcrt(NULL, 0x66, 0x81); + vga_wcrt(par->state.vgabase, 0x66, 0x81); } svga_wcrt_mask(par->state.vgabase, 0x31, 0x00, 0x40); @@ -627,7 +627,7 @@ static int s3fb_set_par(struct fb_info *info) break; case 1: pr_debug("fb%d: 4 bit pseudocolor\n", info->node); - vga_wgfx(NULL, VGA_GFX_MODE, 0x40); + vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40); /* Set additional registers like in 8-bit mode */ svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); @@ -720,7 +720,7 @@ static int s3fb_set_par(struct fb_info *info) /* Set interlaced mode start/end register */ value = info->var.xres + info->var.left_margin + info->var.right_margin + info->var.hsync_len; value = ((value * hmul) / 8) - 5; - vga_wcrt(NULL, 0x3C, (value + 1) / 2); + vga_wcrt(par->state.vgabase, 0x3C, (value + 1) / 2); memset_io(info->screen_base, 0x00, screen_size); /* Device and screen back on */ @@ -873,12 +873,14 @@ static struct fb_ops s3fb_ops = { /* ------------------------------------------------------------------------- */ -static int __devinit s3_identification(int chip) +static int __devinit s3_identification(struct s3fb_info *par) { + int chip = par->chip; + if (chip == CHIP_XXX_TRIO) { - u8 cr30 = vga_rcrt(NULL, 0x30); - u8 cr2e = vga_rcrt(NULL, 0x2e); - u8 cr2f = vga_rcrt(NULL, 0x2f); + u8 cr30 = vga_rcrt(par->state.vgabase, 0x30); + u8 cr2e = vga_rcrt(par->state.vgabase, 0x2e); + u8 cr2f = vga_rcrt(par->state.vgabase, 0x2f); if ((cr30 == 0xE0) || (cr30 == 0xE1)) { if (cr2e == 0x10) @@ -893,7 +895,7 @@ static int __devinit s3_identification(int chip) } if (chip == CHIP_XXX_TRIO64V2_DXGX) { - u8 cr6f = vga_rcrt(NULL, 0x6f); + u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f); if (! (cr6f & 0x01)) return CHIP_775_TRIO64V2_DX; @@ -902,7 +904,7 @@ static int __devinit s3_identification(int chip) } if (chip == CHIP_XXX_VIRGE_DXGX) { - u8 cr6f = vga_rcrt(NULL, 0x6f); + u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f); if (! (cr6f & 0x01)) return CHIP_375_VIRGE_DX; @@ -911,7 +913,7 @@ static int __devinit s3_identification(int chip) } if (chip == CHIP_36X_TRIO3D_1X_2X) { - switch (vga_rcrt(NULL, 0x2f)) { + switch (vga_rcrt(par->state.vgabase, 0x2f)) { case 0x00: return CHIP_360_TRIO3D_1X; case 0x01: @@ -979,21 +981,21 @@ static int __devinit s3_pci_probe(struct pci_dev *dev, const struct pci_device_i } /* Unlock regs */ - cr38 = vga_rcrt(NULL, 0x38); - cr39 = vga_rcrt(NULL, 0x39); - vga_wseq(NULL, 0x08, 0x06); - vga_wcrt(NULL, 0x38, 0x48); - vga_wcrt(NULL, 0x39, 0xA5); + cr38 = vga_rcrt(par->state.vgabase, 0x38); + cr39 = vga_rcrt(par->state.vgabase, 0x39); + vga_wseq(par->state.vgabase, 0x08, 0x06); + vga_wcrt(par->state.vgabase, 0x38, 0x48); + vga_wcrt(par->state.vgabase, 0x39, 0xA5); /* Identify chip type */ par->chip = id->driver_data & CHIP_MASK; - par->rev = vga_rcrt(NULL, 0x2f); + par->rev = vga_rcrt(par->state.vgabase, 0x2f); if (par->chip & CHIP_UNDECIDED_FLAG) - par->chip = s3_identification(par->chip); + par->chip = s3_identification(par); /* Find how many physical memory there is on card */ /* 0x36 register is accessible even if other registers are locked */ - regval = vga_rcrt(NULL, 0x36); + regval = vga_rcrt(par->state.vgabase, 0x36); if (par->chip == CHIP_360_TRIO3D_1X || par->chip == CHIP_362_TRIO3D_2X || par->chip == CHIP_368_TRIO3D_2X) { @@ -1012,13 +1014,13 @@ static int __devinit s3_pci_probe(struct pci_dev *dev, const struct pci_device_i info->fix.smem_len = info->screen_size; /* Find MCLK frequency */ - regval = vga_rseq(NULL, 0x10); - par->mclk_freq = ((vga_rseq(NULL, 0x11) + 2) * 14318) / ((regval & 0x1F) + 2); + regval = vga_rseq(par->state.vgabase, 0x10); + par->mclk_freq = ((vga_rseq(par->state.vgabase, 0x11) + 2) * 14318) / ((regval & 0x1F) + 2); par->mclk_freq = par->mclk_freq >> (regval >> 5); /* Restore locks */ - vga_wcrt(NULL, 0x38, cr38); - vga_wcrt(NULL, 0x39, cr39); + vga_wcrt(par->state.vgabase, 0x38, cr38); + vga_wcrt(par->state.vgabase, 0x39, cr39); strcpy(info->fix.id, s3_names [par->chip]); info->fix.mmio_start = 0; @@ -1054,8 +1056,8 @@ static int __devinit s3_pci_probe(struct pci_dev *dev, const struct pci_device_i if (par->chip == CHIP_UNKNOWN) printk(KERN_INFO "fb%d: unknown chip, CR2D=%x, CR2E=%x, CRT2F=%x, CRT30=%x\n", - info->node, vga_rcrt(NULL, 0x2d), vga_rcrt(NULL, 0x2e), - vga_rcrt(NULL, 0x2f), vga_rcrt(NULL, 0x30)); + info->node, vga_rcrt(par->state.vgabase, 0x2d), vga_rcrt(par->state.vgabase, 0x2e), + vga_rcrt(par->state.vgabase, 0x2f), vga_rcrt(par->state.vgabase, 0x30)); /* Record a reference to the driver data */ pci_set_drvdata(dev, info); From ed3eb4c803dec3cf2976701f0b5722f98e642855 Mon Sep 17 00:00:00 2001 From: David Miller Date: Tue, 11 Jan 2011 23:53:11 +0000 Subject: [PATCH 107/140] vt8623fb: Pass par->state.vgabase to vga_*() calls. Instead of just plain NULL. Signed-off-by: David S. Miller Signed-off-by: Paul Mundt --- drivers/video/vt8623fb.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/video/vt8623fb.c b/drivers/video/vt8623fb.c index 4764fb2fffc0..54ddaeb60f0a 100644 --- a/drivers/video/vt8623fb.c +++ b/drivers/video/vt8623fb.c @@ -271,12 +271,12 @@ static void vt8623_set_pixclock(struct fb_info *info, u32 pixclock) } /* Set VGA misc register */ - regval = vga_r(NULL, VGA_MIS_R); - vga_w(NULL, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD); + regval = vga_r(par->state.vgabase, VGA_MIS_R); + vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD); /* Set clock registers */ - vga_wseq(NULL, 0x46, (n | (r << 6))); - vga_wseq(NULL, 0x47, m); + vga_wseq(par->state.vgabase, 0x46, (n | (r << 6))); + vga_wseq(par->state.vgabase, 0x47, m); udelay(1000); @@ -454,18 +454,18 @@ static int vt8623fb_set_par(struct fb_info *info) svga_wseq_mask(par->state.vgabase, 0x1E, 0xF0, 0xF0); // DI/DVP bus svga_wseq_mask(par->state.vgabase, 0x2A, 0x0F, 0x0F); // DI/DVP bus svga_wseq_mask(par->state.vgabase, 0x16, 0x08, 0xBF); // FIFO read threshold - vga_wseq(NULL, 0x17, 0x1F); // FIFO depth - vga_wseq(NULL, 0x18, 0x4E); + vga_wseq(par->state.vgabase, 0x17, 0x1F); // FIFO depth + vga_wseq(par->state.vgabase, 0x18, 0x4E); svga_wseq_mask(par->state.vgabase, 0x1A, 0x08, 0x08); // enable MMIO ? - vga_wcrt(NULL, 0x32, 0x00); - vga_wcrt(NULL, 0x34, 0x00); - vga_wcrt(NULL, 0x6A, 0x80); - vga_wcrt(NULL, 0x6A, 0xC0); + vga_wcrt(par->state.vgabase, 0x32, 0x00); + vga_wcrt(par->state.vgabase, 0x34, 0x00); + vga_wcrt(par->state.vgabase, 0x6A, 0x80); + vga_wcrt(par->state.vgabase, 0x6A, 0xC0); - vga_wgfx(NULL, 0x20, 0x00); - vga_wgfx(NULL, 0x21, 0x00); - vga_wgfx(NULL, 0x22, 0x00); + vga_wgfx(par->state.vgabase, 0x20, 0x00); + vga_wgfx(par->state.vgabase, 0x21, 0x00); + vga_wgfx(par->state.vgabase, 0x22, 0x00); /* Set SR15 according to number of bits per pixel */ mode = svga_match_format(vt8623fb_formats, &(info->var), &(info->fix)); @@ -478,7 +478,7 @@ static int vt8623fb_set_par(struct fb_info *info) break; case 1: pr_debug("fb%d: 4 bit pseudocolor\n", info->node); - vga_wgfx(NULL, VGA_GFX_MODE, 0x40); + vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40); svga_wseq_mask(par->state.vgabase, 0x15, 0x20, 0xFE); svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x70); break; @@ -717,8 +717,8 @@ static int __devinit vt8623_pci_probe(struct pci_dev *dev, const struct pci_devi } /* Find how many physical memory there is on card */ - memsize1 = (vga_rseq(NULL, 0x34) + 1) >> 1; - memsize2 = vga_rseq(NULL, 0x39) << 2; + memsize1 = (vga_rseq(par->state.vgabase, 0x34) + 1) >> 1; + memsize2 = vga_rseq(par->state.vgabase, 0x39) << 2; if ((16 <= memsize1) && (memsize1 <= 64) && (memsize1 == memsize2)) info->screen_size = memsize1 << 20; From ec70a9435600a7b4c019671aa0b6e6644b60f0b2 Mon Sep 17 00:00:00 2001 From: David Miller Date: Tue, 11 Jan 2011 23:53:38 +0000 Subject: [PATCH 108/140] arkfb: Don't clobber par->state.vgabase during open method. Signed-off-by: David S. Miller Signed-off-by: Paul Mundt --- drivers/video/arkfb.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/video/arkfb.c b/drivers/video/arkfb.c index 53c66e8dcb0b..1c69db310ed5 100644 --- a/drivers/video/arkfb.c +++ b/drivers/video/arkfb.c @@ -535,7 +535,10 @@ static int arkfb_open(struct fb_info *info, int user) mutex_lock(&(par->open_lock)); if (par->ref_count == 0) { + void __iomem *vgabase = par->state.vgabase; + memset(&(par->state), 0, sizeof(struct vgastate)); + par->state.vgabase = vgabase; par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP; par->state.num_crtc = 0x60; par->state.num_seq = 0x30; From 3ff259f2ed21e4438dc7937348710397e5ebd71e Mon Sep 17 00:00:00 2001 From: David Miller Date: Tue, 11 Jan 2011 23:53:53 +0000 Subject: [PATCH 109/140] s3fb: Don't clobber par->state.vgabase during open method. Signed-off-by: David S. Miller Signed-off-by: Paul Mundt --- drivers/video/s3fb.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/video/s3fb.c b/drivers/video/s3fb.c index 262490a74bb7..b2286f916b5d 100644 --- a/drivers/video/s3fb.c +++ b/drivers/video/s3fb.c @@ -379,7 +379,10 @@ static int s3fb_open(struct fb_info *info, int user) mutex_lock(&(par->open_lock)); if (par->ref_count == 0) { + void __iomem *vgabase = par->state.vgabase; + memset(&(par->state), 0, sizeof(struct vgastate)); + par->state.vgabase = vgabase; par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP; par->state.num_crtc = 0x70; par->state.num_seq = 0x20; From 0144a2568c7d8e58806d3f176f8454c3a3a35ba0 Mon Sep 17 00:00:00 2001 From: David Miller Date: Tue, 11 Jan 2011 23:54:07 +0000 Subject: [PATCH 110/140] vt8623fb: Don't clobber par->state.vgabase during open method. Signed-off-by: David S. Miller Signed-off-by: Paul Mundt --- drivers/video/vt8623fb.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/video/vt8623fb.c b/drivers/video/vt8623fb.c index 54ddaeb60f0a..eee01a2ae8c9 100644 --- a/drivers/video/vt8623fb.c +++ b/drivers/video/vt8623fb.c @@ -292,7 +292,10 @@ static int vt8623fb_open(struct fb_info *info, int user) mutex_lock(&(par->open_lock)); if (par->ref_count == 0) { + void __iomem *vgabase = par->state.vgabase; + memset(&(par->state), 0, sizeof(struct vgastate)); + par->state.vgabase = vgabase; par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP; par->state.num_crtc = 0xA2; par->state.num_seq = 0x50; From 94c322c30bd14ae6cdd369cb4a1f94c5c3809ac9 Mon Sep 17 00:00:00 2001 From: David Miller Date: Tue, 11 Jan 2011 23:54:21 +0000 Subject: [PATCH 111/140] s3fb: Compute VGA base iomem pointer explicitly. This allows the driver to work in multi-domain PCI configurations. Signed-off-by: David S. Miller Signed-off-by: Paul Mundt --- drivers/video/s3fb.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/video/s3fb.c b/drivers/video/s3fb.c index b2286f916b5d..55a94b94a326 100644 --- a/drivers/video/s3fb.c +++ b/drivers/video/s3fb.c @@ -934,6 +934,8 @@ static int __devinit s3_identification(struct s3fb_info *par) static int __devinit s3_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) { + struct pci_bus_region bus_reg; + struct resource vga_res; struct fb_info *info; struct s3fb_info *par; int rc; @@ -983,6 +985,15 @@ static int __devinit s3_pci_probe(struct pci_dev *dev, const struct pci_device_i goto err_iomap; } + bus_reg.start = 0; + bus_reg.end = 64 * 1024; + + vga_res.flags = IORESOURCE_IO; + + pcibios_bus_to_resource(dev, &vga_res, &bus_reg); + + par->state.vgabase = (void __iomem *) vga_res.start; + /* Unlock regs */ cr38 = vga_rcrt(par->state.vgabase, 0x38); cr39 = vga_rcrt(par->state.vgabase, 0x39); From 892c24ca40ffebf6d0ca4cc1454e58db131a4f5a Mon Sep 17 00:00:00 2001 From: David Miller Date: Tue, 11 Jan 2011 23:54:35 +0000 Subject: [PATCH 112/140] arkfb: Compute VGA base iomem pointer explicitly. This allows the driver to work in multi-domain PCI configurations. Signed-off-by: David S. Miller Signed-off-by: Paul Mundt --- drivers/video/arkfb.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/video/arkfb.c b/drivers/video/arkfb.c index 1c69db310ed5..8686429cbdf0 100644 --- a/drivers/video/arkfb.c +++ b/drivers/video/arkfb.c @@ -951,6 +951,8 @@ static struct fb_ops arkfb_ops = { /* PCI probe */ static int __devinit ark_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) { + struct pci_bus_region bus_reg; + struct resource vga_res; struct fb_info *info; struct arkfb_info *par; int rc; @@ -1006,6 +1008,15 @@ static int __devinit ark_pci_probe(struct pci_dev *dev, const struct pci_device_ goto err_iomap; } + bus_reg.start = 0; + bus_reg.end = 64 * 1024; + + vga_res.flags = IORESOURCE_IO; + + pcibios_bus_to_resource(dev, &vga_res, &bus_reg); + + par->state.vgabase = (void __iomem *) vga_res.start; + /* FIXME get memsize */ regval = vga_rseq(par->state.vgabase, 0x10); info->screen_size = (1 << (regval >> 6)) << 20; From 6a2f6d5e970afbc1b8b08bafae9d9138a3206960 Mon Sep 17 00:00:00 2001 From: David Miller Date: Tue, 11 Jan 2011 23:55:17 +0000 Subject: [PATCH 113/140] vt8623fb: Compute VGA base iomem pointer explicitly. This allows the driver to work in multi-domain PCI configurations. Signed-off-by: David S. Miller Signed-off-by: Paul Mundt --- drivers/video/vt8623fb.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/video/vt8623fb.c b/drivers/video/vt8623fb.c index eee01a2ae8c9..f9b3e3dc2421 100644 --- a/drivers/video/vt8623fb.c +++ b/drivers/video/vt8623fb.c @@ -661,6 +661,8 @@ static struct fb_ops vt8623fb_ops = { static int __devinit vt8623_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) { + struct pci_bus_region bus_reg; + struct resource vga_res; struct fb_info *info; struct vt8623fb_info *par; unsigned int memsize1, memsize2; @@ -719,6 +721,15 @@ static int __devinit vt8623_pci_probe(struct pci_dev *dev, const struct pci_devi goto err_iomap_2; } + bus_reg.start = 0; + bus_reg.end = 64 * 1024; + + vga_res.flags = IORESOURCE_IO; + + pcibios_bus_to_resource(dev, &vga_res, &bus_reg); + + par->state.vgabase = (void __iomem *) vga_res.start; + /* Find how many physical memory there is on card */ memsize1 = (vga_rseq(par->state.vgabase, 0x34) + 1) >> 1; memsize2 = vga_rseq(par->state.vgabase, 0x39) << 2; From 99d054d8253b1dbc6ab2d4ebcb25ad4a4e6ba1c8 Mon Sep 17 00:00:00 2001 From: Ondrej Zary Date: Tue, 1 Mar 2011 19:18:08 +0000 Subject: [PATCH 114/140] s3fb: maximize virtual vertical size for fast scrolling Maximize virtual vertical framebuffer size during init to allow fast scrolling (accelerated by panning). Signed-off-by: Ondrej Zary Acked-by: Ondrej Zajicek Signed-off-by: Paul Mundt --- drivers/video/s3fb.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/video/s3fb.c b/drivers/video/s3fb.c index 55a94b94a326..9f9be9f37f2e 100644 --- a/drivers/video/s3fb.c +++ b/drivers/video/s3fb.c @@ -1053,6 +1053,14 @@ static int __devinit s3_pci_probe(struct pci_dev *dev, const struct pci_device_i goto err_find_mode; } + /* maximize virtual vertical size for fast scrolling */ + info->var.yres_virtual = info->fix.smem_len * 8 / + (info->var.bits_per_pixel * info->var.xres_virtual); + if (info->var.yres_virtual < info->var.yres) { + dev_err(info->device, "virtual vertical size smaller than real\n"); + goto err_find_mode; + } + rc = fb_alloc_cmap(&info->cmap, 256, 0); if (rc < 0) { dev_err(info->device, "cannot allocate colormap\n"); From 5694f9ce5801d58bfc1b011592a5e460cc0a274b Mon Sep 17 00:00:00 2001 From: Ondrej Zary Date: Tue, 1 Mar 2011 19:18:17 +0000 Subject: [PATCH 115/140] s3fb: add support for 86C365 Trio3D Add support for S3 Trio3D (86C365) cards to s3fb driver. Tested with one 4MB card. Signed-off-by: Ondrej Zary Acked-by: Ondrej Zajicek Signed-off-by: Paul Mundt --- drivers/video/s3fb.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/video/s3fb.c b/drivers/video/s3fb.c index 9f9be9f37f2e..be12145681f6 100644 --- a/drivers/video/s3fb.c +++ b/drivers/video/s3fb.c @@ -64,6 +64,8 @@ static const struct svga_fb_format s3fb_formats[] = { static const struct svga_pll s3_pll = {3, 129, 3, 33, 0, 3, 35000, 240000, 14318}; +static const struct svga_pll s3_trio3d_pll = {3, 129, 3, 31, 0, 4, + 230000, 460000, 14318}; static const int s3_memsizes[] = {4096, 0, 3072, 8192, 2048, 6144, 1024, 512}; @@ -72,7 +74,8 @@ static const char * const s3_names[] = {"S3 Unknown", "S3 Trio32", "S3 Trio64", "S3 Plato/PX", "S3 Aurora64VP", "S3 Virge", "S3 Virge/VX", "S3 Virge/DX", "S3 Virge/GX", "S3 Virge/GX2", "S3 Virge/GX2P", "S3 Virge/GX2P", - "S3 Trio3D/1X", "S3 Trio3D/2X", "S3 Trio3D/2X"}; + "S3 Trio3D/1X", "S3 Trio3D/2X", "S3 Trio3D/2X", + "S3 Trio3D"}; #define CHIP_UNKNOWN 0x00 #define CHIP_732_TRIO32 0x01 @@ -93,6 +96,7 @@ static const char * const s3_names[] = {"S3 Unknown", "S3 Trio32", "S3 Trio64", #define CHIP_360_TRIO3D_1X 0x10 #define CHIP_362_TRIO3D_2X 0x11 #define CHIP_368_TRIO3D_2X 0x12 +#define CHIP_365_TRIO3D 0x13 #define CHIP_XXX_TRIO 0x80 #define CHIP_XXX_TRIO64V2_DXGX 0x81 @@ -341,7 +345,8 @@ static void s3_set_pixclock(struct fb_info *info, u32 pixclock) u8 regval; int rv; - rv = svga_compute_pll(&s3_pll, 1000000000 / pixclock, &m, &n, &r, info->node); + rv = svga_compute_pll((par->chip == CHIP_365_TRIO3D) ? &s3_trio3d_pll : &s3_pll, + 1000000000 / pixclock, &m, &n, &r, info->node); if (rv < 0) { printk(KERN_ERR "fb%d: cannot set requested pixclock, keeping old value\n", info->node); return; @@ -598,7 +603,8 @@ static int s3fb_set_par(struct fb_info *info) if (par->chip == CHIP_360_TRIO3D_1X || par->chip == CHIP_362_TRIO3D_2X || - par->chip == CHIP_368_TRIO3D_2X) { + par->chip == CHIP_368_TRIO3D_2X || + par->chip == CHIP_365_TRIO3D) { dbytes = info->var.xres * ((bpp+7)/8); vga_wcrt(par->state.vgabase, 0x91, (dbytes + 7) / 8); vga_wcrt(par->state.vgabase, 0x90, (((dbytes + 7) / 8) >> 8) | 0x80); @@ -1012,13 +1018,15 @@ static int __devinit s3_pci_probe(struct pci_dev *dev, const struct pci_device_i regval = vga_rcrt(par->state.vgabase, 0x36); if (par->chip == CHIP_360_TRIO3D_1X || par->chip == CHIP_362_TRIO3D_2X || - par->chip == CHIP_368_TRIO3D_2X) { + par->chip == CHIP_368_TRIO3D_2X || + par->chip == CHIP_365_TRIO3D) { switch ((regval & 0xE0) >> 5) { case 0: /* 8MB -- only 4MB usable for display */ case 1: /* 4MB with 32-bit bus */ case 2: /* 4MB */ info->screen_size = 4 << 20; break; + case 4: /* 2MB on 365 Trio3D */ case 6: /* 2MB */ info->screen_size = 2 << 20; break; @@ -1226,6 +1234,7 @@ static struct pci_device_id s3_devices[] __devinitdata = { {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A11), .driver_data = CHIP_357_VIRGE_GX2P}, {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A12), .driver_data = CHIP_359_VIRGE_GX2P}, {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A13), .driver_data = CHIP_36X_TRIO3D_1X_2X}, + {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8904), .driver_data = CHIP_365_TRIO3D}, {0, 0, 0, 0, 0, 0, 0} }; From 3827d10ed4278323b75bf25d09c146c050519254 Mon Sep 17 00:00:00 2001 From: Ondrej Zary Date: Tue, 1 Mar 2011 19:18:27 +0000 Subject: [PATCH 116/140] s3fb: fix 15/16bpp modes with over 115MHz pixclocks on 86C365 Trio3D Enable pixel multiplexing in 15/16bpp modes when pixclock is over 115MHz on Trio3D (86C365) cards to fix artifacts on the left side of screen. Signed-off-by: Ondrej Zary Acked-by: Ondrej Zajicek Signed-off-by: Paul Mundt --- drivers/video/s3fb.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/video/s3fb.c b/drivers/video/s3fb.c index be12145681f6..7b8fdc6d9d55 100644 --- a/drivers/video/s3fb.c +++ b/drivers/video/s3fb.c @@ -675,6 +675,15 @@ static int s3fb_set_par(struct fb_info *info) svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0); else svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); + } else if (par->chip == CHIP_365_TRIO3D) { + svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); + if (info->var.pixclock > 8695) { + svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); + hmul = 2; + } else { + svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0); + multiplex = 1; + } } else { svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); @@ -691,6 +700,15 @@ static int s3fb_set_par(struct fb_info *info) svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0); else svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); + } else if (par->chip == CHIP_365_TRIO3D) { + svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); + if (info->var.pixclock > 8695) { + svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); + hmul = 2; + } else { + svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0); + multiplex = 1; + } } else { svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); From cb11c048928b519548dbfb7da149dd2521500db0 Mon Sep 17 00:00:00 2001 From: Ondrej Zary Date: Tue, 1 Mar 2011 19:18:35 +0000 Subject: [PATCH 117/140] s3fb: enable DTPC Enable Data Transfer Position Control (DTPC). This is needed at least on Virge/DX to correctly display at higher pixclocks. Signed-off-by: Ondrej Zary Acked-by: Ondrej Zajicek Signed-off-by: Paul Mundt --- drivers/video/s3fb.c | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/drivers/video/s3fb.c b/drivers/video/s3fb.c index 7b8fdc6d9d55..808db19aa5de 100644 --- a/drivers/video/s3fb.c +++ b/drivers/video/s3fb.c @@ -126,6 +126,8 @@ static const struct vga_regset s3_line_compare_regs[] = {{0x18, 0, 7}, {0x07, static const struct vga_regset s3_start_address_regs[] = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x31, 4, 5}, {0x51, 0, 1}, VGA_REGSET_END}; static const struct vga_regset s3_offset_regs[] = {{0x13, 0, 7}, {0x51, 4, 5}, VGA_REGSET_END}; /* set 0x43 bit 2 to 0 */ +static const struct vga_regset s3_dtpc_regs[] = {{0x3B, 0, 7}, {0x5D, 6, 6}, VGA_REGSET_END}; + static const struct svga_timing_regs s3_timing_regs = { s3_h_total_regs, s3_h_display_regs, s3_h_blank_start_regs, s3_h_blank_end_regs, s3_h_sync_start_regs, s3_h_sync_end_regs, @@ -485,6 +487,7 @@ static int s3fb_set_par(struct fb_info *info) struct s3fb_info *par = info->par; u32 value, mode, hmul, offset_value, screen_size, multiplex, dbytes; u32 bpp = info->var.bits_per_pixel; + u32 htotal, hsstart; if (bpp != 0) { info->fix.ypanstep = 1; @@ -604,7 +607,9 @@ static int s3fb_set_par(struct fb_info *info) if (par->chip == CHIP_360_TRIO3D_1X || par->chip == CHIP_362_TRIO3D_2X || par->chip == CHIP_368_TRIO3D_2X || - par->chip == CHIP_365_TRIO3D) { + par->chip == CHIP_365_TRIO3D || + par->chip == CHIP_375_VIRGE_DX || + par->chip == CHIP_385_VIRGE_GX) { dbytes = info->var.xres * ((bpp+7)/8); vga_wcrt(par->state.vgabase, 0x91, (dbytes + 7) / 8); vga_wcrt(par->state.vgabase, 0x90, (((dbytes + 7) / 8) >> 8) | 0x80); @@ -612,6 +617,16 @@ static int s3fb_set_par(struct fb_info *info) vga_wcrt(par->state.vgabase, 0x66, 0x81); } + if (par->chip == CHIP_356_VIRGE_GX2 || + par->chip == CHIP_357_VIRGE_GX2P || + par->chip == CHIP_359_VIRGE_GX2P || + par->chip == CHIP_360_TRIO3D_1X || + par->chip == CHIP_362_TRIO3D_2X || + par->chip == CHIP_368_TRIO3D_2X) + vga_wcrt(par->state.vgabase, 0x34, 0x00); + else /* enable Data Transfer Position Control (DTPC) */ + vga_wcrt(par->state.vgabase, 0x34, 0x10); + svga_wcrt_mask(par->state.vgabase, 0x31, 0x00, 0x40); multiplex = 0; hmul = 1; @@ -745,9 +760,14 @@ static int s3fb_set_par(struct fb_info *info) hmul, info->node); /* Set interlaced mode start/end register */ - value = info->var.xres + info->var.left_margin + info->var.right_margin + info->var.hsync_len; - value = ((value * hmul) / 8) - 5; - vga_wcrt(par->state.vgabase, 0x3C, (value + 1) / 2); + htotal = info->var.xres + info->var.left_margin + info->var.right_margin + info->var.hsync_len; + htotal = ((htotal * hmul) / 8) - 5; + vga_wcrt(par->state.vgabase, 0x3C, (htotal + 1) / 2); + + /* Set Data Transfer Position */ + hsstart = ((info->var.xres + info->var.right_margin) * hmul) / 8; + value = clamp((htotal + hsstart + 1) / 2, hsstart + 4, htotal + 1); + svga_wcrt_multi(par->state.vgabase, s3_dtpc_regs, value); memset_io(info->screen_base, 0x00, screen_size); /* Device and screen back on */ From 7fe029df4245b7765efeebbcfd1b3dfda1432a8e Mon Sep 17 00:00:00 2001 From: Ondrej Zary Date: Tue, 1 Mar 2011 19:18:43 +0000 Subject: [PATCH 118/140] s3fb: use new start address register Use "new" start address register 0x69 (bits 16-20) instead of "old" 0x31 (bits 16-17) and 0x51 (bits 18-19). This is needed for panning to work correctly on Trio3D/2X cards (and does no harm on other ones). Signed-off-by: Ondrej Zary Acked-by: Ondrej Zajicek Signed-off-by: Paul Mundt --- drivers/video/s3fb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/video/s3fb.c b/drivers/video/s3fb.c index 808db19aa5de..ddedad9cd069 100644 --- a/drivers/video/s3fb.c +++ b/drivers/video/s3fb.c @@ -123,7 +123,7 @@ static const struct vga_regset s3_v_sync_start_regs[] = {{0x10, 0, 7}, {0x07, static const struct vga_regset s3_v_sync_end_regs[] = {{0x11, 0, 3}, VGA_REGSET_END}; static const struct vga_regset s3_line_compare_regs[] = {{0x18, 0, 7}, {0x07, 4, 4}, {0x09, 6, 6}, {0x5E, 6, 6}, VGA_REGSET_END}; -static const struct vga_regset s3_start_address_regs[] = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x31, 4, 5}, {0x51, 0, 1}, VGA_REGSET_END}; +static const struct vga_regset s3_start_address_regs[] = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x69, 0, 4}, VGA_REGSET_END}; static const struct vga_regset s3_offset_regs[] = {{0x13, 0, 7}, {0x51, 4, 5}, VGA_REGSET_END}; /* set 0x43 bit 2 to 0 */ static const struct vga_regset s3_dtpc_regs[] = {{0x3B, 0, 7}, {0x5D, 6, 6}, VGA_REGSET_END}; From 56fb22f7ca11ba5f04c297b7f7aa758ac8dbb2ce Mon Sep 17 00:00:00 2001 From: axel lin Date: Sat, 29 Jan 2011 09:33:48 +0000 Subject: [PATCH 119/140] video: hpfb: use resource_size() The size calculation is done incorrectly here because it should include both the start and end (end - start + 1). Signed-off-by: Axel Lin Signed-off-by: Paul Mundt --- drivers/video/hpfb.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/video/hpfb.c b/drivers/video/hpfb.c index c8e280f1bb0b..ebf8495ff198 100644 --- a/drivers/video/hpfb.c +++ b/drivers/video/hpfb.c @@ -321,11 +321,11 @@ static int __devinit hpfb_dio_probe(struct dio_dev * d, const struct dio_device_ unsigned long paddr, vaddr; paddr = d->resource.start; - if (!request_mem_region(d->resource.start, d->resource.end - d->resource.start, d->name)) + if (!request_mem_region(d->resource.start, resource_size(&d->resource), d->name)) return -EBUSY; if (d->scode >= DIOII_SCBASE) { - vaddr = (unsigned long)ioremap(paddr, d->resource.end - d->resource.start); + vaddr = (unsigned long)ioremap(paddr, resource_size(&d->resource)); } else { vaddr = paddr + DIO_VIRADDRBASE; } @@ -344,7 +344,7 @@ static void __devexit hpfb_remove_one(struct dio_dev *d) unregister_framebuffer(&fb_info); if (d->scode >= DIOII_SCBASE) iounmap((void *)fb_regs); - release_mem_region(d->resource.start, d->resource.end - d->resource.start); + release_mem_region(d->resource.start, resource_size(&d->resource)); } static struct dio_device_id hpfb_dio_tbl[] = { From e0998eab678233fae7dff7b92db08ad0f01acf91 Mon Sep 17 00:00:00 2001 From: axel lin Date: Sat, 29 Jan 2011 09:35:45 +0000 Subject: [PATCH 120/140] video: sh7760fb: use resource_size() The size calculation is done incorrectly in request_mem_region because it should include both the start and end (end - start + 1). Signed-off-by: Axel Lin Signed-off-by: Paul Mundt --- drivers/video/sh7760fb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/video/sh7760fb.c b/drivers/video/sh7760fb.c index bea38fce2470..8fe19582c460 100644 --- a/drivers/video/sh7760fb.c +++ b/drivers/video/sh7760fb.c @@ -459,14 +459,14 @@ static int __devinit sh7760fb_probe(struct platform_device *pdev) } par->ioarea = request_mem_region(res->start, - (res->end - res->start), pdev->name); + resource_size(res), pdev->name); if (!par->ioarea) { dev_err(&pdev->dev, "mmio area busy\n"); ret = -EBUSY; goto out_fb; } - par->base = ioremap_nocache(res->start, res->end - res->start + 1); + par->base = ioremap_nocache(res->start, resource_size(res)); if (!par->base) { dev_err(&pdev->dev, "cannot remap\n"); ret = -ENODEV; From beee1f20a185c7e79fd33bb83e04fe44ecd75af3 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Mon, 21 Mar 2011 15:03:13 +0000 Subject: [PATCH 121/140] fbdev: sh_mobile_lcdc: checking NULL instead of IS_ERR() backlight_device_register() returns an ERR_PTR. It doesn't return NULL. Signed-off-by: Dan Carpenter Signed-off-by: Paul Mundt --- drivers/video/sh_mobile_lcdcfb.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/video/sh_mobile_lcdcfb.c b/drivers/video/sh_mobile_lcdcfb.c index bf2629f83f40..757665bc500f 100644 --- a/drivers/video/sh_mobile_lcdcfb.c +++ b/drivers/video/sh_mobile_lcdcfb.c @@ -1088,8 +1088,9 @@ static struct backlight_device *sh_mobile_lcdc_bl_probe(struct device *parent, bl = backlight_device_register(ch->cfg.bl_info.name, parent, ch, &sh_mobile_lcdc_bl_ops, NULL); - if (!bl) { - dev_err(parent, "unable to register backlight device\n"); + if (IS_ERR(bl)) { + dev_err(parent, "unable to register backlight device: %ld\n", + PTR_ERR(bl)); return NULL; } From 49bb0943329929e73c9a22c97d53c6c8967eb243 Mon Sep 17 00:00:00 2001 From: Jean Delvare Date: Thu, 3 Feb 2011 08:23:10 +0000 Subject: [PATCH 122/140] radeonfb: Let hwmon driver probe the "monid" I2C bus Some Radeon cards have an I2C-based thermal sensor chip connected to the "monid" I2C bus. Set the I2C probing class of this bus properly so that hwmon drivers can detect devices on it and bind to them. This closes kernel.org bug #26172. We exclude PPC for the time being, as Benjamin doesn't want us to mess up with them without explicit testing, and there is no evidence that this change is needed for them either. Reported-by: Alexander Goomenyuk Signed-off-by: Jean Delvare Cc: Benjamin Herrenschmidt Signed-off-by: Paul Mundt --- drivers/video/aty/radeon_i2c.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/video/aty/radeon_i2c.c b/drivers/video/aty/radeon_i2c.c index 78d1f4cd1fe0..ab1d0fd76316 100644 --- a/drivers/video/aty/radeon_i2c.c +++ b/drivers/video/aty/radeon_i2c.c @@ -100,6 +100,9 @@ void radeon_create_i2c_busses(struct radeonfb_info *rinfo) { rinfo->i2c[0].rinfo = rinfo; rinfo->i2c[0].ddc_reg = GPIO_MONID; +#ifndef CONFIG_PPC + rinfo->i2c[0].adapter.class = I2C_CLASS_HWMON; +#endif radeon_setup_i2c_bus(&rinfo->i2c[0], "monid"); rinfo->i2c[1].rinfo = rinfo; From 7b0e278519eba8050f2b37d7c408958745f30ecd Mon Sep 17 00:00:00 2001 From: axel lin Date: Tue, 8 Feb 2011 14:58:45 +0000 Subject: [PATCH 123/140] video: ffb: fix ffb_probe error path Current implementation calls of_iounmap for par->fbc twice in error path. In the case of goto out_unmap_dac, we should call of_iounmap for par->dac. Signed-off-by: Axel Lin Acked-by: David S. Miller Signed-off-by: Paul Mundt --- drivers/video/ffb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/video/ffb.c b/drivers/video/ffb.c index 910c5e6f6702..14102a3f70f5 100644 --- a/drivers/video/ffb.c +++ b/drivers/video/ffb.c @@ -1010,7 +1010,7 @@ out_dealloc_cmap: fb_dealloc_cmap(&info->cmap); out_unmap_dac: - of_iounmap(&op->resource[2], par->fbc, sizeof(struct ffb_fbc)); + of_iounmap(&op->resource[1], par->dac, sizeof(struct ffb_dac)); out_unmap_fbc: of_iounmap(&op->resource[2], par->fbc, sizeof(struct ffb_fbc)); From 803a4e14a7dceaf01dbc0e02c0fdea2eba4c81b3 Mon Sep 17 00:00:00 2001 From: Thomas Schlichter Date: Sat, 27 Nov 2010 14:17:55 +0100 Subject: [PATCH 124/140] uvesafb,vesafb: create WC or WB PAT-entries with an PAT-enabled kernel, when using uvesafb or vesafb, these drivers will create uncached-minus PAT entries for the framebuffer memory because they use ioremap() (not the *_cache or *_wc variants). When the framebuffer memory intersects with the video RAM used by Xorg, the complete video RAM will be mapped uncached-minus what results in a serve performance penalty. Here are the correct MTRR entries created by uvesafb: schlicht@netbook:~$ cat /proc/mtrr reg00: base=0x000000000 ( 0MB), size= 2048MB, count=1: write-back reg01: base=0x06ff00000 ( 1791MB), size= 1MB, count=1: uncachable reg02: base=0x070000000 ( 1792MB), size= 256MB, count=1: uncachable reg03: base=0x0d0000000 ( 3328MB), size= 16MB, count=1: write-combining And here are the problematic PAT entries: schlicht@netbook:~$ sudo cat /sys/kernel/debug/x86/pat_memtype_list PAT memtype list: write-back @ 0x0-0x1000 uncached-minus @ 0x6fedd000-0x6fee3000 uncached-minus @ 0x6fee2000-0x6fee3000 uncached-minus @ 0x6fee2000-0x6fee3000 uncached-minus @ 0x6fee2000-0x6fee3000 uncached-minus @ 0x6fee2000-0x6fee3000 uncached-minus @ 0x6fee2000-0x6fee3000 uncached-minus @ 0x6fee2000-0x6fee3000 uncached-minus @ 0x6fee2000-0x6fee3000 uncached-minus @ 0x6fee3000-0x6fee4000 uncached-minus @ 0x6fee3000-0x6fee4000 uncached-minus @ 0x6fee3000-0x6fee4000 uncached-minus @ 0xd0000000-0xe0000000 <-- created by xserver-xorg uncached-minus @ 0xd0000000-0xd1194000 <-- created by uvesafb uncached-minus @ 0xf4000000-0xf4009000 uncached-minus @ 0xf4200000-0xf4400000 uncached-minus @ 0xf5000000-0xf5010000 uncached-minus @ 0xf5100000-0xf5104000 uncached-minus @ 0xf5400000-0xf5404000 uncached-minus @ 0xf5404000-0xf5405000 uncached-minus @ 0xf5404000-0xf5405000 uncached-minus @ 0xfed00000-0xfed01000 Therefore I created the attached patch for uvesafb which uses ioremap_wc() to create the correct PAT entries, as shown below: schlicht@netbook:~$ sudo cat /sys/kernel/debug/x86/pat_memtype_list PAT memtype list: write-back @ 0x0-0x1000 uncached-minus @ 0x6fedd000-0x6fee3000 uncached-minus @ 0x6fee2000-0x6fee3000 uncached-minus @ 0x6fee2000-0x6fee3000 uncached-minus @ 0x6fee2000-0x6fee3000 uncached-minus @ 0x6fee2000-0x6fee3000 uncached-minus @ 0x6fee2000-0x6fee3000 uncached-minus @ 0x6fee2000-0x6fee3000 uncached-minus @ 0x6fee2000-0x6fee3000 uncached-minus @ 0x6fee3000-0x6fee4000 uncached-minus @ 0x6fee3000-0x6fee4000 uncached-minus @ 0x6fee3000-0x6fee4000 write-combining @ 0xd0000000-0xe0000000 write-combining @ 0xd0000000-0xd1194000 uncached-minus @ 0xf4000000-0xf4009000 uncached-minus @ 0xf4200000-0xf4400000 uncached-minus @ 0xf5000000-0xf5010000 uncached-minus @ 0xf5100000-0xf5104000 uncached-minus @ 0xf5400000-0xf5404000 uncached-minus @ 0xf5404000-0xf5405000 uncached-minus @ 0xf5404000-0xf5405000 uncached-minus @ 0xfed00000-0xfed01000 This results in a performance gain, objectively measurable with e.g. x11perf -comppixwin10 -comppixwin100 -comppixwin500: 1: x11perf_xaa.log 2: x11perf_xaa_patched.log 1 2 Operation -------- ---------------- ----------------- 124000.0 202000.0 ( 1.63) Composite 10x10 from pixmap to window 3340.0 24400.0 ( 7.31) Composite 100x100 from pixmap to window 131.0 1150.0 ( 8.78) Composite 500x500 from pixmap to window You can see the serve performance gain when composing larger pixmaps to window. The patches replace the ioremap() function with the variant matching the mtrr- parameter. To create "write-back" PAT entries, the ioremap_cache() function must be called after creating the MTRR entries, and the ioremap_cache() region must completely fit into the MTRR region, this is why the MTRR region size is now rounded up to the next power-of-two. Signed-off-by: Thomas Schlichter Signed-off-by: Paul Mundt --- drivers/video/uvesafb.c | 49 +++++++++++++++++++++++++++++------------ drivers/video/vesafb.c | 44 +++++++++++++++++++++++------------- 2 files changed, 64 insertions(+), 29 deletions(-) diff --git a/drivers/video/uvesafb.c b/drivers/video/uvesafb.c index 5180a215d781..7f8472cc993b 100644 --- a/drivers/video/uvesafb.c +++ b/drivers/video/uvesafb.c @@ -1552,8 +1552,7 @@ static void __devinit uvesafb_init_mtrr(struct fb_info *info) int rc; /* Find the largest power-of-two */ - while (temp_size & (temp_size - 1)) - temp_size &= (temp_size - 1); + temp_size = roundup_pow_of_two(temp_size); /* Try and find a power of two to add */ do { @@ -1566,6 +1565,28 @@ static void __devinit uvesafb_init_mtrr(struct fb_info *info) #endif /* CONFIG_MTRR */ } +static void __devinit uvesafb_ioremap(struct fb_info *info) +{ +#ifdef CONFIG_X86 + switch (mtrr) { + case 1: /* uncachable */ + info->screen_base = ioremap_nocache(info->fix.smem_start, info->fix.smem_len); + break; + case 2: /* write-back */ + info->screen_base = ioremap_cache(info->fix.smem_start, info->fix.smem_len); + break; + case 3: /* write-combining */ + info->screen_base = ioremap_wc(info->fix.smem_start, info->fix.smem_len); + break; + case 4: /* write-through */ + default: + info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len); + break; + } +#else + info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len); +#endif /* CONFIG_X86 */ +} static ssize_t uvesafb_show_vbe_ver(struct device *dev, struct device_attribute *attr, char *buf) @@ -1736,15 +1757,22 @@ static int __devinit uvesafb_probe(struct platform_device *dev) uvesafb_init_info(info, mode); + if (!request_region(0x3c0, 32, "uvesafb")) { + printk(KERN_ERR "uvesafb: request region 0x3c0-0x3e0 failed\n"); + err = -EIO; + goto out_mode; + } + if (!request_mem_region(info->fix.smem_start, info->fix.smem_len, "uvesafb")) { printk(KERN_ERR "uvesafb: cannot reserve video memory at " "0x%lx\n", info->fix.smem_start); err = -EIO; - goto out_mode; + goto out_reg; } - info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len); + uvesafb_init_mtrr(info); + uvesafb_ioremap(info); if (!info->screen_base) { printk(KERN_ERR @@ -1755,20 +1783,13 @@ static int __devinit uvesafb_probe(struct platform_device *dev) goto out_mem; } - if (!request_region(0x3c0, 32, "uvesafb")) { - printk(KERN_ERR "uvesafb: request region 0x3c0-0x3e0 failed\n"); - err = -EIO; - goto out_unmap; - } - - uvesafb_init_mtrr(info); platform_set_drvdata(dev, info); if (register_framebuffer(info) < 0) { printk(KERN_ERR "uvesafb: failed to register framebuffer device\n"); err = -EINVAL; - goto out_reg; + goto out_unmap; } printk(KERN_INFO "uvesafb: framebuffer at 0x%lx, mapped to 0x%p, " @@ -1785,12 +1806,12 @@ static int __devinit uvesafb_probe(struct platform_device *dev) return 0; -out_reg: - release_region(0x3c0, 32); out_unmap: iounmap(info->screen_base); out_mem: release_mem_region(info->fix.smem_start, info->fix.smem_len); +out_reg: + release_region(0x3c0, 32); out_mode: if (!list_empty(&info->modelist)) fb_destroy_modelist(&info->modelist); diff --git a/drivers/video/vesafb.c b/drivers/video/vesafb.c index 6a069d047914..a99bbe86db13 100644 --- a/drivers/video/vesafb.c +++ b/drivers/video/vesafb.c @@ -303,19 +303,6 @@ static int __init vesafb_probe(struct platform_device *dev) info->apertures->ranges[0].base = screen_info.lfb_base; info->apertures->ranges[0].size = size_total; - info->screen_base = ioremap(vesafb_fix.smem_start, vesafb_fix.smem_len); - if (!info->screen_base) { - printk(KERN_ERR - "vesafb: abort, cannot ioremap video memory 0x%x @ 0x%lx\n", - vesafb_fix.smem_len, vesafb_fix.smem_start); - err = -EIO; - goto err; - } - - printk(KERN_INFO "vesafb: framebuffer at 0x%lx, mapped to 0x%p, " - "using %dk, total %dk\n", - vesafb_fix.smem_start, info->screen_base, - size_remap/1024, size_total/1024); printk(KERN_INFO "vesafb: mode is %dx%dx%d, linelength=%d, pages=%d\n", vesafb_defined.xres, vesafb_defined.yres, vesafb_defined.bits_per_pixel, vesafb_fix.line_length, screen_info.pages); @@ -438,8 +425,7 @@ static int __init vesafb_probe(struct platform_device *dev) int rc; /* Find the largest power-of-two */ - while (temp_size & (temp_size - 1)) - temp_size &= (temp_size - 1); + temp_size = roundup_pow_of_two(temp_size); /* Try and find a power of two to add */ do { @@ -451,6 +437,34 @@ static int __init vesafb_probe(struct platform_device *dev) } #endif + switch (mtrr) { + case 1: /* uncachable */ + info->screen_base = ioremap_nocache(vesafb_fix.smem_start, vesafb_fix.smem_len); + break; + case 2: /* write-back */ + info->screen_base = ioremap_cache(vesafb_fix.smem_start, vesafb_fix.smem_len); + break; + case 3: /* write-combining */ + info->screen_base = ioremap_wc(vesafb_fix.smem_start, vesafb_fix.smem_len); + break; + case 4: /* write-through */ + default: + info->screen_base = ioremap(vesafb_fix.smem_start, vesafb_fix.smem_len); + break; + } + if (!info->screen_base) { + printk(KERN_ERR + "vesafb: abort, cannot ioremap video memory 0x%x @ 0x%lx\n", + vesafb_fix.smem_len, vesafb_fix.smem_start); + err = -EIO; + goto err; + } + + printk(KERN_INFO "vesafb: framebuffer at 0x%lx, mapped to 0x%p, " + "using %dk, total %dk\n", + vesafb_fix.smem_start, info->screen_base, + size_remap/1024, size_total/1024); + info->fbops = &vesafb_ops; info->var = vesafb_defined; info->fix = vesafb_fix; From 942b8d05cdf1da396b4449a38b87c677591947c0 Mon Sep 17 00:00:00 2001 From: axel lin Date: Fri, 11 Feb 2011 08:51:10 +0000 Subject: [PATCH 125/140] video: s3c-fb: return proper error if clk_get fails Return PTR_ERR(sfb->bus_clk) instead of 0 if clk_get fails. Signed-off-by: Axel Lin Acked-by: Kyungmin Park Signed-off-by: Paul Mundt --- drivers/video/s3c-fb.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c index 83ce9a04d872..6817d187d46e 100644 --- a/drivers/video/s3c-fb.c +++ b/drivers/video/s3c-fb.c @@ -1340,6 +1340,7 @@ static int __devinit s3c_fb_probe(struct platform_device *pdev) sfb->bus_clk = clk_get(dev, "lcd"); if (IS_ERR(sfb->bus_clk)) { dev_err(dev, "failed to get bus clock\n"); + ret = PTR_ERR(sfb->bus_clk); goto err_sfb; } From 7cdcdb69bdf51192bcbfb7cf479850fe7c33357d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20Bie=C3=9Fmann?= Date: Fri, 11 Feb 2011 15:19:43 +0000 Subject: [PATCH 126/140] atmel_lcdfb: implement inverted contrast pwm MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch introduces lcdc->lcdcon_pol_negative which set CONTRAST_CTR register to inverted polarity. Signed-off-by: Andreas Bießmann Signed-off-by: Paul Mundt --- drivers/video/atmel_lcdfb.c | 7 ++++++- include/video/atmel_lcdc.h | 1 + 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c index bac163450216..16da8af7425c 100644 --- a/drivers/video/atmel_lcdfb.c +++ b/drivers/video/atmel_lcdfb.c @@ -68,7 +68,7 @@ static void atmel_lcdfb_update_dma2d(struct atmel_lcdfb_info *sinfo, } #endif -static const u32 contrast_ctr = ATMEL_LCDC_PS_DIV8 +static u32 contrast_ctr = ATMEL_LCDC_PS_DIV8 | ATMEL_LCDC_POL_POSITIVE | ATMEL_LCDC_ENA_PWMENABLE; @@ -163,6 +163,10 @@ static void exit_backlight(struct atmel_lcdfb_info *sinfo) static void init_contrast(struct atmel_lcdfb_info *sinfo) { + /* contrast pwm can be 'inverted' */ + if (sinfo->lcdcon_pol_negative) + contrast_ctr &= ~(ATMEL_LCDC_POL_POSITIVE); + /* have some default contrast/backlight settings */ lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, contrast_ctr); lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT); @@ -816,6 +820,7 @@ static int __init atmel_lcdfb_probe(struct platform_device *pdev) sinfo->guard_time = pdata_sinfo->guard_time; sinfo->smem_len = pdata_sinfo->smem_len; sinfo->lcdcon_is_backlight = pdata_sinfo->lcdcon_is_backlight; + sinfo->lcdcon_pol_negative = pdata_sinfo->lcdcon_pol_negative; sinfo->lcd_wiring_mode = pdata_sinfo->lcd_wiring_mode; } else { dev_err(dev, "cannot get default configuration\n"); diff --git a/include/video/atmel_lcdc.h b/include/video/atmel_lcdc.h index 0c864db1a466..28447f1594fa 100644 --- a/include/video/atmel_lcdc.h +++ b/include/video/atmel_lcdc.h @@ -52,6 +52,7 @@ struct atmel_lcdfb_info { u8 bl_power; #endif bool lcdcon_is_backlight; + bool lcdcon_pol_negative; u8 saved_lcdcon; u8 default_bpp; From bed7bddbb434df0e76ffe2ff8cb535fe8f3c0c69 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20Bie=C3=9Fmann?= Date: Fri, 11 Feb 2011 15:19:44 +0000 Subject: [PATCH 127/140] atmel_lcdfb: add fb_blank function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andreas Bießmann Signed-off-by: Paul Mundt --- drivers/video/atmel_lcdfb.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c index 16da8af7425c..59654e29e205 100644 --- a/drivers/video/atmel_lcdfb.c +++ b/drivers/video/atmel_lcdfb.c @@ -714,11 +714,35 @@ static int atmel_lcdfb_pan_display(struct fb_var_screeninfo *var, return 0; } +static int atmel_lcdfb_blank(int blank_mode, struct fb_info *info) +{ + struct atmel_lcdfb_info *sinfo = info->par; + + switch (blank_mode) { + case FB_BLANK_UNBLANK: + case FB_BLANK_NORMAL: + atmel_lcdfb_start(sinfo); + break; + case FB_BLANK_VSYNC_SUSPEND: + case FB_BLANK_HSYNC_SUSPEND: + break; + case FB_BLANK_POWERDOWN: + atmel_lcdfb_stop(sinfo); + break; + default: + return -EINVAL; + } + + /* let fbcon do a soft blank for us */ + return ((blank_mode == FB_BLANK_NORMAL) ? 1 : 0); +} + static struct fb_ops atmel_lcdfb_ops = { .owner = THIS_MODULE, .fb_check_var = atmel_lcdfb_check_var, .fb_set_par = atmel_lcdfb_set_par, .fb_setcolreg = atmel_lcdfb_setcolreg, + .fb_blank = atmel_lcdfb_blank, .fb_pan_display = atmel_lcdfb_pan_display, .fb_fillrect = cfb_fillrect, .fb_copyarea = cfb_copyarea, From 83e61f71d72da7240378fe7ecba5e936a0f159db Mon Sep 17 00:00:00 2001 From: "Justin P. Mattock" Date: Wed, 16 Feb 2011 06:55:38 +0000 Subject: [PATCH 128/140] drivers:video:aty:radeon_base Fix typo occationally to occasionally The below patch fixes a typo occationally to occasionally. Signed-off-by: Justin P. Mattock Signed-off-by: Paul Mundt --- drivers/gpu/drm/radeon/radeon_legacy_crtc.c | 2 +- drivers/video/aty/radeon_base.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c index 66c9af1b3d96..41a5d48e657b 100644 --- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c +++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c @@ -889,7 +889,7 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) } if (rdev->flags & RADEON_IS_MOBILITY) { - /* A temporal workaround for the occational blanking on certain laptop panels. + /* A temporal workaround for the occasional blanking on certain laptop panels. This appears to related to the PLL divider registers (fail to lock?). It occurs even when all dividers are the same with their old settings. In this case we really don't need to fiddle with PLL registers. diff --git a/drivers/video/aty/radeon_base.c b/drivers/video/aty/radeon_base.c index 3c1e13ed1cba..32f8cf6200a7 100644 --- a/drivers/video/aty/radeon_base.c +++ b/drivers/video/aty/radeon_base.c @@ -1248,7 +1248,7 @@ static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_reg /* Workaround from XFree */ if (rinfo->is_mobility) { - /* A temporal workaround for the occational blanking on certain laptop + /* A temporal workaround for the occasional blanking on certain laptop * panels. This appears to related to the PLL divider registers * (fail to lock?). It occurs even when all dividers are the same * with their old settings. In this case we really don't need to From 79ac33ec845c1872a23169644c5867528ff05590 Mon Sep 17 00:00:00 2001 From: axel lin Date: Sun, 13 Feb 2011 13:06:23 +0000 Subject: [PATCH 129/140] video: hecubafb: add __devexit_p around reference to hecubafb_remove hecubafb_remove is marked __devexit, thus add __devexit_p around reference to hecubafb_remove. Signed-off-by: Axel Lin Signed-off-by: Paul Mundt --- drivers/video/hecubafb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/video/hecubafb.c b/drivers/video/hecubafb.c index c77bcc6ab463..1b94643ecbcf 100644 --- a/drivers/video/hecubafb.c +++ b/drivers/video/hecubafb.c @@ -299,7 +299,7 @@ static int __devexit hecubafb_remove(struct platform_device *dev) static struct platform_driver hecubafb_driver = { .probe = hecubafb_probe, - .remove = hecubafb_remove, + .remove = __devexit_p(hecubafb_remove), .driver = { .owner = THIS_MODULE, .name = "hecubafb", From 1e93f390e56d82c4fcf684c86a45e1c593dc4b28 Mon Sep 17 00:00:00 2001 From: axel lin Date: Sun, 13 Feb 2011 04:02:10 +0000 Subject: [PATCH 130/140] video: metronomefb: add __devexit_p around reference to metronomefb_remove metronomefb_remove is marked __devexit, thus add __devexit_p around reference to metronomefb_remove. Signed-off-by: Axel Lin Signed-off-by: Paul Mundt --- drivers/video/metronomefb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/video/metronomefb.c b/drivers/video/metronomefb.c index 63ed3b72b01c..ed64edfd2c43 100644 --- a/drivers/video/metronomefb.c +++ b/drivers/video/metronomefb.c @@ -765,7 +765,7 @@ static int __devexit metronomefb_remove(struct platform_device *dev) static struct platform_driver metronomefb_driver = { .probe = metronomefb_probe, - .remove = metronomefb_remove, + .remove = __devexit_p(metronomefb_remove), .driver = { .owner = THIS_MODULE, .name = "metronomefb", From 6359691d7efc639bf0f996aa9a694b2653fc6ae6 Mon Sep 17 00:00:00 2001 From: axel lin Date: Tue, 15 Feb 2011 09:35:02 +0000 Subject: [PATCH 131/140] video: add missing framebuffer_release in error path This patch fixes a memory leak in the error path. Signed-off-by: Axel Lin Acked-by: David S. Miller Signed-off-by: Paul Mundt --- drivers/video/cg14.c | 1 + drivers/video/cg6.c | 1 + drivers/video/tcx.c | 1 + 3 files changed, 3 insertions(+) diff --git a/drivers/video/cg14.c b/drivers/video/cg14.c index e2c85b0db632..f18895006627 100644 --- a/drivers/video/cg14.c +++ b/drivers/video/cg14.c @@ -565,6 +565,7 @@ out_dealloc_cmap: out_unmap_regs: cg14_unmap_regs(op, info, par); + framebuffer_release(info); out_err: return err; diff --git a/drivers/video/cg6.c b/drivers/video/cg6.c index 4ffad90bde42..179e96cdb323 100644 --- a/drivers/video/cg6.c +++ b/drivers/video/cg6.c @@ -821,6 +821,7 @@ out_dealloc_cmap: out_unmap_regs: cg6_unmap_regs(op, info, par); + framebuffer_release(info); out_err: return err; diff --git a/drivers/video/tcx.c b/drivers/video/tcx.c index 855b71993f61..07c66e946634 100644 --- a/drivers/video/tcx.c +++ b/drivers/video/tcx.c @@ -480,6 +480,7 @@ out_dealloc_cmap: out_unmap_regs: tcx_unmap_regs(op, info, par); + framebuffer_release(info); out_err: return err; From d6244bc0ed0c52a795e6f4dcab3886daf3e74fac Mon Sep 17 00:00:00 2001 From: Henry Nestler Date: Sun, 20 Feb 2011 20:50:56 +0000 Subject: [PATCH 132/140] fbcon: Bugfix soft cursor detection in Tile Blitting Use mask 0x10 for "soft cursor" detection on in function tile_cursor. (Tile Blitting Operation in framebuffer console). The old mask 0x01 for vc_cursor_type detects CUR_NONE, CUR_LOWER_THIRD and every second mode value as "software cursor". This hides the cursor for these modes (cursor.mode = 0). But, only CUR_NONE or "software cursor" should hide the cursor. See also 0x10 in functions add_softcursor, bit_cursor and cw_cursor. Signed-off-by: Henry Nestler Cc: stable@kernel.org Signed-off-by: Paul Mundt --- drivers/video/console/tileblit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/video/console/tileblit.c b/drivers/video/console/tileblit.c index 0056a41e5c35..15e8e1a89c45 100644 --- a/drivers/video/console/tileblit.c +++ b/drivers/video/console/tileblit.c @@ -83,7 +83,7 @@ static void tile_cursor(struct vc_data *vc, struct fb_info *info, int mode, int softback_lines, int fg, int bg) { struct fb_tilecursor cursor; - int use_sw = (vc->vc_cursor_type & 0x01); + int use_sw = (vc->vc_cursor_type & 0x10); cursor.sx = vc->vc_x; cursor.sy = vc->vc_y; From dfc906daeec03b3f2d306ae260d398d97ba232c5 Mon Sep 17 00:00:00 2001 From: Martin Decky Date: Sun, 13 Feb 2011 19:28:40 +0000 Subject: [PATCH 133/140] video: Fix EDID macros H_SYNC_WIDTH and H_SYNC_OFFSET The macros for getting the values for horizontal sync width and offset do not respect the EDID specification. Both these values are 10 bit values according to [1], not 6 bit values. The lower 8 bits are stored in byte 8 and byte 9 of the DTD respectively, while two additional bits for each value are stored in byte 11. The original macros just slammed the bits together. Although the original macros usually worked fine because the higher two bits are rarely used, it can cause severe problems on plasma panels running at 1920x1080 @ 50 Hz with drivers that rely on the correct parsing of the EDID data by fbmon.c (e.g. udlfb). The patch should apply cleanly to both the fbdev-2.6.git branch and linux-next.git branch. [1] VESA Enhanced Extended Display Identification Data Standard, Release A, Revision 2, page 34, notes 7 & 8, VESA, Sep 2006 Signed-off-by: Martin Decky Signed-off-by: Paul Mundt --- drivers/video/edid.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/video/edid.h b/drivers/video/edid.h index bd89fb3be8c2..d03a232d90b2 100644 --- a/drivers/video/edid.h +++ b/drivers/video/edid.h @@ -101,8 +101,8 @@ #define V_SYNC_WIDTH COMBINE_HI_4LO( V_SYNC_WIDTH_HI, V_SYNC_WIDTH_LO ) #define V_SYNC_OFFSET COMBINE_HI_4LO( V_SYNC_OFFSET_HI, V_SYNC_OFFSET_LO ) -#define H_SYNC_WIDTH COMBINE_HI_4LO( H_SYNC_WIDTH_HI, H_SYNC_WIDTH_LO ) -#define H_SYNC_OFFSET COMBINE_HI_4LO( H_SYNC_OFFSET_HI, H_SYNC_OFFSET_LO ) +#define H_SYNC_WIDTH COMBINE_HI_8LO( H_SYNC_WIDTH_HI, H_SYNC_WIDTH_LO ) +#define H_SYNC_OFFSET COMBINE_HI_8LO( H_SYNC_OFFSET_HI, H_SYNC_OFFSET_LO ) #define H_SIZE_LO (unsigned)block[ 12 ] #define V_SIZE_LO (unsigned)block[ 13 ] From bf5f0019046d596d613caf74722ba4994e153899 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Mon, 24 Jan 2011 09:57:20 +0000 Subject: [PATCH 134/140] video, sm501: add I/O functions for use on powerpc - add read/write functions for using this driver also on powerpc plattforms Signed-off-by: Heiko Schocher cc: linux-fbdev@vger.kernel.org cc: devicetree-discuss@ozlabs.org cc: Ben Dooks cc: Vincent Sanders cc: Samuel Ortiz cc: linux-kernel@vger.kernel.org cc: Randy Dunlap cc: Paul Mundt Acked-by: Samuel Ortiz Signed-off-by: Paul Mundt --- drivers/mfd/sm501.c | 125 ++++++++++++++--------------- drivers/video/sm501fb.c | 172 +++++++++++++++++++++------------------- include/linux/sm501.h | 8 ++ 3 files changed, 161 insertions(+), 144 deletions(-) diff --git a/drivers/mfd/sm501.c b/drivers/mfd/sm501.c index 5de3a760ea1e..558d5f3f6d02 100644 --- a/drivers/mfd/sm501.c +++ b/drivers/mfd/sm501.c @@ -133,10 +133,10 @@ static unsigned long decode_div(unsigned long pll2, unsigned long val, static void sm501_dump_clk(struct sm501_devdata *sm) { - unsigned long misct = readl(sm->regs + SM501_MISC_TIMING); - unsigned long pm0 = readl(sm->regs + SM501_POWER_MODE_0_CLOCK); - unsigned long pm1 = readl(sm->regs + SM501_POWER_MODE_1_CLOCK); - unsigned long pmc = readl(sm->regs + SM501_POWER_MODE_CONTROL); + unsigned long misct = smc501_readl(sm->regs + SM501_MISC_TIMING); + unsigned long pm0 = smc501_readl(sm->regs + SM501_POWER_MODE_0_CLOCK); + unsigned long pm1 = smc501_readl(sm->regs + SM501_POWER_MODE_1_CLOCK); + unsigned long pmc = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL); unsigned long sdclk0, sdclk1; unsigned long pll2 = 0; @@ -193,29 +193,29 @@ static void sm501_dump_regs(struct sm501_devdata *sm) void __iomem *regs = sm->regs; dev_info(sm->dev, "System Control %08x\n", - readl(regs + SM501_SYSTEM_CONTROL)); + smc501_readl(regs + SM501_SYSTEM_CONTROL)); dev_info(sm->dev, "Misc Control %08x\n", - readl(regs + SM501_MISC_CONTROL)); + smc501_readl(regs + SM501_MISC_CONTROL)); dev_info(sm->dev, "GPIO Control Low %08x\n", - readl(regs + SM501_GPIO31_0_CONTROL)); + smc501_readl(regs + SM501_GPIO31_0_CONTROL)); dev_info(sm->dev, "GPIO Control Hi %08x\n", - readl(regs + SM501_GPIO63_32_CONTROL)); + smc501_readl(regs + SM501_GPIO63_32_CONTROL)); dev_info(sm->dev, "DRAM Control %08x\n", - readl(regs + SM501_DRAM_CONTROL)); + smc501_readl(regs + SM501_DRAM_CONTROL)); dev_info(sm->dev, "Arbitration Ctrl %08x\n", - readl(regs + SM501_ARBTRTN_CONTROL)); + smc501_readl(regs + SM501_ARBTRTN_CONTROL)); dev_info(sm->dev, "Misc Timing %08x\n", - readl(regs + SM501_MISC_TIMING)); + smc501_readl(regs + SM501_MISC_TIMING)); } static void sm501_dump_gate(struct sm501_devdata *sm) { dev_info(sm->dev, "CurrentGate %08x\n", - readl(sm->regs + SM501_CURRENT_GATE)); + smc501_readl(sm->regs + SM501_CURRENT_GATE)); dev_info(sm->dev, "CurrentClock %08x\n", - readl(sm->regs + SM501_CURRENT_CLOCK)); + smc501_readl(sm->regs + SM501_CURRENT_CLOCK)); dev_info(sm->dev, "PowerModeControl %08x\n", - readl(sm->regs + SM501_POWER_MODE_CONTROL)); + smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL)); } #else @@ -231,7 +231,7 @@ static inline void sm501_dump_clk(struct sm501_devdata *sm) { } static void sm501_sync_regs(struct sm501_devdata *sm) { - readl(sm->regs); + smc501_readl(sm->regs); } static inline void sm501_mdelay(struct sm501_devdata *sm, unsigned int delay) @@ -261,11 +261,11 @@ int sm501_misc_control(struct device *dev, spin_lock_irqsave(&sm->reg_lock, save); - misc = readl(sm->regs + SM501_MISC_CONTROL); + misc = smc501_readl(sm->regs + SM501_MISC_CONTROL); to = (misc & ~clear) | set; if (to != misc) { - writel(to, sm->regs + SM501_MISC_CONTROL); + smc501_writel(to, sm->regs + SM501_MISC_CONTROL); sm501_sync_regs(sm); dev_dbg(sm->dev, "MISC_CONTROL %08lx\n", misc); @@ -294,11 +294,11 @@ unsigned long sm501_modify_reg(struct device *dev, spin_lock_irqsave(&sm->reg_lock, save); - data = readl(sm->regs + reg); + data = smc501_readl(sm->regs + reg); data |= set; data &= ~clear; - writel(data, sm->regs + reg); + smc501_writel(data, sm->regs + reg); sm501_sync_regs(sm); spin_unlock_irqrestore(&sm->reg_lock, save); @@ -322,9 +322,9 @@ int sm501_unit_power(struct device *dev, unsigned int unit, unsigned int to) mutex_lock(&sm->clock_lock); - mode = readl(sm->regs + SM501_POWER_MODE_CONTROL); - gate = readl(sm->regs + SM501_CURRENT_GATE); - clock = readl(sm->regs + SM501_CURRENT_CLOCK); + mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL); + gate = smc501_readl(sm->regs + SM501_CURRENT_GATE); + clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK); mode &= 3; /* get current power mode */ @@ -356,14 +356,14 @@ int sm501_unit_power(struct device *dev, unsigned int unit, unsigned int to) switch (mode) { case 1: - writel(gate, sm->regs + SM501_POWER_MODE_0_GATE); - writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK); + smc501_writel(gate, sm->regs + SM501_POWER_MODE_0_GATE); + smc501_writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK); mode = 0; break; case 2: case 0: - writel(gate, sm->regs + SM501_POWER_MODE_1_GATE); - writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK); + smc501_writel(gate, sm->regs + SM501_POWER_MODE_1_GATE); + smc501_writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK); mode = 1; break; @@ -372,7 +372,7 @@ int sm501_unit_power(struct device *dev, unsigned int unit, unsigned int to) goto already; } - writel(mode, sm->regs + SM501_POWER_MODE_CONTROL); + smc501_writel(mode, sm->regs + SM501_POWER_MODE_CONTROL); sm501_sync_regs(sm); dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n", @@ -519,9 +519,9 @@ unsigned long sm501_set_clock(struct device *dev, unsigned long req_freq) { struct sm501_devdata *sm = dev_get_drvdata(dev); - unsigned long mode = readl(sm->regs + SM501_POWER_MODE_CONTROL); - unsigned long gate = readl(sm->regs + SM501_CURRENT_GATE); - unsigned long clock = readl(sm->regs + SM501_CURRENT_CLOCK); + unsigned long mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL); + unsigned long gate = smc501_readl(sm->regs + SM501_CURRENT_GATE); + unsigned long clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK); unsigned char reg; unsigned int pll_reg = 0; unsigned long sm501_freq; /* the actual frequency achieved */ @@ -592,9 +592,9 @@ unsigned long sm501_set_clock(struct device *dev, mutex_lock(&sm->clock_lock); - mode = readl(sm->regs + SM501_POWER_MODE_CONTROL); - gate = readl(sm->regs + SM501_CURRENT_GATE); - clock = readl(sm->regs + SM501_CURRENT_CLOCK); + mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL); + gate = smc501_readl(sm->regs + SM501_CURRENT_GATE); + clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK); clock = clock & ~(0xFF << clksrc); clock |= reg<regs + SM501_POWER_MODE_0_GATE); - writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK); + smc501_writel(gate, sm->regs + SM501_POWER_MODE_0_GATE); + smc501_writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK); mode = 0; break; case 2: case 0: - writel(gate, sm->regs + SM501_POWER_MODE_1_GATE); - writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK); + smc501_writel(gate, sm->regs + SM501_POWER_MODE_1_GATE); + smc501_writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK); mode = 1; break; @@ -619,10 +619,11 @@ unsigned long sm501_set_clock(struct device *dev, return -1; } - writel(mode, sm->regs + SM501_POWER_MODE_CONTROL); + smc501_writel(mode, sm->regs + SM501_POWER_MODE_CONTROL); if (pll_reg) - writel(pll_reg, sm->regs + SM501_PROGRAMMABLE_PLL_CONTROL); + smc501_writel(pll_reg, + sm->regs + SM501_PROGRAMMABLE_PLL_CONTROL); sm501_sync_regs(sm); @@ -902,7 +903,7 @@ static int sm501_gpio_get(struct gpio_chip *chip, unsigned offset) struct sm501_gpio_chip *smgpio = to_sm501_gpio(chip); unsigned long result; - result = readl(smgpio->regbase + SM501_GPIO_DATA_LOW); + result = smc501_readl(smgpio->regbase + SM501_GPIO_DATA_LOW); result >>= offset; return result & 1UL; @@ -915,13 +916,13 @@ static void sm501_gpio_ensure_gpio(struct sm501_gpio_chip *smchip, /* check and modify if this pin is not set as gpio. */ - if (readl(smchip->control) & bit) { + if (smc501_readl(smchip->control) & bit) { dev_info(sm501_gpio_to_dev(smchip->ourgpio)->dev, "changing mode of gpio, bit %08lx\n", bit); - ctrl = readl(smchip->control); + ctrl = smc501_readl(smchip->control); ctrl &= ~bit; - writel(ctrl, smchip->control); + smc501_writel(ctrl, smchip->control); sm501_sync_regs(sm501_gpio_to_dev(smchip->ourgpio)); } @@ -942,10 +943,10 @@ static void sm501_gpio_set(struct gpio_chip *chip, unsigned offset, int value) spin_lock_irqsave(&smgpio->lock, save); - val = readl(regs + SM501_GPIO_DATA_LOW) & ~bit; + val = smc501_readl(regs + SM501_GPIO_DATA_LOW) & ~bit; if (value) val |= bit; - writel(val, regs); + smc501_writel(val, regs); sm501_sync_regs(sm501_gpio_to_dev(smgpio)); sm501_gpio_ensure_gpio(smchip, bit); @@ -967,8 +968,8 @@ static int sm501_gpio_input(struct gpio_chip *chip, unsigned offset) spin_lock_irqsave(&smgpio->lock, save); - ddr = readl(regs + SM501_GPIO_DDR_LOW); - writel(ddr & ~bit, regs + SM501_GPIO_DDR_LOW); + ddr = smc501_readl(regs + SM501_GPIO_DDR_LOW); + smc501_writel(ddr & ~bit, regs + SM501_GPIO_DDR_LOW); sm501_sync_regs(sm501_gpio_to_dev(smgpio)); sm501_gpio_ensure_gpio(smchip, bit); @@ -994,18 +995,18 @@ static int sm501_gpio_output(struct gpio_chip *chip, spin_lock_irqsave(&smgpio->lock, save); - val = readl(regs + SM501_GPIO_DATA_LOW); + val = smc501_readl(regs + SM501_GPIO_DATA_LOW); if (value) val |= bit; else val &= ~bit; - writel(val, regs); + smc501_writel(val, regs); - ddr = readl(regs + SM501_GPIO_DDR_LOW); - writel(ddr | bit, regs + SM501_GPIO_DDR_LOW); + ddr = smc501_readl(regs + SM501_GPIO_DDR_LOW); + smc501_writel(ddr | bit, regs + SM501_GPIO_DDR_LOW); sm501_sync_regs(sm501_gpio_to_dev(smgpio)); - writel(val, regs + SM501_GPIO_DATA_LOW); + smc501_writel(val, regs + SM501_GPIO_DATA_LOW); sm501_sync_regs(sm501_gpio_to_dev(smgpio)); spin_unlock_irqrestore(&smgpio->lock, save); @@ -1231,7 +1232,7 @@ static ssize_t sm501_dbg_regs(struct device *dev, for (reg = 0x00; reg < 0x70; reg += 4) { ret = sprintf(ptr, "%08x = %08x\n", - reg, readl(sm->regs + reg)); + reg, smc501_readl(sm->regs + reg)); ptr += ret; } @@ -1255,10 +1256,10 @@ static inline void sm501_init_reg(struct sm501_devdata *sm, { unsigned long tmp; - tmp = readl(sm->regs + reg); + tmp = smc501_readl(sm->regs + reg); tmp &= ~r->mask; tmp |= r->set; - writel(tmp, sm->regs + reg); + smc501_writel(tmp, sm->regs + reg); } /* sm501_init_regs @@ -1299,7 +1300,7 @@ static void sm501_init_regs(struct sm501_devdata *sm, static int sm501_check_clocks(struct sm501_devdata *sm) { - unsigned long pwrmode = readl(sm->regs + SM501_CURRENT_CLOCK); + unsigned long pwrmode = smc501_readl(sm->regs + SM501_CURRENT_CLOCK); unsigned long msrc = (pwrmode & SM501_POWERMODE_M_SRC); unsigned long m1src = (pwrmode & SM501_POWERMODE_M1_SRC); @@ -1334,7 +1335,7 @@ static int __devinit sm501_init_dev(struct sm501_devdata *sm) INIT_LIST_HEAD(&sm->devices); - devid = readl(sm->regs + SM501_DEVICEID); + devid = smc501_readl(sm->regs + SM501_DEVICEID); if ((devid & SM501_DEVICEID_IDMASK) != SM501_DEVICEID_SM501) { dev_err(sm->dev, "incorrect device id %08lx\n", devid); @@ -1342,9 +1343,9 @@ static int __devinit sm501_init_dev(struct sm501_devdata *sm) } /* disable irqs */ - writel(0, sm->regs + SM501_IRQ_MASK); + smc501_writel(0, sm->regs + SM501_IRQ_MASK); - dramctrl = readl(sm->regs + SM501_DRAM_CONTROL); + dramctrl = smc501_readl(sm->regs + SM501_DRAM_CONTROL); mem_avail = sm501_mem_local[(dramctrl >> 13) & 0x7]; dev_info(sm->dev, "SM501 At %p: Version %08lx, %ld Mb, IRQ %d\n", @@ -1489,7 +1490,7 @@ static int sm501_plat_suspend(struct platform_device *pdev, pm_message_t state) struct sm501_devdata *sm = platform_get_drvdata(pdev); sm->in_suspend = 1; - sm->pm_misc = readl(sm->regs + SM501_MISC_CONTROL); + sm->pm_misc = smc501_readl(sm->regs + SM501_MISC_CONTROL); sm501_dump_regs(sm); @@ -1513,9 +1514,9 @@ static int sm501_plat_resume(struct platform_device *pdev) /* check to see if we are in the same state as when suspended */ - if (readl(sm->regs + SM501_MISC_CONTROL) != sm->pm_misc) { + if (smc501_readl(sm->regs + SM501_MISC_CONTROL) != sm->pm_misc) { dev_info(sm->dev, "SM501_MISC_CONTROL changed over sleep\n"); - writel(sm->pm_misc, sm->regs + SM501_MISC_CONTROL); + smc501_writel(sm->pm_misc, sm->regs + SM501_MISC_CONTROL); /* our suspend causes the controller state to change, * either by something attempting setup, power loss, diff --git a/drivers/video/sm501fb.c b/drivers/video/sm501fb.c index bcb44a594ebc..5df406c87c50 100644 --- a/drivers/video/sm501fb.c +++ b/drivers/video/sm501fb.c @@ -117,7 +117,7 @@ static inline int v_total(struct fb_var_screeninfo *var) static inline void sm501fb_sync_regs(struct sm501fb_info *info) { - readl(info->regs); + smc501_readl(info->regs); } /* sm501_alloc_mem @@ -262,7 +262,7 @@ static void sm501fb_setup_gamma(struct sm501fb_info *fbi, /* set gamma values */ for (offset = 0; offset < 256 * 4; offset += 4) { - writel(value, fbi->regs + palette + offset); + smc501_writel(value, fbi->regs + palette + offset); value += 0x010101; /* Advance RGB by 1,1,1.*/ } } @@ -476,7 +476,8 @@ static int sm501fb_set_par_common(struct fb_info *info, /* set start of framebuffer to the screen */ - writel(par->screen.sm_addr | SM501_ADDR_FLIP, fbi->regs + head_addr); + smc501_writel(par->screen.sm_addr | SM501_ADDR_FLIP, + fbi->regs + head_addr); /* program CRT clock */ @@ -519,7 +520,7 @@ static void sm501fb_set_par_geometry(struct fb_info *info, reg = info->fix.line_length; reg |= ((var->xres * var->bits_per_pixel)/8) << 16; - writel(reg, fbi->regs + (par->head == HEAD_CRT ? + smc501_writel(reg, fbi->regs + (par->head == HEAD_CRT ? SM501_DC_CRT_FB_OFFSET : SM501_DC_PANEL_FB_OFFSET)); /* program horizontal total */ @@ -527,27 +528,27 @@ static void sm501fb_set_par_geometry(struct fb_info *info, reg = (h_total(var) - 1) << 16; reg |= (var->xres - 1); - writel(reg, base + SM501_OFF_DC_H_TOT); + smc501_writel(reg, base + SM501_OFF_DC_H_TOT); /* program horizontal sync */ reg = var->hsync_len << 16; reg |= var->xres + var->right_margin - 1; - writel(reg, base + SM501_OFF_DC_H_SYNC); + smc501_writel(reg, base + SM501_OFF_DC_H_SYNC); /* program vertical total */ reg = (v_total(var) - 1) << 16; reg |= (var->yres - 1); - writel(reg, base + SM501_OFF_DC_V_TOT); + smc501_writel(reg, base + SM501_OFF_DC_V_TOT); /* program vertical sync */ reg = var->vsync_len << 16; reg |= var->yres + var->lower_margin - 1; - writel(reg, base + SM501_OFF_DC_V_SYNC); + smc501_writel(reg, base + SM501_OFF_DC_V_SYNC); } /* sm501fb_pan_crt @@ -566,15 +567,15 @@ static int sm501fb_pan_crt(struct fb_var_screeninfo *var, xoffs = var->xoffset * bytes_pixel; - reg = readl(fbi->regs + SM501_DC_CRT_CONTROL); + reg = smc501_readl(fbi->regs + SM501_DC_CRT_CONTROL); reg &= ~SM501_DC_CRT_CONTROL_PIXEL_MASK; reg |= ((xoffs & 15) / bytes_pixel) << 4; - writel(reg, fbi->regs + SM501_DC_CRT_CONTROL); + smc501_writel(reg, fbi->regs + SM501_DC_CRT_CONTROL); reg = (par->screen.sm_addr + xoffs + var->yoffset * info->fix.line_length); - writel(reg | SM501_ADDR_FLIP, fbi->regs + SM501_DC_CRT_FB_ADDR); + smc501_writel(reg | SM501_ADDR_FLIP, fbi->regs + SM501_DC_CRT_FB_ADDR); sm501fb_sync_regs(fbi); return 0; @@ -593,10 +594,10 @@ static int sm501fb_pan_pnl(struct fb_var_screeninfo *var, unsigned long reg; reg = var->xoffset | (var->xres_virtual << 16); - writel(reg, fbi->regs + SM501_DC_PANEL_FB_WIDTH); + smc501_writel(reg, fbi->regs + SM501_DC_PANEL_FB_WIDTH); reg = var->yoffset | (var->yres_virtual << 16); - writel(reg, fbi->regs + SM501_DC_PANEL_FB_HEIGHT); + smc501_writel(reg, fbi->regs + SM501_DC_PANEL_FB_HEIGHT); sm501fb_sync_regs(fbi); return 0; @@ -622,7 +623,7 @@ static int sm501fb_set_par_crt(struct fb_info *info) /* enable CRT DAC - note 0 is on!*/ sm501_misc_control(fbi->dev->parent, 0, SM501_MISC_DAC_POWER); - control = readl(fbi->regs + SM501_DC_CRT_CONTROL); + control = smc501_readl(fbi->regs + SM501_DC_CRT_CONTROL); control &= (SM501_DC_CRT_CONTROL_PIXEL_MASK | SM501_DC_CRT_CONTROL_GAMMA | @@ -684,7 +685,7 @@ static int sm501fb_set_par_crt(struct fb_info *info) out_update: dev_dbg(fbi->dev, "new control is %08lx\n", control); - writel(control, fbi->regs + SM501_DC_CRT_CONTROL); + smc501_writel(control, fbi->regs + SM501_DC_CRT_CONTROL); sm501fb_sync_regs(fbi); return 0; @@ -696,18 +697,18 @@ static void sm501fb_panel_power(struct sm501fb_info *fbi, int to) void __iomem *ctrl_reg = fbi->regs + SM501_DC_PANEL_CONTROL; struct sm501_platdata_fbsub *pd = fbi->pdata->fb_pnl; - control = readl(ctrl_reg); + control = smc501_readl(ctrl_reg); if (to && (control & SM501_DC_PANEL_CONTROL_VDD) == 0) { /* enable panel power */ control |= SM501_DC_PANEL_CONTROL_VDD; /* FPVDDEN */ - writel(control, ctrl_reg); + smc501_writel(control, ctrl_reg); sm501fb_sync_regs(fbi); mdelay(10); control |= SM501_DC_PANEL_CONTROL_DATA; /* DATA */ - writel(control, ctrl_reg); + smc501_writel(control, ctrl_reg); sm501fb_sync_regs(fbi); mdelay(10); @@ -719,7 +720,7 @@ static void sm501fb_panel_power(struct sm501fb_info *fbi, int to) else control |= SM501_DC_PANEL_CONTROL_BIAS; - writel(control, ctrl_reg); + smc501_writel(control, ctrl_reg); sm501fb_sync_regs(fbi); mdelay(10); } @@ -730,7 +731,7 @@ static void sm501fb_panel_power(struct sm501fb_info *fbi, int to) else control |= SM501_DC_PANEL_CONTROL_FPEN; - writel(control, ctrl_reg); + smc501_writel(control, ctrl_reg); sm501fb_sync_regs(fbi); mdelay(10); } @@ -742,7 +743,7 @@ static void sm501fb_panel_power(struct sm501fb_info *fbi, int to) else control &= ~SM501_DC_PANEL_CONTROL_FPEN; - writel(control, ctrl_reg); + smc501_writel(control, ctrl_reg); sm501fb_sync_regs(fbi); mdelay(10); } @@ -753,18 +754,18 @@ static void sm501fb_panel_power(struct sm501fb_info *fbi, int to) else control &= ~SM501_DC_PANEL_CONTROL_BIAS; - writel(control, ctrl_reg); + smc501_writel(control, ctrl_reg); sm501fb_sync_regs(fbi); mdelay(10); } control &= ~SM501_DC_PANEL_CONTROL_DATA; - writel(control, ctrl_reg); + smc501_writel(control, ctrl_reg); sm501fb_sync_regs(fbi); mdelay(10); control &= ~SM501_DC_PANEL_CONTROL_VDD; - writel(control, ctrl_reg); + smc501_writel(control, ctrl_reg); sm501fb_sync_regs(fbi); mdelay(10); } @@ -799,7 +800,7 @@ static int sm501fb_set_par_pnl(struct fb_info *info) /* update control register */ - control = readl(fbi->regs + SM501_DC_PANEL_CONTROL); + control = smc501_readl(fbi->regs + SM501_DC_PANEL_CONTROL); control &= (SM501_DC_PANEL_CONTROL_GAMMA | SM501_DC_PANEL_CONTROL_VDD | SM501_DC_PANEL_CONTROL_DATA | @@ -833,16 +834,16 @@ static int sm501fb_set_par_pnl(struct fb_info *info) BUG(); } - writel(0x0, fbi->regs + SM501_DC_PANEL_PANNING_CONTROL); + smc501_writel(0x0, fbi->regs + SM501_DC_PANEL_PANNING_CONTROL); /* panel plane top left and bottom right location */ - writel(0x00, fbi->regs + SM501_DC_PANEL_TL_LOC); + smc501_writel(0x00, fbi->regs + SM501_DC_PANEL_TL_LOC); reg = var->xres - 1; reg |= (var->yres - 1) << 16; - writel(reg, fbi->regs + SM501_DC_PANEL_BR_LOC); + smc501_writel(reg, fbi->regs + SM501_DC_PANEL_BR_LOC); /* program panel control register */ @@ -855,7 +856,7 @@ static int sm501fb_set_par_pnl(struct fb_info *info) if ((var->sync & FB_SYNC_VERT_HIGH_ACT) == 0) control |= SM501_DC_PANEL_CONTROL_VSP; - writel(control, fbi->regs + SM501_DC_PANEL_CONTROL); + smc501_writel(control, fbi->regs + SM501_DC_PANEL_CONTROL); sm501fb_sync_regs(fbi); /* ensure the panel interface is not tristated at this point */ @@ -924,7 +925,7 @@ static int sm501fb_setcolreg(unsigned regno, val |= (green >> 8) << 8; val |= blue >> 8; - writel(val, base + (regno * 4)); + smc501_writel(val, base + (regno * 4)); } break; @@ -980,7 +981,7 @@ static int sm501fb_blank_crt(int blank_mode, struct fb_info *info) dev_dbg(fbi->dev, "%s(mode=%d, %p)\n", __func__, blank_mode, info); - ctrl = readl(fbi->regs + SM501_DC_CRT_CONTROL); + ctrl = smc501_readl(fbi->regs + SM501_DC_CRT_CONTROL); switch (blank_mode) { case FB_BLANK_POWERDOWN: @@ -1004,7 +1005,7 @@ static int sm501fb_blank_crt(int blank_mode, struct fb_info *info) } - writel(ctrl, fbi->regs + SM501_DC_CRT_CONTROL); + smc501_writel(ctrl, fbi->regs + SM501_DC_CRT_CONTROL); sm501fb_sync_regs(fbi); return 0; @@ -1041,12 +1042,14 @@ static int sm501fb_cursor(struct fb_info *info, struct fb_cursor *cursor) if (cursor->image.depth > 1) return -EINVAL; - hwc_addr = readl(base + SM501_OFF_HWC_ADDR); + hwc_addr = smc501_readl(base + SM501_OFF_HWC_ADDR); if (cursor->enable) - writel(hwc_addr | SM501_HWC_EN, base + SM501_OFF_HWC_ADDR); + smc501_writel(hwc_addr | SM501_HWC_EN, + base + SM501_OFF_HWC_ADDR); else - writel(hwc_addr & ~SM501_HWC_EN, base + SM501_OFF_HWC_ADDR); + smc501_writel(hwc_addr & ~SM501_HWC_EN, + base + SM501_OFF_HWC_ADDR); /* set data */ if (cursor->set & FB_CUR_SETPOS) { @@ -1060,7 +1063,7 @@ static int sm501fb_cursor(struct fb_info *info, struct fb_cursor *cursor) //y += cursor->image.height; - writel(x | (y << 16), base + SM501_OFF_HWC_LOC); + smc501_writel(x | (y << 16), base + SM501_OFF_HWC_LOC); } if (cursor->set & FB_CUR_SETCMAP) { @@ -1080,8 +1083,8 @@ static int sm501fb_cursor(struct fb_info *info, struct fb_cursor *cursor) dev_dbg(fbi->dev, "fgcol %08lx, bgcol %08lx\n", fg, bg); - writel(bg, base + SM501_OFF_HWC_COLOR_1_2); - writel(fg, base + SM501_OFF_HWC_COLOR_3); + smc501_writel(bg, base + SM501_OFF_HWC_COLOR_1_2); + smc501_writel(fg, base + SM501_OFF_HWC_COLOR_3); } if (cursor->set & FB_CUR_SETSIZE || @@ -1102,7 +1105,7 @@ static int sm501fb_cursor(struct fb_info *info, struct fb_cursor *cursor) __func__, cursor->image.width, cursor->image.height); for (op = 0; op < (64*64*2)/8; op+=4) - writel(0x0, dst + op); + smc501_writel(0x0, dst + op); for (y = 0; y < cursor->image.height; y++) { for (x = 0; x < cursor->image.width; x++) { @@ -1141,7 +1144,7 @@ static ssize_t sm501fb_crtsrc_show(struct device *dev, struct sm501fb_info *info = dev_get_drvdata(dev); unsigned long ctrl; - ctrl = readl(info->regs + SM501_DC_CRT_CONTROL); + ctrl = smc501_readl(info->regs + SM501_DC_CRT_CONTROL); ctrl &= SM501_DC_CRT_CONTROL_SEL; return snprintf(buf, PAGE_SIZE, "%s\n", ctrl ? "crt" : "panel"); @@ -1172,7 +1175,7 @@ static ssize_t sm501fb_crtsrc_store(struct device *dev, dev_info(dev, "setting crt source to head %d\n", head); - ctrl = readl(info->regs + SM501_DC_CRT_CONTROL); + ctrl = smc501_readl(info->regs + SM501_DC_CRT_CONTROL); if (head == HEAD_CRT) { ctrl |= SM501_DC_CRT_CONTROL_SEL; @@ -1184,7 +1187,7 @@ static ssize_t sm501fb_crtsrc_store(struct device *dev, ctrl &= ~SM501_DC_CRT_CONTROL_TE; } - writel(ctrl, info->regs + SM501_DC_CRT_CONTROL); + smc501_writel(ctrl, info->regs + SM501_DC_CRT_CONTROL); sm501fb_sync_regs(info); return len; @@ -1205,7 +1208,8 @@ static int sm501fb_show_regs(struct sm501fb_info *info, char *ptr, unsigned int reg; for (reg = start; reg < (len + start); reg += 4) - ptr += sprintf(ptr, "%08x = %08x\n", reg, readl(mem + reg)); + ptr += sprintf(ptr, "%08x = %08x\n", reg, + smc501_readl(mem + reg)); return ptr - buf; } @@ -1257,7 +1261,7 @@ static int sm501fb_sync(struct fb_info *info) /* wait for the 2d engine to be ready */ while ((count > 0) && - (readl(fbi->regs + SM501_SYSTEM_CONTROL) & + (smc501_readl(fbi->regs + SM501_SYSTEM_CONTROL) & SM501_SYSCTRL_2D_ENGINE_STATUS) != 0) count--; @@ -1312,45 +1316,46 @@ static void sm501fb_copyarea(struct fb_info *info, const struct fb_copyarea *are return; /* set the base addresses */ - writel(par->screen.sm_addr, fbi->regs2d + SM501_2D_SOURCE_BASE); - writel(par->screen.sm_addr, fbi->regs2d + SM501_2D_DESTINATION_BASE); + smc501_writel(par->screen.sm_addr, fbi->regs2d + SM501_2D_SOURCE_BASE); + smc501_writel(par->screen.sm_addr, + fbi->regs2d + SM501_2D_DESTINATION_BASE); /* set the window width */ - writel((info->var.xres << 16) | info->var.xres, + smc501_writel((info->var.xres << 16) | info->var.xres, fbi->regs2d + SM501_2D_WINDOW_WIDTH); /* set window stride */ - writel((info->var.xres_virtual << 16) | info->var.xres_virtual, + smc501_writel((info->var.xres_virtual << 16) | info->var.xres_virtual, fbi->regs2d + SM501_2D_PITCH); /* set data format */ switch (info->var.bits_per_pixel) { case 8: - writel(0, fbi->regs2d + SM501_2D_STRETCH); + smc501_writel(0, fbi->regs2d + SM501_2D_STRETCH); break; case 16: - writel(0x00100000, fbi->regs2d + SM501_2D_STRETCH); + smc501_writel(0x00100000, fbi->regs2d + SM501_2D_STRETCH); break; case 32: - writel(0x00200000, fbi->regs2d + SM501_2D_STRETCH); + smc501_writel(0x00200000, fbi->regs2d + SM501_2D_STRETCH); break; } /* 2d compare mask */ - writel(0xffffffff, fbi->regs2d + SM501_2D_COLOR_COMPARE_MASK); + smc501_writel(0xffffffff, fbi->regs2d + SM501_2D_COLOR_COMPARE_MASK); /* 2d mask */ - writel(0xffffffff, fbi->regs2d + SM501_2D_MASK); + smc501_writel(0xffffffff, fbi->regs2d + SM501_2D_MASK); /* source and destination x y */ - writel((sx << 16) | sy, fbi->regs2d + SM501_2D_SOURCE); - writel((dx << 16) | dy, fbi->regs2d + SM501_2D_DESTINATION); + smc501_writel((sx << 16) | sy, fbi->regs2d + SM501_2D_SOURCE); + smc501_writel((dx << 16) | dy, fbi->regs2d + SM501_2D_DESTINATION); /* w/h */ - writel((width << 16) | height, fbi->regs2d + SM501_2D_DIMENSION); + smc501_writel((width << 16) | height, fbi->regs2d + SM501_2D_DIMENSION); /* do area move */ - writel(0x800000cc | rtl, fbi->regs2d + SM501_2D_CONTROL); + smc501_writel(0x800000cc | rtl, fbi->regs2d + SM501_2D_CONTROL); } static void sm501fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) @@ -1372,47 +1377,49 @@ static void sm501fb_fillrect(struct fb_info *info, const struct fb_fillrect *rec return; /* set the base addresses */ - writel(par->screen.sm_addr, fbi->regs2d + SM501_2D_SOURCE_BASE); - writel(par->screen.sm_addr, fbi->regs2d + SM501_2D_DESTINATION_BASE); + smc501_writel(par->screen.sm_addr, fbi->regs2d + SM501_2D_SOURCE_BASE); + smc501_writel(par->screen.sm_addr, + fbi->regs2d + SM501_2D_DESTINATION_BASE); /* set the window width */ - writel((info->var.xres << 16) | info->var.xres, + smc501_writel((info->var.xres << 16) | info->var.xres, fbi->regs2d + SM501_2D_WINDOW_WIDTH); /* set window stride */ - writel((info->var.xres_virtual << 16) | info->var.xres_virtual, + smc501_writel((info->var.xres_virtual << 16) | info->var.xres_virtual, fbi->regs2d + SM501_2D_PITCH); /* set data format */ switch (info->var.bits_per_pixel) { case 8: - writel(0, fbi->regs2d + SM501_2D_STRETCH); + smc501_writel(0, fbi->regs2d + SM501_2D_STRETCH); break; case 16: - writel(0x00100000, fbi->regs2d + SM501_2D_STRETCH); + smc501_writel(0x00100000, fbi->regs2d + SM501_2D_STRETCH); break; case 32: - writel(0x00200000, fbi->regs2d + SM501_2D_STRETCH); + smc501_writel(0x00200000, fbi->regs2d + SM501_2D_STRETCH); break; } /* 2d compare mask */ - writel(0xffffffff, fbi->regs2d + SM501_2D_COLOR_COMPARE_MASK); + smc501_writel(0xffffffff, fbi->regs2d + SM501_2D_COLOR_COMPARE_MASK); /* 2d mask */ - writel(0xffffffff, fbi->regs2d + SM501_2D_MASK); + smc501_writel(0xffffffff, fbi->regs2d + SM501_2D_MASK); /* colour */ - writel(rect->color, fbi->regs2d + SM501_2D_FOREGROUND); + smc501_writel(rect->color, fbi->regs2d + SM501_2D_FOREGROUND); /* x y */ - writel((rect->dx << 16) | rect->dy, fbi->regs2d + SM501_2D_DESTINATION); + smc501_writel((rect->dx << 16) | rect->dy, + fbi->regs2d + SM501_2D_DESTINATION); /* w/h */ - writel((width << 16) | height, fbi->regs2d + SM501_2D_DIMENSION); + smc501_writel((width << 16) | height, fbi->regs2d + SM501_2D_DIMENSION); /* do rectangle fill */ - writel(0x800100cc, fbi->regs2d + SM501_2D_CONTROL); + smc501_writel(0x800100cc, fbi->regs2d + SM501_2D_CONTROL); } @@ -1470,11 +1477,12 @@ static int sm501_init_cursor(struct fb_info *fbi, unsigned int reg_base) /* initialise the colour registers */ - writel(par->cursor.sm_addr, par->cursor_regs + SM501_OFF_HWC_ADDR); + smc501_writel(par->cursor.sm_addr, + par->cursor_regs + SM501_OFF_HWC_ADDR); - writel(0x00, par->cursor_regs + SM501_OFF_HWC_LOC); - writel(0x00, par->cursor_regs + SM501_OFF_HWC_COLOR_1_2); - writel(0x00, par->cursor_regs + SM501_OFF_HWC_COLOR_3); + smc501_writel(0x00, par->cursor_regs + SM501_OFF_HWC_LOC); + smc501_writel(0x00, par->cursor_regs + SM501_OFF_HWC_COLOR_1_2); + smc501_writel(0x00, par->cursor_regs + SM501_OFF_HWC_COLOR_3); sm501fb_sync_regs(info); return 0; @@ -1581,7 +1589,7 @@ static int sm501fb_start(struct sm501fb_info *info, /* clear palette ram - undefined at power on */ for (k = 0; k < (256 * 3); k++) - writel(0, info->regs + SM501_DC_PANEL_PALETTE + (k * 4)); + smc501_writel(0, info->regs + SM501_DC_PANEL_PALETTE + (k * 4)); /* enable display controller */ sm501_unit_power(dev->parent, SM501_GATE_DISPLAY, 1); @@ -1649,20 +1657,20 @@ static int sm501fb_init_fb(struct fb_info *fb, switch (head) { case HEAD_CRT: pd = info->pdata->fb_crt; - ctrl = readl(info->regs + SM501_DC_CRT_CONTROL); + ctrl = smc501_readl(info->regs + SM501_DC_CRT_CONTROL); enable = (ctrl & SM501_DC_CRT_CONTROL_ENABLE) ? 1 : 0; /* ensure we set the correct source register */ if (info->pdata->fb_route != SM501_FB_CRT_PANEL) { ctrl |= SM501_DC_CRT_CONTROL_SEL; - writel(ctrl, info->regs + SM501_DC_CRT_CONTROL); + smc501_writel(ctrl, info->regs + SM501_DC_CRT_CONTROL); } break; case HEAD_PANEL: pd = info->pdata->fb_pnl; - ctrl = readl(info->regs + SM501_DC_PANEL_CONTROL); + ctrl = smc501_readl(info->regs + SM501_DC_PANEL_CONTROL); enable = (ctrl & SM501_DC_PANEL_CONTROL_EN) ? 1 : 0; break; @@ -1680,7 +1688,7 @@ static int sm501fb_init_fb(struct fb_info *fb, if (head == HEAD_CRT && info->pdata->fb_route == SM501_FB_CRT_PANEL) { ctrl &= ~SM501_DC_CRT_CONTROL_SEL; - writel(ctrl, info->regs + SM501_DC_CRT_CONTROL); + smc501_writel(ctrl, info->regs + SM501_DC_CRT_CONTROL); enable = 0; } @@ -2085,7 +2093,7 @@ static int sm501fb_suspend(struct platform_device *pdev, pm_message_t state) struct sm501fb_info *info = platform_get_drvdata(pdev); /* store crt control to resume with */ - info->pm_crt_ctrl = readl(info->regs + SM501_DC_CRT_CONTROL); + info->pm_crt_ctrl = smc501_readl(info->regs + SM501_DC_CRT_CONTROL); sm501fb_suspend_fb(info, HEAD_CRT); sm501fb_suspend_fb(info, HEAD_PANEL); @@ -2109,10 +2117,10 @@ static int sm501fb_resume(struct platform_device *pdev) /* restore the items we want to be saved for crt control */ - crt_ctrl = readl(info->regs + SM501_DC_CRT_CONTROL); + crt_ctrl = smc501_readl(info->regs + SM501_DC_CRT_CONTROL); crt_ctrl &= ~SM501_CRT_CTRL_SAVE; crt_ctrl |= info->pm_crt_ctrl & SM501_CRT_CTRL_SAVE; - writel(crt_ctrl, info->regs + SM501_DC_CRT_CONTROL); + smc501_writel(crt_ctrl, info->regs + SM501_DC_CRT_CONTROL); sm501fb_resume_fb(info, HEAD_CRT); sm501fb_resume_fb(info, HEAD_PANEL); diff --git a/include/linux/sm501.h b/include/linux/sm501.h index 214f93209b8c..02fde50a79a5 100644 --- a/include/linux/sm501.h +++ b/include/linux/sm501.h @@ -172,3 +172,11 @@ struct sm501_platdata { struct sm501_platdata_gpio_i2c *gpio_i2c; unsigned int gpio_i2c_nr; }; + +#if defined(CONFIG_PPC32) +#define smc501_readl(addr) ioread32be((addr)) +#define smc501_writel(val, addr) iowrite32be((val), (addr)) +#else +#define smc501_readl(addr) readl(addr) +#define smc501_writel(val, addr) writel(val, addr) +#endif From e6a049807105decf5aa7f0c510f5e5ec96c3548e Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Wed, 26 Jan 2011 07:21:22 +0000 Subject: [PATCH 135/140] video, sm501: add edid and commandline support - add commandline options: sm501fb.mode: Specify resolution as "x[-][@]" sm501fb.bpp: Specify bit-per-pixel if not specified mode - Add support for encoding display mode information in the device tree using verbatim EDID block. If the "edid" entry in the "smi,sm501" node is present, the driver will build mode database using EDID data and allow setting the display modes from this database. Signed-off-by: Heiko Schocher cc: linux-fbdev@vger.kernel.org cc: devicetree-discuss@ozlabs.org cc: Ben Dooks cc: Vincent Sanders cc: Samuel Ortiz cc: linux-kernel@vger.kernel.org cc: Randy Dunlap cc: Paul Mundt Signed-off-by: Paul Mundt --- Documentation/fb/sm501.txt | 10 ++++++ drivers/video/sm501fb.c | 65 +++++++++++++++++++++++++++++++++++--- 2 files changed, 70 insertions(+), 5 deletions(-) create mode 100644 Documentation/fb/sm501.txt diff --git a/Documentation/fb/sm501.txt b/Documentation/fb/sm501.txt new file mode 100644 index 000000000000..8d17aebd2648 --- /dev/null +++ b/Documentation/fb/sm501.txt @@ -0,0 +1,10 @@ +Configuration: + +You can pass the following kernel command line options to sm501 videoframebuffer: + + sm501fb.bpp= SM501 Display driver: + Specifiy bits-per-pixel if not specified by 'mode' + + sm501fb.mode= SM501 Display driver: + Specify resolution as + "x[-][@]" diff --git a/drivers/video/sm501fb.c b/drivers/video/sm501fb.c index 5df406c87c50..f31252ce8892 100644 --- a/drivers/video/sm501fb.c +++ b/drivers/video/sm501fb.c @@ -41,6 +41,26 @@ #include #include +#include "edid.h" + +static char *fb_mode = "640x480-16@60"; +static unsigned long default_bpp = 16; + +static struct fb_videomode __devinitdata sm501_default_mode = { + .refresh = 60, + .xres = 640, + .yres = 480, + .pixclock = 20833, + .left_margin = 142, + .right_margin = 13, + .upper_margin = 21, + .lower_margin = 1, + .hsync_len = 69, + .vsync_len = 3, + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED +}; + #define NR_PALETTE 256 enum sm501_controller { @@ -77,6 +97,7 @@ struct sm501fb_info { void __iomem *regs2d; /* 2d remapped registers */ void __iomem *fbmem; /* remapped framebuffer */ size_t fbmem_len; /* length of remapped region */ + u8 *edid_data; }; /* per-framebuffer private data */ @@ -1725,9 +1746,16 @@ static int sm501fb_init_fb(struct fb_info *fb, fb->var.vmode = FB_VMODE_NONINTERLACED; fb->var.bits_per_pixel = 16; + if (info->edid_data) { + /* Now build modedb from EDID */ + fb_edid_to_monspecs(info->edid_data, &fb->monspecs); + fb_videomode_to_modelist(fb->monspecs.modedb, + fb->monspecs.modedb_len, + &fb->modelist); + } + if (enable && (pd->flags & SM501FB_FLAG_USE_INIT_MODE) && 0) { /* TODO read the mode from the current display */ - } else { if (pd->def_mode) { dev_info(info->dev, "using supplied mode\n"); @@ -1737,12 +1765,34 @@ static int sm501fb_init_fb(struct fb_info *fb, fb->var.xres_virtual = fb->var.xres; fb->var.yres_virtual = fb->var.yres; } else { - ret = fb_find_mode(&fb->var, fb, + if (info->edid_data) + ret = fb_find_mode(&fb->var, fb, fb_mode, + fb->monspecs.modedb, + fb->monspecs.modedb_len, + &sm501_default_mode, default_bpp); + else + ret = fb_find_mode(&fb->var, fb, NULL, NULL, 0, NULL, 8); - if (ret == 0 || ret == 4) { - dev_err(info->dev, - "failed to get initial mode\n"); + switch (ret) { + case 1: + dev_info(info->dev, "using mode specified in " + "@mode\n"); + break; + case 2: + dev_info(info->dev, "using mode specified in " + "@mode with ignored refresh rate\n"); + break; + case 3: + dev_info(info->dev, "using mode default " + "mode\n"); + break; + case 4: + dev_info(info->dev, "using mode from list\n"); + break; + default: + dev_info(info->dev, "ret = %d\n", ret); + dev_info(info->dev, "failed to find mode\n"); return -EINVAL; } } @@ -2157,6 +2207,11 @@ static void __exit sm501fb_cleanup(void) module_init(sm501fb_init); module_exit(sm501fb_cleanup); +module_param_named(mode, fb_mode, charp, 0); +MODULE_PARM_DESC(mode, + "Specify resolution as \"x[-][@]\" "); +module_param_named(bpp, default_bpp, ulong, 0); +MODULE_PARM_DESC(bpp, "Specify bit-per-pixel if not specified mode"); MODULE_AUTHOR("Ben Dooks, Vincent Sanders"); MODULE_DESCRIPTION("SM501 Framebuffer driver"); MODULE_LICENSE("GPL v2"); From 4295f9bf74a885da390abc49a3b42a011c1bb890 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Wed, 26 Jan 2011 07:21:30 +0000 Subject: [PATCH 136/140] video, sm501: add OF binding to support SM501 - add binding to OF, compatible name "smi,sm501" Signed-off-by: Heiko Schocher cc: linux-fbdev@vger.kernel.org cc: devicetree-discuss@ozlabs.org cc: Ben Dooks cc: Vincent Sanders cc: Samuel Ortiz cc: linux-kernel@vger.kernel.org cc: Randy Dunlap cc: Paul Mundt Signed-off-by: Paul Mundt --- Documentation/powerpc/dts-bindings/sm501.txt | 34 ++++++++++++++++ drivers/mfd/sm501.c | 9 ++++- drivers/video/sm501fb.c | 42 ++++++++++++++++++-- 3 files changed, 81 insertions(+), 4 deletions(-) create mode 100644 Documentation/powerpc/dts-bindings/sm501.txt diff --git a/Documentation/powerpc/dts-bindings/sm501.txt b/Documentation/powerpc/dts-bindings/sm501.txt new file mode 100644 index 000000000000..7d319fba9b5b --- /dev/null +++ b/Documentation/powerpc/dts-bindings/sm501.txt @@ -0,0 +1,34 @@ +* SM SM501 + +The SM SM501 is a LCD controller, with proper hardware, it can also +drive DVI monitors. + +Required properties: +- compatible : should be "smi,sm501". +- reg : contain two entries: + - First entry: System Configuration register + - Second entry: IO space (Display Controller register) +- interrupts : SMI interrupt to the cpu should be described here. +- interrupt-parent : the phandle for the interrupt controller that + services interrupts for this device. + +Optional properties: +- mode : select a video mode: + x[-][@] +- edid : verbatim EDID data block describing attached display. + Data from the detailed timing descriptor will be used to + program the display controller. +- little-endian: availiable on big endian systems, to + set different foreign endian. +- big-endian: availiable on little endian systems, to + set different foreign endian. + +Example for MPC5200: + display@1,0 { + compatible = "smi,sm501"; + reg = <1 0x00000000 0x00800000 + 1 0x03e00000 0x00200000>; + interrupts = <1 1 3>; + mode = "640x480-32@60"; + edid = [edid-data]; + }; diff --git a/drivers/mfd/sm501.c b/drivers/mfd/sm501.c index 558d5f3f6d02..df3702c1756d 100644 --- a/drivers/mfd/sm501.c +++ b/drivers/mfd/sm501.c @@ -1377,7 +1377,7 @@ static int __devinit sm501_init_dev(struct sm501_devdata *sm) sm501_register_gpio(sm); } - if (pdata->gpio_i2c != NULL && pdata->gpio_i2c_nr > 0) { + if (pdata && pdata->gpio_i2c != NULL && pdata->gpio_i2c_nr > 0) { if (!sm501_gpio_isregistered(sm)) dev_err(sm->dev, "no gpio available for i2c gpio.\n"); else @@ -1422,6 +1422,7 @@ static int __devinit sm501_plat_probe(struct platform_device *dev) sm->io_res = platform_get_resource(dev, IORESOURCE_MEM, 1); sm->mem_res = platform_get_resource(dev, IORESOURCE_MEM, 0); + if (sm->io_res == NULL || sm->mem_res == NULL) { dev_err(&dev->dev, "failed to get IO resource\n"); ret = -ENOENT; @@ -1735,10 +1736,16 @@ static struct pci_driver sm501_pci_driver = { MODULE_ALIAS("platform:sm501"); +static struct of_device_id __devinitdata of_sm501_match_tbl[] = { + { .compatible = "smi,sm501", }, + { /* end */ } +}; + static struct platform_driver sm501_plat_driver = { .driver = { .name = "sm501", .owner = THIS_MODULE, + .of_match_table = of_sm501_match_tbl, }, .probe = sm501_plat_probe, .remove = sm501_plat_remove, diff --git a/drivers/video/sm501fb.c b/drivers/video/sm501fb.c index f31252ce8892..46d1a64fe80d 100644 --- a/drivers/video/sm501fb.c +++ b/drivers/video/sm501fb.c @@ -1729,6 +1729,15 @@ static int sm501fb_init_fb(struct fb_info *fb, FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT | FBINFO_HWACCEL_XPAN | FBINFO_HWACCEL_YPAN; +#if defined(CONFIG_OF) +#ifdef __BIG_ENDIAN + if (of_get_property(info->dev->parent->of_node, "little-endian", NULL)) + fb->flags |= FBINFO_FOREIGN_ENDIAN; +#else + if (of_get_property(info->dev->parent->of_node, "big-endian", NULL)) + fb->flags |= FBINFO_FOREIGN_ENDIAN; +#endif +#endif /* fixed data */ fb->fix.type = FB_TYPE_PACKED_PIXELS; @@ -1765,14 +1774,17 @@ static int sm501fb_init_fb(struct fb_info *fb, fb->var.xres_virtual = fb->var.xres; fb->var.yres_virtual = fb->var.yres; } else { - if (info->edid_data) + if (info->edid_data) { ret = fb_find_mode(&fb->var, fb, fb_mode, fb->monspecs.modedb, fb->monspecs.modedb_len, &sm501_default_mode, default_bpp); - else + /* edid_data is no longer needed, free it */ + kfree(info->edid_data); + } else { ret = fb_find_mode(&fb->var, fb, NULL, NULL, 0, NULL, 8); + } switch (ret) { case 1: @@ -1933,8 +1945,32 @@ static int __devinit sm501fb_probe(struct platform_device *pdev) } if (info->pdata == NULL) { - dev_info(dev, "using default configuration data\n"); + int found = 0; +#if defined(CONFIG_OF) + struct device_node *np = pdev->dev.parent->of_node; + const u8 *prop; + const char *cp; + int len; + info->pdata = &sm501fb_def_pdata; + if (np) { + /* Get EDID */ + cp = of_get_property(np, "mode", &len); + if (cp) + strcpy(fb_mode, cp); + prop = of_get_property(np, "edid", &len); + if (prop && len == EDID_LENGTH) { + info->edid_data = kmemdup(prop, EDID_LENGTH, + GFP_KERNEL); + if (info->edid_data) + found = 1; + } + } +#endif + if (!found) { + dev_info(dev, "using default configuration data\n"); + info->pdata = &sm501fb_def_pdata; + } } /* probe for the presence of each panel */ From 32b98bf8752c5483481f77d48934aba26c967fcd Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 21 Dec 2010 01:41:17 +0000 Subject: [PATCH 137/140] fbcon: fix situation where fbcon gets deinitialised and can't reinit. Situation as follow: 2 GPUs + vesafb + kms. GPU 1 is primary, vesafb binds to it as fb0 radeon loads GPU 0 loads as fb1 GPU 1 loads, vesafb gets kicked off which causes fb0 to unbind console, which causes the dummy console to rebind. this means fbcon_deinit gets called, which calls fbcon_exit since the console isn't bound anymore and we set fbcon_has_exited. GPU 1 creates a new fb0 which is primary and we want to be console. fbcon_fb_registered gets called sets the primary up and calls set_con2fb_map, however as fbcon_has_exited is set nothing further ever happens. This patch bypasses the fbcon_has_exited and checks if the console is unbound, if its unbound it calls the fbcon_takeover which calls the vt layer to call the fbcon_startup method and everthing works. Signed-off-by: Dave Airlie Signed-off-by: Paul Mundt --- drivers/video/console/fbcon.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/video/console/fbcon.c b/drivers/video/console/fbcon.c index 9c092b8d64e6..c58393402da2 100644 --- a/drivers/video/console/fbcon.c +++ b/drivers/video/console/fbcon.c @@ -823,10 +823,10 @@ static int set_con2fb_map(int unit, int newidx, int user) if (oldidx == newidx) return 0; - if (!info || fbcon_has_exited) + if (!info) return -EINVAL; - if (!err && !search_for_mapped_con()) { + if (!search_for_mapped_con() || !con_is_bound(&fb_con)) { info_idx = newidx; return fbcon_takeover(0); } From 9c7fbe2fbd1d861c50912b10b2bc3a15371a7a5e Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Wed, 23 Mar 2011 08:16:45 +0900 Subject: [PATCH 138/140] video: Move sm501fb devicetree binding documentation to a better place. Now that there is a Documentation/devicetree hierarchy, and the driver in question has no specific platform dependency, move the binding information to a more appropriate place. Signed-off-by: Paul Mundt --- .../dts-bindings/sm501.txt => devicetree/bindings/fb/sm501fb.txt} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename Documentation/{powerpc/dts-bindings/sm501.txt => devicetree/bindings/fb/sm501fb.txt} (100%) diff --git a/Documentation/powerpc/dts-bindings/sm501.txt b/Documentation/devicetree/bindings/fb/sm501fb.txt similarity index 100% rename from Documentation/powerpc/dts-bindings/sm501.txt rename to Documentation/devicetree/bindings/fb/sm501fb.txt From d958c62c0cf43bb9c7dcd9833a35335ae72856f7 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Wed, 23 Mar 2011 08:22:41 +0900 Subject: [PATCH 139/140] MAINTAINERS: Add file pattern for fb dt bindings. Now that Documentation/devicetree/bindings/fb/ exists, make sure it's also matched by the default framebuffer entry. Signed-off-by: Paul Mundt --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 5b28ed0b60c6..d71a5c8649cf 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2633,6 +2633,7 @@ Q: http://patchwork.kernel.org/project/linux-fbdev/list/ T: git git://git.kernel.org/pub/scm/linux/kernel/git/lethal/fbdev-2.6.git S: Orphan F: Documentation/fb/ +F: Documentation/devicetree/bindings/fb/ F: drivers/video/ F: include/video/ F: include/linux/fb.h From 56be1416453c31d32f984328b5193489ab63ffcf Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Wed, 23 Mar 2011 08:29:07 +0900 Subject: [PATCH 140/140] MAINTAINERS: de-orphan fbdev. It's been a few kernel versions now without any unexpected surprises, so tentatively bump up the support status. Signed-off-by: Paul Mundt --- MAINTAINERS | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index d71a5c8649cf..c7acfb0ef9ee 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2627,11 +2627,12 @@ F: drivers/net/wan/dlci.c F: drivers/net/wan/sdla.c FRAMEBUFFER LAYER +M: Paul Mundt L: linux-fbdev@vger.kernel.org W: http://linux-fbdev.sourceforge.net/ Q: http://patchwork.kernel.org/project/linux-fbdev/list/ T: git git://git.kernel.org/pub/scm/linux/kernel/git/lethal/fbdev-2.6.git -S: Orphan +S: Maintained F: Documentation/fb/ F: Documentation/devicetree/bindings/fb/ F: drivers/video/