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drm/nouveau/pmu/gm200-: use alternate falcon reset sequence

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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Link: https://gitlab.freedesktop.org/drm/nouveau/-/merge_requests/10
This commit is contained in:
Ben Skeggs 2021-02-25 14:54:59 +10:00 committed by Karol Herbst
parent 1d2271d2fb
commit 4cdd2450bf
6 changed files with 41 additions and 6 deletions
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8
drivers/gpu/drm/nouveau/nvkm/falcon/base.c
View File

@ -117,8 +117,12 @@ nvkm_falcon_disable(struct nvkm_falcon *falcon)
int
nvkm_falcon_reset(struct nvkm_falcon *falcon)
{
nvkm_falcon_disable(falcon);
return nvkm_falcon_enable(falcon);
if (!falcon->func->reset) {
nvkm_falcon_disable(falcon);
return nvkm_falcon_enable(falcon);
}
return falcon->func->reset(falcon);
}
int

31
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm200.c
View File

@ -23,9 +23,38 @@
*/
#include "priv.h"
static int
gm200_pmu_flcn_reset(struct nvkm_falcon *falcon)
{
struct nvkm_pmu *pmu = container_of(falcon, typeof(*pmu), falcon);
nvkm_falcon_wr32(falcon, 0x014, 0x0000ffff);
pmu->func->reset(pmu);
return nvkm_falcon_enable(falcon);
}
const struct nvkm_falcon_func
gm200_pmu_flcn = {
.debug = 0xc08,
.fbif = 0xe00,
.load_imem = nvkm_falcon_v1_load_imem,
.load_dmem = nvkm_falcon_v1_load_dmem,
.read_dmem = nvkm_falcon_v1_read_dmem,
.bind_context = nvkm_falcon_v1_bind_context,
.wait_for_halt = nvkm_falcon_v1_wait_for_halt,
.clear_interrupt = nvkm_falcon_v1_clear_interrupt,
.set_start_addr = nvkm_falcon_v1_set_start_addr,
.start = nvkm_falcon_v1_start,
.enable = nvkm_falcon_v1_enable,
.disable = nvkm_falcon_v1_disable,
.reset = gm200_pmu_flcn_reset,
.cmdq = { 0x4a0, 0x4b0, 4 },
.msgq = { 0x4c8, 0x4cc, 0 },
};
static const struct nvkm_pmu_func
gm200_pmu = {
.flcn = &gt215_pmu_flcn,
.flcn = &gm200_pmu_flcn,
.enabled = gf100_pmu_enabled,
.reset = gf100_pmu_reset,
};

2
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c
View File

@ -211,7 +211,7 @@ gm20b_pmu_recv(struct nvkm_pmu *pmu)
static const struct nvkm_pmu_func
gm20b_pmu = {
.flcn = &gt215_pmu_flcn,
.flcn = &gm200_pmu_flcn,
.enabled = gf100_pmu_enabled,
.intr = gt215_pmu_intr,
.recv = gm20b_pmu_recv,

2
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp102.c
View File

@ -39,7 +39,7 @@ gp102_pmu_enabled(struct nvkm_pmu *pmu)
static const struct nvkm_pmu_func
gp102_pmu = {
.flcn = &gt215_pmu_flcn,
.flcn = &gm200_pmu_flcn,
.enabled = gp102_pmu_enabled,
.reset = gp102_pmu_reset,
};

2
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp10b.c
View File

@ -78,7 +78,7 @@ gp10b_pmu_acr = {
static const struct nvkm_pmu_func
gp10b_pmu = {
.flcn = &gt215_pmu_flcn,
.flcn = &gm200_pmu_flcn,
.enabled = gf100_pmu_enabled,
.intr = gt215_pmu_intr,
.recv = gm20b_pmu_recv,

2
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h
View File

@ -44,6 +44,8 @@ void gf100_pmu_reset(struct nvkm_pmu *);
void gk110_pmu_pgob(struct nvkm_pmu *, bool);
extern const struct nvkm_falcon_func gm200_pmu_flcn;
void gm20b_pmu_acr_bld_patch(struct nvkm_acr *, u32, s64);
void gm20b_pmu_acr_bld_write(struct nvkm_acr *, u32, struct nvkm_acr_lsfw *);
int gm20b_pmu_acr_boot(struct nvkm_falcon *);