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drm/i915/mtl: Introduce FBC B

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MTL introduces a second FBC engine. The two FBC engines can
operate entirely independently, FBC A serving pipe A and
FBC B serving pipe B.

The one place where things might go a bit wrong is the CFB
allocation from stolen. We might have to consider some change
to the allocation strategy to have a better chance of both
engines being able to allocate its CFB. Maybe FBC A should
allocate bottom up and FBC B top down, or something? For the
moment the allocation strategy is DRM_MM_INSERT_BEST for both.

Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220817122624.213889-1-jani.nikula@intel.com
This commit is contained in:
Ville Syrjälä 2022-08-17 15:26:24 +03:00 committed by Jani Nikula
parent f386832509
commit 4cf05a4d71
2 changed files with 3 additions and 1 deletions
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1
drivers/gpu/drm/i915/display/intel_fbc.h
View File

@ -19,6 +19,7 @@ struct intel_plane_state;
enum intel_fbc_id {
INTEL_FBC_A,
INTEL_FBC_B,
I915_MAX_FBCS,
};

3
drivers/gpu/drm/i915/i915_pci.c
View File

@ -1111,7 +1111,8 @@ static const struct intel_device_info pvc_info = {
#define XE_LPDP_FEATURES \
XE_LPD_FEATURES, \
.display.ver = 14, \
.display.has_cdclk_crawl = 1
.display.has_cdclk_crawl = 1, \
.display.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B)
__maybe_unused
static const struct intel_device_info mtl_info = {