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drm/xe: Add missing DG2 engine workarounds

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Synchronize with i915 the DG2 gt workarounds as of
commit 4d14d7717f19 ("drm/i915/selftest: Fix ktime_get() and h/w access
order").

A few simplifications were done when the WA should be applied to
some steps of a subplatform and all the steppings of the other
subplatforms. This happened with Wa_1509727124, Wa_22012856258 and a few
others. In figure the pre-production steppings will be removed, so this
can be already simplified a little bit.

v2:
  - Make 1308578152 conditional on first gslice fused off
  - Add the missing Wa_1608949956/Wa_14010198302 (Matt Roper)
v3:
  - Do not duplicate the implementation of 18019627453 since it's
    already covered by other WA numbers in graphics versions 1200 and
    1210

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20230314003012.2600353-10-lucas.demarchi@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Lucas De Marchi 2023-03-13 17:30:07 -07:00 committed by Rodrigo Vivi
parent 911aeb0f61
commit 4d5ab12163
2 changed files with 214 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

27
drivers/gpu/drm/xe/regs/xe_gt_regs.h
View File

@ -48,6 +48,7 @@
#define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec)
#define FF_DOP_CLOCK_GATE_DISABLE REG_BIT(1)
#define GEN12_REPLAY_MODE_GRANULARITY REG_BIT(0)
#define PS_INVOCATION_COUNT _MMIO(0x2348)
@ -91,6 +92,9 @@
#define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11)
#define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE REG_BIT(9)
#define VFG_PREEMPTION_CHICKEN _MMIO(0x83b4)
#define POLYGON_TRIFAN_LINELOOP_DISABLE REG_BIT(4)
#define XEHP_SQCM MCR_REG(0x8724)
#define EN_32B_ACCESS REG_BIT(30)
@ -248,8 +252,13 @@
#define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
#define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)
#define GEN9_HALF_SLICE_CHICKEN7 MCR_REG(0xe194)
#define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15)
#define CACHE_MODE_SS MCR_REG(0xe420)
#define ENABLE_EU_COUNT_FOR_TDL_FLUSH REG_BIT(10)
#define DISABLE_ECC REG_BIT(5)
#define ENABLE_PREFETCH_INTO_IC REG_BIT(3)
#define GEN9_ROW_CHICKEN4 MCR_REG(0xe48c)
#define GEN12_DISABLE_GRF_CLEAR REG_BIT(13)
@ -260,6 +269,10 @@
#define THREAD_EX_ARB_MODE REG_GENMASK(3, 2)
#define THREAD_EX_ARB_MODE_RR_AFTER_DEP REG_FIELD_PREP(THREAD_EX_ARB_MODE, 0x2)
#define GEN8_ROW_CHICKEN MCR_REG(0xe4f0)
#define UGM_BACKUP_MODE REG_BIT(13)
#define MDQ_ARBITRATION_MODE REG_BIT(12)
#define GEN8_ROW_CHICKEN2 MCR_REG(0xe4f4)
#define GEN12_DISABLE_READ_SUPPRESSION REG_BIT(15)
#define GEN12_DISABLE_EARLY_READ REG_BIT(14)
@ -267,8 +280,22 @@
#define GEN12_PUSH_CONST_DEREF_HOLD_DIS REG_BIT(8)
#define GEN12_DISABLE_DOP_GATING REG_BIT(0)
#define XEHP_HDC_CHICKEN0 MCR_REG(0xe5f0)
#define LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK REG_GENMASK(13, 11)
#define RT_CTRL MCR_REG(0xe530)
#define DIS_NULL_QUERY REG_BIT(10)
#define LSC_CHICKEN_BIT_0 MCR_REG(0xe7c8)
#define DISABLE_D8_D16_COASLESCE REG_BIT(30)
#define FORCE_1_SUB_MESSAGE_PER_FRAGMENT REG_BIT(15)
#define LSC_CHICKEN_BIT_0_UDW MCR_REG(0xe7c8 + 4)
#define DIS_CHAIN_2XSIMD8 REG_BIT(55 - 32)
#define FORCE_SLM_FENCE_SCOPE_TO_TILE REG_BIT(42 - 32)
#define FORCE_UGM_FENCE_SCOPE_TO_TILE REG_BIT(41 - 32)
#define MAXREQS_PER_BANK REG_GENMASK(39 - 32, 37 - 32)
#define DISABLE_128B_EVICTION_COMMAND_UDW REG_BIT(36 - 32)
#define SARB_CHICKEN1 MCR_REG(0xe90c)
#define COMP_CKN_IN REG_GENMASK(30, 29)

193
drivers/gpu/drm/xe/xe_wa.c
View File

@ -91,6 +91,9 @@
#define _MMIO(x) _XE_RTP_REG(x)
#define MCR_REG(x) _XE_RTP_MCR_REG(x)
__diag_push();
__diag_ignore_all("-Woverride-init", "Allow field overrides in table");
static const struct xe_rtp_entry gt_was[] = {
{ XE_RTP_NAME("14011060649"),
XE_RTP_RULES(MEDIA_VERSION_RANGE(1200, 1255),
@ -259,8 +262,8 @@ static const struct xe_rtp_entry engine_was[] = {
XE_RTP_ACTIONS(SET(GEN8_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ,
XE_RTP_ACTION_FLAG(MASKED_REG)))
},
{ XE_RTP_NAME("14010826681, 1606700617, 22010271021"),
XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
{ XE_RTP_NAME("14010826681, 1606700617, 22010271021, 18019627453"),
XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1255), ENGINE_CLASS(RENDER)),
XE_RTP_ACTIONS(SET(GEN9_CS_DEBUG_MODE1, FF_DOP_CLOCK_GATE_DISABLE,
XE_RTP_ACTION_FLAG(MASKED_REG)))
},
@ -298,16 +301,192 @@ static const struct xe_rtp_entry engine_was[] = {
/* DG2 */
{ XE_RTP_NAME("22013037850"),
XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW,
DISABLE_128B_EVICTION_COMMAND_UDW))
},
{ XE_RTP_NAME("22014226127"),
XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE))
},
{ XE_RTP_NAME("18017747507"),
XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
XE_RTP_ACTIONS(SET(VFG_PREEMPTION_CHICKEN,
POLYGON_TRIFAN_LINELOOP_DISABLE,
XE_RTP_ACTION_FLAG(MASKED_REG)))
},
{ XE_RTP_NAME("22012826095, 22013059131"),
XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(B0, C0),
FUNC(xe_rtp_match_first_render_or_compute)),
XE_RTP_ACTIONS(FIELD_SET(LSC_CHICKEN_BIT_0_UDW,
MAXREQS_PER_BANK,
REG_FIELD_PREP(MAXREQS_PER_BANK, 2)))
},
{ XE_RTP_NAME("22012826095, 22013059131"),
XE_RTP_RULES(SUBPLATFORM(DG2, G11),
FUNC(xe_rtp_match_first_render_or_compute)),
XE_RTP_ACTIONS(FIELD_SET(LSC_CHICKEN_BIT_0_UDW,
MAXREQS_PER_BANK,
REG_FIELD_PREP(MAXREQS_PER_BANK, 2)))
},
{ XE_RTP_NAME("22013059131"),
XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(B0, C0),
FUNC(xe_rtp_match_first_render_or_compute)),
XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, FORCE_1_SUB_MESSAGE_PER_FRAGMENT))
},
{ XE_RTP_NAME("22013059131"),
XE_RTP_RULES(SUBPLATFORM(DG2, G11),
FUNC(xe_rtp_match_first_render_or_compute)),
XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, FORCE_1_SUB_MESSAGE_PER_FRAGMENT))
},
{ XE_RTP_NAME("14010918519"),
XE_RTP_RULES(SUBPLATFORM(DG2, G10),
FUNC(xe_rtp_match_first_render_or_compute)),
XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0,
FORCE_SLM_FENCE_SCOPE_TO_TILE |
FORCE_UGM_FENCE_SCOPE_TO_TILE,
/*
* Ignore read back as it always returns 0 in these
* steps
*/
.read_mask = 0))
},
{ XE_RTP_NAME("14015227452"),
XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
XE_RTP_RULES(PLATFORM(DG2),
FUNC(xe_rtp_match_first_render_or_compute)),
XE_RTP_ACTIONS(SET(GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE,
XE_RTP_ACTION_FLAG(MASKED_REG)))
},
{ XE_RTP_NAME("18019627453"),
XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
XE_RTP_ACTIONS(SET(GEN9_CS_DEBUG_MODE1, FF_DOP_CLOCK_GATE_DISABLE,
{ XE_RTP_NAME("16015675438"),
XE_RTP_RULES(PLATFORM(DG2),
FUNC(xe_rtp_match_first_render_or_compute)),
XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN2,
PERF_FIX_BALANCING_CFE_DISABLE,
XE_RTP_ACTION_FLAG(MASKED_REG)))
},
{ XE_RTP_NAME("16011620976, 22015475538"),
XE_RTP_RULES(PLATFORM(DG2),
FUNC(xe_rtp_match_first_render_or_compute)),
XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8))
},
{ XE_RTP_NAME("22012654132"),
XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(A0, C0),
FUNC(xe_rtp_match_first_render_or_compute)),
XE_RTP_ACTIONS(SET(CACHE_MODE_SS, ENABLE_PREFETCH_INTO_IC,
XE_RTP_ACTION_FLAG(MASKED_REG),
/*
* Register can't be read back for verification on
* DG2 due to Wa_14012342262
*/
.read_mask = 0))
},
{ XE_RTP_NAME("22012654132"),
XE_RTP_RULES(SUBPLATFORM(DG2, G11),
FUNC(xe_rtp_match_first_render_or_compute)),
XE_RTP_ACTIONS(SET(CACHE_MODE_SS, ENABLE_PREFETCH_INTO_IC,
XE_RTP_ACTION_FLAG(MASKED_REG),
/*
* Register can't be read back for verification on
* DG2 due to Wa_14012342262
*/
.read_mask = 0))
},
{ XE_RTP_NAME("1509727124"),
XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
XE_RTP_ACTIONS(SET(GEN10_SAMPLER_MODE, SC_DISABLE_POWER_OPTIMIZATION_EBB,
XE_RTP_ACTION_FLAG(MASKED_REG)))
},
{ XE_RTP_NAME("22012856258"),
XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
XE_RTP_ACTIONS(SET(GEN8_ROW_CHICKEN2, GEN12_DISABLE_READ_SUPPRESSION,
XE_RTP_ACTION_FLAG(MASKED_REG)))
},
{ XE_RTP_NAME("14013392000"),
XE_RTP_RULES(SUBPLATFORM(DG2, G11), STEP(A0, B0), ENGINE_CLASS(RENDER)),
XE_RTP_ACTIONS(SET(GEN8_ROW_CHICKEN2, GEN12_ENABLE_LARGE_GRF_MODE,
XE_RTP_ACTION_FLAG(MASKED_REG)))
},
{ XE_RTP_NAME("14012419201"),
XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(A0, B0), ENGINE_CLASS(RENDER)),
XE_RTP_ACTIONS(SET(GEN9_ROW_CHICKEN4,
GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX,
XE_RTP_ACTION_FLAG(MASKED_REG)))
},
{ XE_RTP_NAME("14012419201"),
XE_RTP_RULES(SUBPLATFORM(DG2, G11), STEP(A0, B0), ENGINE_CLASS(RENDER)),
XE_RTP_ACTIONS(SET(GEN9_ROW_CHICKEN4,
GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX,
XE_RTP_ACTION_FLAG(MASKED_REG)))
},
{ XE_RTP_NAME("1308578152"),
XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(B0, C0), ENGINE_CLASS(RENDER),
FUNC(xe_rtp_match_first_gslice_fused_off)),
XE_RTP_ACTIONS(CLR(GEN9_CS_DEBUG_MODE1,
GEN12_REPLAY_MODE_GRANULARITY,
XE_RTP_ACTION_FLAG(MASKED_REG)))
},
{ XE_RTP_NAME("22010960976, 14013347512"),
XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
XE_RTP_ACTIONS(CLR(XEHP_HDC_CHICKEN0,
LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK,
XE_RTP_ACTION_FLAG(MASKED_REG)))
},
{ XE_RTP_NAME("1608949956, 14010198302"),
XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
XE_RTP_ACTIONS(SET(GEN8_ROW_CHICKEN,
MDQ_ARBITRATION_MODE | UGM_BACKUP_MODE,
XE_RTP_ACTION_FLAG(MASKED_REG)))
},
{ XE_RTP_NAME("22010430635"),
XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(A0, B0), ENGINE_CLASS(RENDER)),
XE_RTP_ACTIONS(SET(GEN9_ROW_CHICKEN4,
GEN12_DISABLE_GRF_CLEAR,
XE_RTP_ACTION_FLAG(MASKED_REG)))
},
{ XE_RTP_NAME("14013202645"),
XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(B0, C0), ENGINE_CLASS(RENDER)),
XE_RTP_ACTIONS(SET(RT_CTRL, DIS_NULL_QUERY))
},
{ XE_RTP_NAME("14013202645"),
XE_RTP_RULES(SUBPLATFORM(DG2, G11), STEP(A0, B0), ENGINE_CLASS(RENDER)),
XE_RTP_ACTIONS(SET(RT_CTRL, DIS_NULL_QUERY))
},
{ XE_RTP_NAME("22012532006"),
XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(A0, C0), ENGINE_CLASS(RENDER)),
XE_RTP_ACTIONS(SET(GEN9_HALF_SLICE_CHICKEN7,
DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA,
XE_RTP_ACTION_FLAG(MASKED_REG)))
},
{ XE_RTP_NAME("22012532006"),
XE_RTP_RULES(SUBPLATFORM(DG2, G11), STEP(A0, B0), ENGINE_CLASS(RENDER)),
XE_RTP_ACTIONS(SET(GEN9_HALF_SLICE_CHICKEN7,
DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA,
XE_RTP_ACTION_FLAG(MASKED_REG)))
},
{ XE_RTP_NAME("22014600077"),
XE_RTP_RULES(SUBPLATFORM(DG2, G11), STEP(B0, FOREVER),
ENGINE_CLASS(RENDER)),
XE_RTP_ACTIONS(SET(CACHE_MODE_SS,
ENABLE_EU_COUNT_FOR_TDL_FLUSH,
XE_RTP_ACTION_FLAG(MASKED_REG),
/*
* Wa_14012342262 write-only reg, so skip
* verification
*/
.read_mask = 0))
},
{ XE_RTP_NAME("22014600077"),
XE_RTP_RULES(SUBPLATFORM(DG2, G10), ENGINE_CLASS(RENDER)),
XE_RTP_ACTIONS(SET(CACHE_MODE_SS,
ENABLE_EU_COUNT_FOR_TDL_FLUSH,
XE_RTP_ACTION_FLAG(MASKED_REG),
/*
* Wa_14012342262 write-only reg, so skip
* verification
*/
.read_mask = 0))
},
/* PVC */
@ -365,6 +544,8 @@ static const struct xe_rtp_entry lrc_was[] = {
{}
};
__diag_pop();
/**
* xe_wa_process_gt - process GT workaround table
* @gt: GT instance to process workarounds for