drm/amd/display: Adding support for VESA SCR
[HOW&WHY] Write DPCD 721 bit 7 to high, and the appropriate luminance level to DPCD 734-736 if bit 4 from DPCD register 734 is high, indicating that the panel luminance control is enabled from the panel side. Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Iswara Nagulendran <Iswara.Nagulendran@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -566,6 +566,12 @@ struct dpcd_amd_device_id {
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uint8_t dal_version_byte2;
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};
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struct target_luminance_value {
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uint8_t byte0;
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uint8_t byte1;
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uint8_t byte2;
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};
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struct dpcd_source_backlight_set {
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struct {
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uint8_t byte0;
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@ -1225,6 +1231,7 @@ struct dpcd_caps {
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union dp_main_line_channel_coding_cap channel_coding_cap;
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union dp_sink_video_fallback_formats fallback_formats;
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union dp_fec_capability1 fec_cap1;
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bool panel_luminance_control;
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union dp_cable_id cable_id;
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uint8_t edp_rev;
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union edp_alpm_caps alpm_caps;
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@ -1450,7 +1450,8 @@ bool read_is_mst_supported(struct dc_link *link)
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*/
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static bool dpcd_read_sink_ext_caps(struct dc_link *link)
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{
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uint8_t dpcd_data;
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uint8_t dpcd_data = 0;
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uint8_t edp_general_cap2 = 0;
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if (!link)
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return false;
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@ -1459,6 +1460,12 @@ static bool dpcd_read_sink_ext_caps(struct dc_link *link)
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return false;
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link->dpcd_sink_ext_caps.raw = dpcd_data;
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if (core_link_read_dpcd(link, DP_EDP_GENERAL_CAP_2, &edp_general_cap2, 1) != DC_OK)
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return false;
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link->dpcd_caps.panel_luminance_control = (edp_general_cap2 & DP_EDP_PANEL_LUMINANCE_CONTROL_CAPABLE) != 0;
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return true;
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}
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@ -164,14 +164,35 @@ bool edp_set_backlight_level_nits(struct dc_link *link,
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*(uint16_t *)&dpcd_backlight_set.backlight_transition_time_ms = (uint16_t)transition_time_in_ms;
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if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
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if (!link->dpcd_caps.panel_luminance_control) {
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if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
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(uint8_t *)(&dpcd_backlight_set),
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sizeof(dpcd_backlight_set)) != DC_OK)
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return false;
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return false;
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if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_CONTROL,
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if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_CONTROL,
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&backlight_control, 1) != DC_OK)
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return false;
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return false;
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} else {
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const uint8_t backlight_enable = DP_EDP_PANEL_LUMINANCE_CONTROL_ENABLE;
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struct target_luminance_value *target_luminance = NULL;
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//if target luminance value is greater than 24 bits, clip the value to 24 bits
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if (backlight_millinits > 0xFFFFFF)
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backlight_millinits = 0xFFFFFF;
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target_luminance = (struct target_luminance_value *)&backlight_millinits;
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if (core_link_write_dpcd(link, DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
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&backlight_enable,
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sizeof(backlight_enable)) != DC_OK)
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return false;
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if (core_link_write_dpcd(link, DP_EDP_PANEL_TARGET_LUMINANCE_VALUE,
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(uint8_t *)(target_luminance),
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sizeof(struct target_luminance_value)) != DC_OK)
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return false;
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}
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return true;
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}
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@ -983,6 +983,7 @@
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#define DP_EDP_GENERAL_CAP_2 0x703
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# define DP_EDP_OVERDRIVE_ENGINE_ENABLED (1 << 0)
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# define DP_EDP_PANEL_LUMINANCE_CONTROL_CAPABLE (1 << 4)
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#define DP_EDP_GENERAL_CAP_3 0x704 /* eDP 1.4 */
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# define DP_EDP_X_REGION_CAP_MASK (0xf << 0)
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@ -1008,6 +1009,7 @@
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# define DP_EDP_DYNAMIC_BACKLIGHT_ENABLE (1 << 4)
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# define DP_EDP_REGIONAL_BACKLIGHT_ENABLE (1 << 5)
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# define DP_EDP_UPDATE_REGION_BRIGHTNESS (1 << 6) /* eDP 1.4 */
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# define DP_EDP_PANEL_LUMINANCE_CONTROL_ENABLE (1 << 7)
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#define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722
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#define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723
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@ -1032,6 +1034,7 @@
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#define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732
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#define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733
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#define DP_EDP_PANEL_TARGET_LUMINANCE_VALUE 0x734
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#define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */
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#define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */
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