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ASoC: mediatek: remove soft reset and add second I2S clock

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To improve I2S flow, this patch removes soft reset and adds second
I2S clock to use.

Signed-off-by: PC Liao <pc.liao@mediatek.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
PC Liao 2016-02-23 16:20:24 +08:00 committed by Mark Brown
parent 0f83f9296d
commit 4d7cb66c8f
1 changed files with 6 additions and 8 deletions
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14
sound/soc/mediatek/mtk-afe-pcm.c
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@ -283,20 +283,13 @@ static void mtk_afe_set_i2s_enable(struct mtk_afe *afe, bool enable)
regmap_read(afe->regmap, AFE_I2S_CON2, &val); regmap_read(afe->regmap, AFE_I2S_CON2, &val);
if (!!(val & AFE_I2S_CON2_EN) == enable) if (!!(val & AFE_I2S_CON2_EN) == enable)
return; /* must skip soft reset */ return;
/* I2S soft reset begin */
regmap_update_bits(afe->regmap, AUDIO_TOP_CON1, 0x4, 0x4);
/* input */ /* input */
regmap_update_bits(afe->regmap, AFE_I2S_CON2, 0x1, enable); regmap_update_bits(afe->regmap, AFE_I2S_CON2, 0x1, enable);
/* output */ /* output */
regmap_update_bits(afe->regmap, AFE_I2S_CON1, 0x1, enable); regmap_update_bits(afe->regmap, AFE_I2S_CON1, 0x1, enable);
/* I2S soft reset end */
udelay(1);
regmap_update_bits(afe->regmap, AUDIO_TOP_CON1, 0x4, 0);
} }
static int mtk_afe_dais_enable_clks(struct mtk_afe *afe, static int mtk_afe_dais_enable_clks(struct mtk_afe *afe,
@ -365,6 +358,7 @@ static int mtk_afe_i2s_startup(struct snd_pcm_substream *substream,
return 0; return 0;
mtk_afe_dais_enable_clks(afe, afe->clocks[MTK_CLK_I2S1_M], NULL); mtk_afe_dais_enable_clks(afe, afe->clocks[MTK_CLK_I2S1_M], NULL);
mtk_afe_dais_enable_clks(afe, afe->clocks[MTK_CLK_I2S2_M], NULL);
regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M, 0); AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M, 0);
return 0; return 0;
@ -384,6 +378,7 @@ static void mtk_afe_i2s_shutdown(struct snd_pcm_substream *substream,
AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M, AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M,
AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M); AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M);
mtk_afe_dais_disable_clks(afe, afe->clocks[MTK_CLK_I2S1_M], NULL); mtk_afe_dais_disable_clks(afe, afe->clocks[MTK_CLK_I2S1_M], NULL);
mtk_afe_dais_disable_clks(afe, afe->clocks[MTK_CLK_I2S2_M], NULL);
} }
static int mtk_afe_i2s_prepare(struct snd_pcm_substream *substream, static int mtk_afe_i2s_prepare(struct snd_pcm_substream *substream,
@ -397,6 +392,9 @@ static int mtk_afe_i2s_prepare(struct snd_pcm_substream *substream,
mtk_afe_dais_set_clks(afe, mtk_afe_dais_set_clks(afe,
afe->clocks[MTK_CLK_I2S1_M], runtime->rate * 256, afe->clocks[MTK_CLK_I2S1_M], runtime->rate * 256,
NULL, 0); NULL, 0);
mtk_afe_dais_set_clks(afe,
afe->clocks[MTK_CLK_I2S2_M], runtime->rate * 256,
NULL, 0);
/* config I2S */ /* config I2S */
ret = mtk_afe_set_i2s(afe, substream->runtime->rate); ret = mtk_afe_set_i2s(afe, substream->runtime->rate);
if (ret) if (ret)