Merge branch 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm
Pull ARM fixes from Russell King: "A number of ARM updates for -rc, covering mostly ARM specific code, but with one change to modpost.c to allow Thumb section mismatches to be detected. ARM changes include reporting when an attempt is made to boot a LPAE kernel on hardware which does not support LPAE, rather than just being silent about it. A number of other minor fixes are included too" * 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm: ARM: 7992/1: boot: compressed: ignore bswapsdi2.S ARM: 7991/1: sa1100: fix compile problem on Collie ARM: fix noMMU kallsyms symbol filtering ARM: 7980/1: kernel: improve error message when LPAE config doesn't match CPU ARM: 7964/1: Detect section mismatches in thumb relocations ARM: 7963/1: mm: report both sections from PMD
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commit
4d7eaa12f3
@ -1578,6 +1578,7 @@ config BL_SWITCHER_DUMMY_IF
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choice
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prompt "Memory split"
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depends on MMU
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default VMSPLIT_3G
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help
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Select the desired split between kernel and user memory.
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@ -1595,6 +1596,7 @@ endchoice
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config PAGE_OFFSET
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hex
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default PHYS_OFFSET if !MMU
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default 0x40000000 if VMSPLIT_1G
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default 0x80000000 if VMSPLIT_2G
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default 0xC0000000
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1
arch/arm/boot/compressed/.gitignore
vendored
1
arch/arm/boot/compressed/.gitignore
vendored
@ -1,4 +1,5 @@
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ashldi3.S
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bswapsdi2.S
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font.c
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lib1funcs.S
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hyp-stub.S
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@ -30,14 +30,15 @@
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*/
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#define UL(x) _AC(x, UL)
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/* PAGE_OFFSET - the virtual address of the start of the kernel image */
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#define PAGE_OFFSET UL(CONFIG_PAGE_OFFSET)
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#ifdef CONFIG_MMU
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/*
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* PAGE_OFFSET - the virtual address of the start of the kernel image
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* TASK_SIZE - the maximum size of a user space task.
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* TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area
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*/
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#define PAGE_OFFSET UL(CONFIG_PAGE_OFFSET)
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#define TASK_SIZE (UL(CONFIG_PAGE_OFFSET) - UL(SZ_16M))
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#define TASK_UNMAPPED_BASE ALIGN(TASK_SIZE / 3, SZ_16M)
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@ -104,10 +105,6 @@
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#define END_MEM (UL(CONFIG_DRAM_BASE) + CONFIG_DRAM_SIZE)
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#endif
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#ifndef PAGE_OFFSET
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#define PAGE_OFFSET PLAT_PHYS_OFFSET
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#endif
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/*
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* The module can be at any place in ram in nommu mode.
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*/
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@ -177,6 +177,18 @@ __lookup_processor_type_data:
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.long __proc_info_end
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.size __lookup_processor_type_data, . - __lookup_processor_type_data
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__error_lpae:
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#ifdef CONFIG_DEBUG_LL
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adr r0, str_lpae
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bl printascii
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b __error
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str_lpae: .asciz "\nError: Kernel with LPAE support, but CPU does not support LPAE.\n"
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#else
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b __error
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#endif
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.align
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ENDPROC(__error_lpae)
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__error_p:
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#ifdef CONFIG_DEBUG_LL
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adr r0, str_p1
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@ -102,7 +102,7 @@ ENTRY(stext)
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and r3, r3, #0xf @ extract VMSA support
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cmp r3, #5 @ long-descriptor translation table format?
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THUMB( it lo ) @ force fixup-able long branch encoding
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blo __error_p @ only classic page table format
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blo __error_lpae @ only classic page table format
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#endif
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#ifndef CONFIG_XIP_KERNEL
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@ -13,6 +13,8 @@
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#ifndef __ASM_ARCH_COLLIE_H
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#define __ASM_ARCH_COLLIE_H
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#include "hardware.h" /* Gives GPIO_MAX */
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extern void locomolcd_power(int on);
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#define COLLIE_SCOOP_GPIO_BASE (GPIO_MAX + 1)
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@ -264,6 +264,9 @@ static void walk_pmd(struct pg_state *st, pud_t *pud, unsigned long start)
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note_page(st, addr, 3, pmd_val(*pmd));
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else
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walk_pte(st, pmd, addr);
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if (SECTION_SIZE < PMD_SIZE && pmd_large(pmd[1]))
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note_page(st, addr + SECTION_SIZE, 3, pmd_val(pmd[1]));
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}
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}
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@ -1502,6 +1502,16 @@ static int addend_386_rel(struct elf_info *elf, Elf_Shdr *sechdr, Elf_Rela *r)
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#define R_ARM_JUMP24 29
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#endif
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#ifndef R_ARM_THM_CALL
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#define R_ARM_THM_CALL 10
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#endif
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#ifndef R_ARM_THM_JUMP24
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#define R_ARM_THM_JUMP24 30
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#endif
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#ifndef R_ARM_THM_JUMP19
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#define R_ARM_THM_JUMP19 51
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#endif
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static int addend_arm_rel(struct elf_info *elf, Elf_Shdr *sechdr, Elf_Rela *r)
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{
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unsigned int r_typ = ELF_R_TYPE(r->r_info);
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@ -1515,6 +1525,9 @@ static int addend_arm_rel(struct elf_info *elf, Elf_Shdr *sechdr, Elf_Rela *r)
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case R_ARM_PC24:
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case R_ARM_CALL:
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case R_ARM_JUMP24:
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case R_ARM_THM_CALL:
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case R_ARM_THM_JUMP24:
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case R_ARM_THM_JUMP19:
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/* From ARM ABI: ((S + A) | T) - P */
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r->r_addend = (int)(long)(elf->hdr +
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sechdr->sh_offset +
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