perf/x86: Implement IBS pmu control ops
Add code to control the IBS pmu. We need to maintain per-cpu states. Since some states are used and changed by the nmi handler, access to these states must be atomic. Signed-off-by: Robert Richter <robert.richter@amd.com> Acked-by: Peter Zijlstra <peterz@infradead.org> Cc: Stephane Eranian <eranian@google.com> Link: http://lkml.kernel.org/r/1323968199-9326-4-git-send-email-robert.richter@amd.com Signed-off-by: Ingo Molnar <mingo@elte.hu>
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@ -24,6 +24,19 @@ static u32 ibs_caps;
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#define IBS_FETCH_CONFIG_MASK (IBS_FETCH_RAND_EN | IBS_FETCH_MAX_CNT)
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#define IBS_OP_CONFIG_MASK IBS_OP_MAX_CNT
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enum ibs_states {
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IBS_ENABLED = 0,
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IBS_STARTED = 1,
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IBS_STOPPING = 2,
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IBS_MAX_STATES,
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};
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struct cpu_perf_ibs {
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struct perf_event *event;
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unsigned long state[BITS_TO_LONGS(IBS_MAX_STATES)];
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};
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struct perf_ibs {
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struct pmu pmu;
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unsigned int msr;
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@ -33,6 +46,7 @@ struct perf_ibs {
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u64 valid_mask;
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unsigned long offset_mask[1];
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int offset_max;
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struct cpu_perf_ibs __percpu *pcpu;
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};
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struct perf_ibs_data {
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@ -97,15 +111,66 @@ static int perf_ibs_init(struct perf_event *event)
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return 0;
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}
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static void perf_ibs_start(struct perf_event *event, int flags)
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{
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struct hw_perf_event *hwc = &event->hw;
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struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
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struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
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if (test_and_set_bit(IBS_STARTED, pcpu->state))
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return;
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wrmsrl(hwc->config_base, hwc->config | perf_ibs->enable_mask);
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}
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static void perf_ibs_stop(struct perf_event *event, int flags)
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{
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struct hw_perf_event *hwc = &event->hw;
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struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
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struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
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u64 val;
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if (!test_and_clear_bit(IBS_STARTED, pcpu->state))
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return;
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set_bit(IBS_STOPPING, pcpu->state);
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rdmsrl(hwc->config_base, val);
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val &= ~perf_ibs->enable_mask;
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wrmsrl(hwc->config_base, val);
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}
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static int perf_ibs_add(struct perf_event *event, int flags)
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{
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struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
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struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
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if (test_and_set_bit(IBS_ENABLED, pcpu->state))
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return -ENOSPC;
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pcpu->event = event;
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if (flags & PERF_EF_START)
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perf_ibs_start(event, PERF_EF_RELOAD);
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return 0;
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}
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static void perf_ibs_del(struct perf_event *event, int flags)
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{
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struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
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struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
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if (!test_and_clear_bit(IBS_ENABLED, pcpu->state))
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return;
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perf_ibs_stop(event, 0);
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pcpu->event = NULL;
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}
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static void perf_ibs_read(struct perf_event *event) { }
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static struct perf_ibs perf_ibs_fetch = {
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.pmu = {
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.task_ctx_nr = perf_invalid_context,
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@ -113,6 +178,9 @@ static struct perf_ibs perf_ibs_fetch = {
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.event_init = perf_ibs_init,
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.add = perf_ibs_add,
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.del = perf_ibs_del,
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.start = perf_ibs_start,
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.stop = perf_ibs_stop,
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.read = perf_ibs_read,
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},
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.msr = MSR_AMD64_IBSFETCHCTL,
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.config_mask = IBS_FETCH_CONFIG_MASK,
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@ -130,6 +198,9 @@ static struct perf_ibs perf_ibs_op = {
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.event_init = perf_ibs_init,
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.add = perf_ibs_add,
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.del = perf_ibs_del,
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.start = perf_ibs_start,
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.stop = perf_ibs_stop,
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.read = perf_ibs_read,
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},
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.msr = MSR_AMD64_IBSOPCTL,
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.config_mask = IBS_OP_CONFIG_MASK,
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@ -142,7 +213,8 @@ static struct perf_ibs perf_ibs_op = {
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static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs)
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{
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struct perf_event *event = NULL;
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struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
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struct perf_event *event = pcpu->event;
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struct hw_perf_event *hwc = &event->hw;
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struct perf_sample_data data;
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struct perf_raw_record raw;
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@ -152,6 +224,14 @@ static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs)
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unsigned int msr;
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u64 *buf;
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if (!test_bit(IBS_STARTED, pcpu->state)) {
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/* Catch spurious interrupts after stopping IBS: */
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if (!test_and_clear_bit(IBS_STOPPING, pcpu->state))
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return 0;
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rdmsrl(perf_ibs->msr, *ibs_data.regs);
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return (*ibs_data.regs & perf_ibs->valid_mask) ? 1 : 0;
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}
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msr = hwc->config_base;
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buf = ibs_data.regs;
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rdmsrl(msr, *buf);
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@ -200,13 +280,33 @@ perf_ibs_nmi_handler(unsigned int cmd, struct pt_regs *regs)
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return handled;
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}
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static __init int perf_ibs_pmu_init(struct perf_ibs *perf_ibs, char *name)
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{
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struct cpu_perf_ibs __percpu *pcpu;
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int ret;
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pcpu = alloc_percpu(struct cpu_perf_ibs);
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if (!pcpu)
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return -ENOMEM;
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perf_ibs->pcpu = pcpu;
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ret = perf_pmu_register(&perf_ibs->pmu, name, -1);
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if (ret) {
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perf_ibs->pcpu = NULL;
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free_percpu(pcpu);
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}
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return ret;
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}
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static __init int perf_event_ibs_init(void)
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{
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if (!ibs_caps)
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return -ENODEV; /* ibs not supported by the cpu */
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perf_pmu_register(&perf_ibs_fetch.pmu, "ibs_fetch", -1);
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perf_pmu_register(&perf_ibs_op.pmu, "ibs_op", -1);
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perf_ibs_pmu_init(&perf_ibs_fetch, "ibs_fetch");
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perf_ibs_pmu_init(&perf_ibs_op, "ibs_op");
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register_nmi_handler(NMI_LOCAL, &perf_ibs_nmi_handler, 0, "perf_ibs");
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printk(KERN_INFO "perf: AMD IBS detected (0x%08x)\n", ibs_caps);
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